--- /dev/null
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * tegra_ahub.h - Definitions for Tegra124 audio hub driver
+ * Taken from dc tegra_ahub.h
+ *
+ * Copyright 2018 Google LLC
+ * Copyright (c) 2013, NVIDIA CORPORATION. All rights reserved.
+ */
+
+#ifndef _TEGRA_AHUB_H_
+#define _TEGRA_AHUB_H_
+
+/*
+ * Each TX CIF transmits data into the XBAR. Each RX CIF can receive audio
+ * transmitted by a particular TX CIF.
+ */
+struct xbar_regs {
+ u32 apbif_rx0; /* AUDIO_APBIF_RX0, offset 0x00 */
+ u32 apbif_rx1; /* AUDIO_APBIF_RX1, offset 0x04 */
+ u32 apbif_rx2; /* AUDIO_APBIF_RX2, offset 0x08 */
+ u32 apbif_rx3; /* AUDIO_APBIF_RX3, offset 0x0C */
+
+ u32 i2s0_rx0; /* AUDIO_I2S0_RX0, offset 0x10 */
+ u32 i2s1_rx0; /* AUDIO_I2S1_RX0, offset 0x14 */
+ u32 i2s2_rx0; /* AUDIO_I2S2_RX0, offset 0x18 */
+ u32 i2s3_rx0; /* AUDIO_I2S3_RX0, offset 0x1C */
+ u32 i2s4_rx0; /* AUDIO_I2S4_RX0, offset 0x20 */
+
+ u32 dam0_rx0; /* AUDIO_DAM0_RX0, offset 0x24 */
+ u32 dam0_rx1; /* AUDIO_DAM0_RX1, offset 0x28 */
+ u32 dam1_rx0; /* AUDIO_DAM1_RX0, offset 0x2C */
+ u32 dam1_rx1; /* AUDIO_DAM1_RX1, offset 0x30 */
+ u32 dam2_rx0; /* AUDIO_DAM2_RX0, offset 0x34 */
+ u32 dam2_rx1; /* AUDIO_DAM2_RX1, offset 0x38 */
+
+ u32 spdif_rx0; /* AUDIO_SPDIF_RX0, offset 0x3C */
+ u32 spdif_rx1; /* AUDIO_SPDIF_RX1, offset 0x40 */
+
+ u32 apbif_rx4; /* AUDIO_APBIF_RX4, offset 0x44 */
+ u32 apbif_rx5; /* AUDIO_APBIF_RX4, offset 0x48 */
+ u32 apbif_rx6; /* AUDIO_APBIF_RX4, offset 0x4C */
+ u32 apbif_rx7; /* AUDIO_APBIF_RX4, offset 0x50 */
+ u32 apbif_rx8; /* AUDIO_APBIF_RX4, offset 0x54 */
+ u32 apbif_rx9; /* AUDIO_APBIF_RX4, offset 0x58 */
+
+ u32 amx0_rx0; /* AUDIO_AMX0_RX0, offset 0x5C */
+ u32 amx0_rx1; /* AUDIO_AMX0_RX1, offset 0x60 */
+ u32 amx0_rx2; /* AUDIO_AMX0_RX2, offset 0x64 */
+ u32 amx0_rx3; /* AUDIO_AMX0_RX3, offset 0x68 */
+
+ u32 adx0_rx0; /* AUDIO_ADX0_RX0, offset 0x6C */
+};
+
+struct apbif_regs {
+ u32 channel0_ctrl; /* APBIF_CHANNEL0_CTRL */
+ u32 channel0_clr; /* APBIF_CHANNEL0_CLEAR */
+ u32 channel0_stat; /* APBIF_CHANNEL0_STATUS */
+ u32 channel0_txfifo; /* APBIF_CHANNEL0_TXFIFO */
+ u32 channel0_rxfifo; /* APBIF_CHANNEL0_RXFIFO */
+ u32 channel0_cif_tx0_ctrl; /* APBIF_AUDIOCIF_TX0_CTRL */
+ u32 channel0_cif_rx0_ctrl; /* APBIF_AUDIOCIF_RX0_CTRL */
+ u32 channel0_reserved0; /* RESERVED, offset 0x1C */
+ /* ahub_channel1_ctrl/clr/stat/txfifo/rxfifl/ciftx/cifrx ... here */
+ /* ahub_channel2_ctrl/clr/stat/txfifo/rxfifl/ciftx/cifrx ... here */
+ /* ahub_channel3_ctrl/clr/stat/txfifo/rxfifl/ciftx/cifrx ... here */
+ u32 reserved123[3 * 8];
+ u32 config_link_ctrl; /* APBIF_CONFIG_LINK_CTRL_0, off 0x80 */
+ u32 misc_ctrl; /* APBIF_MISC_CTRL_0, offset 0x84 */
+ u32 apbdma_live_stat; /* APBIF_APBDMA_LIVE_STATUS_0 */
+ u32 i2s_live_stat; /* APBIF_I2S_LIVE_STATUS_0 */
+ u32 dam0_live_stat; /* APBIF_DAM0_LIVE_STATUS_0 */
+ u32 dam1_live_stat; /* APBIF_DAM0_LIVE_STATUS_0 */
+ u32 dam2_live_stat; /* APBIF_DAM0_LIVE_STATUS_0 */
+ u32 spdif_live_stat; /* APBIF_SPDIF_LIVE_STATUS_0 */
+ u32 i2s_int_mask; /* APBIF_I2S_INT_MASK_0, offset B0 */
+ u32 dam_int_mask; /* APBIF_DAM_INT_MASK_0 */
+ u32 reserved_int_mask; /* RESERVED, offset 0xB8 */
+ u32 spdif_int_mask; /* APBIF_SPDIF_INT_MASK_0 */
+ u32 apbif_int_mask; /* APBIF_APBIF_INT_MASK_0, off C0 */
+ u32 reserved2_int_mask; /* RESERVED, offset 0xC4 */
+ u32 i2s_int_stat; /* APBIF_I2S_INT_STATUS_0, offset C8 */
+ u32 dam_int_stat; /* APBIF_DAM_INT_STATUS_0 */
+ u32 reserved_int_stat; /* RESERVED, offset 0xD0 */
+ u32 spdif_int_stat; /* APBIF_SPDIF_INT_STATUS_0 */
+ u32 apbif_int_stat; /* APBIF_APBIF_INT_STATUS_0 */
+ u32 reserved2_int_stat; /* RESERVED, offset 0xDC */
+ u32 i2s_int_src; /* APBIF_I2S_INT_SOURCE_0, offset E0 */
+ u32 dam_int_src; /* APBIF_DAM_INT_SOURCE_0 */
+ u32 reserved_int_src; /* RESERVED, offset 0xE8 */
+ u32 spdif_int_src; /* APBIF_SPDIF_INT_SOURCE_0 */
+ u32 apbif_int_src; /* APBIF_APBIF_INT_SOURCE_0, off F0 */
+ u32 reserved2_int_src; /* RESERVED, offset 0xF4 */
+ u32 i2s_int_set; /* APBIF_I2S_INT_SET_0, offset 0xF8 */
+ u32 dam_int_set; /* APBIF_DAM_INT_SET_0, offset 0xFC */
+ u32 spdif_int_set; /* APBIF_SPDIF_INT_SET_0, off 0x100 */
+ u32 apbif_int_set; /* APBIF_APBIF_INT_SET_0, off 0x104 */
+};
+
+/*
+ * Tegra AHUB Registers Definition
+ */
+enum {
+ TEGRA_AUDIOCIF_CTRL_FIFO_THRESHOLD_SHIFT = 24,
+ TEGRA_AUDIOCIF_CTRL_FIFO_THRESHOLD_MASK_US = 0x3f,
+ TEGRA_AUDIOCIF_CTRL_FIFO_THRESHOLD_MASK =
+ TEGRA_AUDIOCIF_CTRL_FIFO_THRESHOLD_MASK_US <<
+ TEGRA_AUDIOCIF_CTRL_FIFO_THRESHOLD_SHIFT,
+
+ /* Channel count minus 1 */
+ TEGRA_AUDIOCIF_CTRL_AUDIO_CHANNELS_SHIFT = 20,
+ TEGRA_AUDIOCIF_CTRL_AUDIO_CHANNELS_MASK_US = 0xf,
+ TEGRA_AUDIOCIF_CTRL_AUDIO_CHANNELS_MASK =
+ TEGRA_AUDIOCIF_CTRL_AUDIO_CHANNELS_MASK_US <<
+ TEGRA_AUDIOCIF_CTRL_AUDIO_CHANNELS_SHIFT,
+
+ /* Channel count minus 1 */
+ TEGRA_AUDIOCIF_CTRL_CLIENT_CHANNELS_SHIFT = 16,
+ TEGRA_AUDIOCIF_CTRL_CLIENT_CHANNELS_MASK_US = 0xf,
+ TEGRA_AUDIOCIF_CTRL_CLIENT_CHANNELS_MASK =
+ TEGRA_AUDIOCIF_CTRL_CLIENT_CHANNELS_MASK_US <<
+ TEGRA_AUDIOCIF_CTRL_CLIENT_CHANNELS_SHIFT,
+
+ TEGRA_AUDIOCIF_BITS_4 = 0,
+ TEGRA_AUDIOCIF_BITS_8 = 1,
+ TEGRA_AUDIOCIF_BITS_12 = 2,
+ TEGRA_AUDIOCIF_BITS_16 = 3,
+ TEGRA_AUDIOCIF_BITS_20 = 4,
+ TEGRA_AUDIOCIF_BITS_24 = 5,
+ TEGRA_AUDIOCIF_BITS_28 = 6,
+ TEGRA_AUDIOCIF_BITS_32 = 7,
+
+ TEGRA_AUDIOCIF_CTRL_AUDIO_BITS_SHIFT = 12,
+ TEGRA_AUDIOCIF_CTRL_AUDIO_BITS_MASK =
+ 7 << TEGRA_AUDIOCIF_CTRL_AUDIO_BITS_SHIFT,
+ TEGRA_AUDIOCIF_CTRL_AUDIO_BITS_4 =
+ TEGRA_AUDIOCIF_BITS_4 << TEGRA_AUDIOCIF_CTRL_AUDIO_BITS_SHIFT,
+ TEGRA_AUDIOCIF_CTRL_AUDIO_BITS_8 =
+ TEGRA_AUDIOCIF_BITS_8 << TEGRA_AUDIOCIF_CTRL_AUDIO_BITS_SHIFT,
+ TEGRA_AUDIOCIF_CTRL_AUDIO_BITS_12 =
+ TEGRA_AUDIOCIF_BITS_12 << TEGRA_AUDIOCIF_CTRL_AUDIO_BITS_SHIFT,
+ TEGRA_AUDIOCIF_CTRL_AUDIO_BITS_16 =
+ TEGRA_AUDIOCIF_BITS_16 << TEGRA_AUDIOCIF_CTRL_AUDIO_BITS_SHIFT,
+ TEGRA_AUDIOCIF_CTRL_AUDIO_BITS_20 =
+ TEGRA_AUDIOCIF_BITS_20 << TEGRA_AUDIOCIF_CTRL_AUDIO_BITS_SHIFT,
+ TEGRA_AUDIOCIF_CTRL_AUDIO_BITS_24 =
+ TEGRA_AUDIOCIF_BITS_24 << TEGRA_AUDIOCIF_CTRL_AUDIO_BITS_SHIFT,
+ TEGRA_AUDIOCIF_CTRL_AUDIO_BITS_28 =
+ TEGRA_AUDIOCIF_BITS_28 << TEGRA_AUDIOCIF_CTRL_AUDIO_BITS_SHIFT,
+ TEGRA_AUDIOCIF_CTRL_AUDIO_BITS_32 =
+ TEGRA_AUDIOCIF_BITS_32 << TEGRA_AUDIOCIF_CTRL_AUDIO_BITS_SHIFT,
+
+ TEGRA_AUDIOCIF_CTRL_CLIENT_BITS_SHIFT = 8,
+ TEGRA_AUDIOCIF_CTRL_CLIENT_BITS_MASK =
+ 7 << TEGRA_AUDIOCIF_CTRL_CLIENT_BITS_SHIFT,
+ TEGRA_AUDIOCIF_CTRL_CLIENT_BITS_4 =
+ TEGRA_AUDIOCIF_BITS_4 << TEGRA_AUDIOCIF_CTRL_CLIENT_BITS_SHIFT,
+ TEGRA_AUDIOCIF_CTRL_CLIENT_BITS_8 =
+ TEGRA_AUDIOCIF_BITS_8 << TEGRA_AUDIOCIF_CTRL_CLIENT_BITS_SHIFT,
+ TEGRA_AUDIOCIF_CTRL_CLIENT_BITS_12 =
+ TEGRA_AUDIOCIF_BITS_12 << TEGRA_AUDIOCIF_CTRL_CLIENT_BITS_SHIFT,
+ TEGRA_AUDIOCIF_CTRL_CLIENT_BITS_16 =
+ TEGRA_AUDIOCIF_BITS_16 << TEGRA_AUDIOCIF_CTRL_CLIENT_BITS_SHIFT,
+ TEGRA_AUDIOCIF_CTRL_CLIENT_BITS_20 =
+ TEGRA_AUDIOCIF_BITS_20 << TEGRA_AUDIOCIF_CTRL_CLIENT_BITS_SHIFT,
+ TEGRA_AUDIOCIF_CTRL_CLIENT_BITS_24 =
+ TEGRA_AUDIOCIF_BITS_24 << TEGRA_AUDIOCIF_CTRL_CLIENT_BITS_SHIFT,
+ TEGRA_AUDIOCIF_CTRL_CLIENT_BITS_28 =
+ TEGRA_AUDIOCIF_BITS_28 << TEGRA_AUDIOCIF_CTRL_CLIENT_BITS_SHIFT,
+ TEGRA_AUDIOCIF_CTRL_CLIENT_BITS_32 =
+ TEGRA_AUDIOCIF_BITS_32 << TEGRA_AUDIOCIF_CTRL_CLIENT_BITS_SHIFT,
+
+ TEGRA_AUDIOCIF_EXPAND_ZERO = 0,
+ TEGRA_AUDIOCIF_EXPAND_ONE = 1,
+ TEGRA_AUDIOCIF_EXPAND_LFSR = 2,
+
+ TEGRA_AUDIOCIF_CTRL_EXPAND_SHIFT = 6,
+ TEGRA_AUDIOCIF_CTRL_EXPAND_MASK = 3 << TEGRA_AUDIOCIF_CTRL_EXPAND_SHIFT,
+ TEGRA_AUDIOCIF_CTRL_EXPAND_ZERO =
+ TEGRA_AUDIOCIF_EXPAND_ZERO << TEGRA_AUDIOCIF_CTRL_EXPAND_SHIFT,
+ TEGRA_AUDIOCIF_CTRL_EXPAND_ONE =
+ TEGRA_AUDIOCIF_EXPAND_ONE << TEGRA_AUDIOCIF_CTRL_EXPAND_SHIFT,
+ TEGRA_AUDIOCIF_CTRL_EXPAND_LFSR =
+ TEGRA_AUDIOCIF_EXPAND_LFSR << TEGRA_AUDIOCIF_CTRL_EXPAND_SHIFT,
+
+ TEGRA_AUDIOCIF_STEREO_CONV_CH0 = 0,
+ TEGRA_AUDIOCIF_STEREO_CONV_CH1 = 1,
+ TEGRA_AUDIOCIF_STEREO_CONV_AVG = 2,
+
+ TEGRA_AUDIOCIF_CTRL_STEREO_CONV_SHIFT = 4,
+ TEGRA_AUDIOCIF_CTRL_STEREO_CONV_MASK =
+ 3 << TEGRA_AUDIOCIF_CTRL_STEREO_CONV_SHIFT,
+ TEGRA_AUDIOCIF_CTRL_STEREO_CONV_CH0 =
+ TEGRA_AUDIOCIF_STEREO_CONV_CH0 <<
+ TEGRA_AUDIOCIF_CTRL_STEREO_CONV_SHIFT,
+ TEGRA_AUDIOCIF_CTRL_STEREO_CONV_CH1 =
+ TEGRA_AUDIOCIF_STEREO_CONV_CH1 <<
+ TEGRA_AUDIOCIF_CTRL_STEREO_CONV_SHIFT,
+ TEGRA_AUDIOCIF_CTRL_STEREO_CONV_AVG =
+ TEGRA_AUDIOCIF_STEREO_CONV_AVG <<
+ TEGRA_AUDIOCIF_CTRL_STEREO_CONV_SHIFT,
+
+ TEGRA_AUDIOCIF_CTRL_REPLICATE = 3,
+
+ TEGRA_AUDIOCIF_DIRECTION_TX = 0,
+ TEGRA_AUDIOCIF_DIRECTION_RX = 1,
+
+ TEGRA_AUDIOCIF_CTRL_DIRECTION_SHIFT = 2,
+ TEGRA_AUDIOCIF_CTRL_DIRECTION_MASK =
+ 1 << TEGRA_AUDIOCIF_CTRL_DIRECTION_SHIFT,
+ TEGRA_AUDIOCIF_CTRL_DIRECTION_TX =
+ TEGRA_AUDIOCIF_DIRECTION_TX <<
+ TEGRA_AUDIOCIF_CTRL_DIRECTION_SHIFT,
+ TEGRA_AUDIOCIF_CTRL_DIRECTION_RX =
+ TEGRA_AUDIOCIF_DIRECTION_RX <<
+ TEGRA_AUDIOCIF_CTRL_DIRECTION_SHIFT,
+
+ TEGRA_AUDIOCIF_TRUNCATE_ROUND = 0,
+ TEGRA_AUDIOCIF_TRUNCATE_CHOP = 1,
+
+ TEGRA_AUDIOCIF_CTRL_TRUNCATE_SHIFT = 1,
+ TEGRA_AUDIOCIF_CTRL_TRUNCATE_MASK =
+ 1 << TEGRA_AUDIOCIF_CTRL_TRUNCATE_SHIFT,
+ TEGRA_AUDIOCIF_CTRL_TRUNCATE_ROUND =
+ TEGRA_AUDIOCIF_TRUNCATE_ROUND <<
+ TEGRA_AUDIOCIF_CTRL_TRUNCATE_SHIFT,
+ TEGRA_AUDIOCIF_CTRL_TRUNCATE_CHOP =
+ TEGRA_AUDIOCIF_TRUNCATE_CHOP <<
+ TEGRA_AUDIOCIF_CTRL_TRUNCATE_SHIFT,
+
+ TEGRA_AUDIOCIF_MONO_CONV_ZERO = 0,
+ TEGRA_AUDIOCIF_MONO_CONV_COPY = 1,
+
+ TEGRA_AUDIOCIF_CTRL_MONO_CONV_SHIFT = 0,
+ TEGRA_AUDIOCIF_CTRL_MONO_CONV_MASK =
+ 1 << TEGRA_AUDIOCIF_CTRL_MONO_CONV_SHIFT,
+ TEGRA_AUDIOCIF_CTRL_MONO_CONV_ZERO =
+ TEGRA_AUDIOCIF_MONO_CONV_ZERO <<
+ TEGRA_AUDIOCIF_CTRL_MONO_CONV_SHIFT,
+ TEGRA_AUDIOCIF_CTRL_MONO_CONV_COPY =
+ TEGRA_AUDIOCIF_MONO_CONV_COPY <<
+ TEGRA_AUDIOCIF_CTRL_MONO_CONV_SHIFT,
+
+ /* Registers within TEGRA_AUDIO_CLUSTER_BASE */
+
+ TEGRA_AHUB_CHANNEL_CTRL = 0x0,
+ TEGRA_AHUB_CHANNEL_CTRL_STRIDE = 0x20,
+ TEGRA_AHUB_CHANNEL_CTRL_COUNT = 4,
+ TEGRA_AHUB_CHANNEL_CTRL_TX_EN = 1 << 31,
+ TEGRA_AHUB_CHANNEL_CTRL_RX_EN = 1 << 30,
+ TEGRA_AHUB_CHANNEL_CTRL_LOOPBACK = 1 << 29,
+
+ TEGRA_AHUB_CHANNEL_CTRL_TX_THRESHOLD_SHIFT = 16,
+ TEGRA_AHUB_CHANNEL_CTRL_TX_THRESHOLD_MASK_US = 0xff,
+ TEGRA_AHUB_CHANNEL_CTRL_TX_THRESHOLD_MASK =
+ TEGRA_AHUB_CHANNEL_CTRL_TX_THRESHOLD_MASK_US <<
+ TEGRA_AHUB_CHANNEL_CTRL_TX_THRESHOLD_SHIFT,
+
+ TEGRA_AHUB_CHANNEL_CTRL_RX_THRESHOLD_SHIFT = 8,
+ TEGRA_AHUB_CHANNEL_CTRL_RX_THRESHOLD_MASK_US = 0xff,
+ TEGRA_AHUB_CHANNEL_CTRL_RX_THRESHOLD_MASK =
+ TEGRA_AHUB_CHANNEL_CTRL_RX_THRESHOLD_MASK_US <<
+ TEGRA_AHUB_CHANNEL_CTRL_RX_THRESHOLD_SHIFT,
+
+ TEGRA_AHUB_CHANNEL_CTRL_TX_PACK_EN = 1 << 6,
+
+ TEGRA_PACK_8_4 = 2,
+ TEGRA_PACK_16 = 3,
+
+ TEGRA_AHUB_CHANNEL_CTRL_TX_PACK_SHIFT = 4,
+ TEGRA_AHUB_CHANNEL_CTRL_TX_PACK_MASK_US = 3,
+ TEGRA_AHUB_CHANNEL_CTRL_TX_PACK_MASK =
+ TEGRA_AHUB_CHANNEL_CTRL_TX_PACK_MASK_US <<
+ TEGRA_AHUB_CHANNEL_CTRL_TX_PACK_SHIFT,
+ TEGRA_AHUB_CHANNEL_CTRL_TX_PACK_8_4 =
+ TEGRA_PACK_8_4 << TEGRA_AHUB_CHANNEL_CTRL_TX_PACK_SHIFT,
+ TEGRA_AHUB_CHANNEL_CTRL_TX_PACK_16 =
+ TEGRA_PACK_16 << TEGRA_AHUB_CHANNEL_CTRL_TX_PACK_SHIFT,
+
+ TEGRA_AHUB_CHANNEL_CTRL_RX_PACK_EN = 1 << 2,
+
+ TEGRA_AHUB_CHANNEL_CTRL_RX_PACK_SHIFT = 0,
+ TEGRA_AHUB_CHANNEL_CTRL_RX_PACK_MASK_US = 3,
+ TEGRA_AHUB_CHANNEL_CTRL_RX_PACK_MASK =
+ TEGRA_AHUB_CHANNEL_CTRL_RX_PACK_MASK_US <<
+ TEGRA_AHUB_CHANNEL_CTRL_RX_PACK_SHIFT,
+ TEGRA_AHUB_CHANNEL_CTRL_RX_PACK_8_4 =
+ TEGRA_PACK_8_4 << TEGRA_AHUB_CHANNEL_CTRL_RX_PACK_SHIFT,
+ TEGRA_AHUB_CHANNEL_CTRL_RX_PACK_16 =
+ TEGRA_PACK_16 << TEGRA_AHUB_CHANNEL_CTRL_RX_PACK_SHIFT,
+
+ /* TEGRA_AHUB_CHANNEL_CLEAR */
+
+ TEGRA_AHUB_CHANNEL_CLEAR = 0x4,
+ TEGRA_AHUB_CHANNEL_CLEAR_STRIDE = 0x20,
+ TEGRA_AHUB_CHANNEL_CLEAR_COUNT = 4,
+ TEGRA_AHUB_CHANNEL_CLEAR_TX_SOFT_RESET = 1 << 31,
+ TEGRA_AHUB_CHANNEL_CLEAR_RX_SOFT_RESET = 1 << 30,
+
+ TEGRA_AHUB_CHANNEL_STATUS = 0x8,
+ TEGRA_AHUB_CHANNEL_STATUS_STRIDE = 0x20,
+ TEGRA_AHUB_CHANNEL_STATUS_COUNT = 4,
+ TEGRA_AHUB_CHANNEL_STATUS_TX_FREE_SHIFT = 24,
+ TEGRA_AHUB_CHANNEL_STATUS_TX_FREE_MASK_US = 0xff,
+ TEGRA_AHUB_CHANNEL_STATUS_TX_FREE_MASK =
+ TEGRA_AHUB_CHANNEL_STATUS_TX_FREE_MASK_US <<
+ TEGRA_AHUB_CHANNEL_STATUS_TX_FREE_SHIFT,
+ TEGRA_AHUB_CHANNEL_STATUS_RX_FREE_SHIFT = 16,
+ TEGRA_AHUB_CHANNEL_STATUS_RX_FREE_MASK_US = 0xff,
+ TEGRA_AHUB_CHANNEL_STATUS_RX_FREE_MASK =
+ TEGRA_AHUB_CHANNEL_STATUS_RX_FREE_MASK_US <<
+ TEGRA_AHUB_CHANNEL_STATUS_RX_FREE_SHIFT,
+ TEGRA_AHUB_CHANNEL_STATUS_TX_TRIG = 1 << 1,
+ TEGRA_AHUB_CHANNEL_STATUS_RX_TRIG = 1 << 0,
+
+ TEGRA_AHUB_CHANNEL_TXFIFO = 0xc,
+ TEGRA_AHUB_CHANNEL_TXFIFO_STRIDE = 0x20,
+ TEGRA_AHUB_CHANNEL_TXFIFO_COUNT = 4,
+
+ TEGRA_AHUB_CHANNEL_RXFIFO = 0x10,
+ TEGRA_AHUB_CHANNEL_RXFIFO_STRIDE = 0x20,
+ TEGRA_AHUB_CHANNEL_RXFIFO_COUNT = 4,
+
+ TEGRA_AHUB_CIF_TX_CTRL = 0x14,
+ TEGRA_AHUB_CIF_TX_CTRL_STRIDE = 0x20,
+ TEGRA_AHUB_CIF_TX_CTRL_COUNT = 4,
+ /* Uses field from TEGRA_AUDIOCIF_CTRL_* */
+
+ TEGRA_AHUB_CIF_RX_CTRL = 0x18,
+ TEGRA_AHUB_CIF_RX_CTRL_STRIDE = 0x20,
+ TEGRA_AHUB_CIF_RX_CTRL_COUNT = 4,
+ /* Uses field from TEGRA_AUDIOCIF_CTRL_* */
+
+ TEGRA_AHUB_CONFIG_LINK_CTRL = 0x80,
+ TEGRA_AHUB_CONFIG_LINK_CTRL_MASTER_FIFO_FULL_CNT_SHIFT = 28,
+ TEGRA_AHUB_CONFIG_LINK_CTRL_MASTER_FIFO_FULL_CNT_MASK_US = 0xf,
+ TEGRA_AHUB_CONFIG_LINK_CTRL_MASTER_FIFO_FULL_CNT_MASK =
+ TEGRA_AHUB_CONFIG_LINK_CTRL_MASTER_FIFO_FULL_CNT_MASK_US <<
+ TEGRA_AHUB_CONFIG_LINK_CTRL_MASTER_FIFO_FULL_CNT_SHIFT,
+ TEGRA_AHUB_CONFIG_LINK_CTRL_TIMEOUT_CNT_SHIFT = 16,
+ TEGRA_AHUB_CONFIG_LINK_CTRL_TIMEOUT_CNT_MASK_US = 0xfff,
+ TEGRA_AHUB_CONFIG_LINK_CTRL_TIMEOUT_CNT_MASK =
+ TEGRA_AHUB_CONFIG_LINK_CTRL_TIMEOUT_CNT_MASK_US <<
+ TEGRA_AHUB_CONFIG_LINK_CTRL_TIMEOUT_CNT_SHIFT,
+ TEGRA_AHUB_CONFIG_LINK_CTRL_IDLE_CNT_SHIFT = 4,
+ TEGRA_AHUB_CONFIG_LINK_CTRL_IDLE_CNT_MASK_US = 0xfff,
+ TEGRA_AHUB_CONFIG_LINK_CTRL_IDLE_CNT_MASK =
+ TEGRA_AHUB_CONFIG_LINK_CTRL_IDLE_CNT_MASK_US <<
+ TEGRA_AHUB_CONFIG_LINK_CTRL_IDLE_CNT_SHIFT,
+ TEGRA_AHUB_CONFIG_LINK_CTRL_CG_EN = 1 << 2,
+ TEGRA_AHUB_CONFIG_LINK_CTRL_CLEAR_TIMEOUT_CNTR = 1 << 1,
+ TEGRA_AHUB_CONFIG_LINK_CTRL_SOFT_RESET = 1 << 0,
+
+ TEGRA_AHUB_MISC_CTRL = 0x84,
+ TEGRA_AHUB_MISC_CTRL_AUDIO_ACTIVE = 1 << 31,
+ TEGRA_AHUB_MISC_CTRL_AUDIO_CG_EN = 1 << 8,
+ TEGRA_AHUB_MISC_CTRL_AUDIO_OBS_SEL_SHIFT = 0,
+ TEGRA_AHUB_MISC_CTRL_AUDIO_OBS_SEL_MASK =
+ 0x1f << TEGRA_AHUB_MISC_CTRL_AUDIO_OBS_SEL_SHIFT,
+
+ TEGRA_AHUB_APBDMA_LIVE_STATUS = 0x88,
+ TEGRA_AHUB_APBDMA_LIVE_STATUS_CH3_RX_CIF_FIFO_FULL = 1 << 31,
+ TEGRA_AHUB_APBDMA_LIVE_STATUS_CH3_TX_CIF_FIFO_FULL = 1 << 30,
+ TEGRA_AHUB_APBDMA_LIVE_STATUS_CH2_RX_CIF_FIFO_FULL = 1 << 29,
+ TEGRA_AHUB_APBDMA_LIVE_STATUS_CH2_TX_CIF_FIFO_FULL = 1 << 28,
+ TEGRA_AHUB_APBDMA_LIVE_STATUS_CH1_RX_CIF_FIFO_FULL = 1 << 27,
+ TEGRA_AHUB_APBDMA_LIVE_STATUS_CH1_TX_CIF_FIFO_FULL = 1 << 26,
+ TEGRA_AHUB_APBDMA_LIVE_STATUS_CH0_RX_CIF_FIFO_FULL = 1 << 25,
+ TEGRA_AHUB_APBDMA_LIVE_STATUS_CH0_TX_CIF_FIFO_FULL = 1 << 24,
+ TEGRA_AHUB_APBDMA_LIVE_STATUS_CH3_RX_CIF_FIFO_EMPTY = 1 << 23,
+ TEGRA_AHUB_APBDMA_LIVE_STATUS_CH3_TX_CIF_FIFO_EMPTY = 1 << 22,
+ TEGRA_AHUB_APBDMA_LIVE_STATUS_CH2_RX_CIF_FIFO_EMPTY = 1 << 21,
+ TEGRA_AHUB_APBDMA_LIVE_STATUS_CH2_TX_CIF_FIFO_EMPTY = 1 << 20,
+ TEGRA_AHUB_APBDMA_LIVE_STATUS_CH1_RX_CIF_FIFO_EMPTY = 1 << 19,
+ TEGRA_AHUB_APBDMA_LIVE_STATUS_CH1_TX_CIF_FIFO_EMPTY = 1 << 18,
+ TEGRA_AHUB_APBDMA_LIVE_STATUS_CH0_RX_CIF_FIFO_EMPTY = 1 << 17,
+ TEGRA_AHUB_APBDMA_LIVE_STATUS_CH0_TX_CIF_FIFO_EMPTY = 1 << 16,
+ TEGRA_AHUB_APBDMA_LIVE_STATUS_CH3_RX_DMA_FIFO_FULL = 1 << 15,
+ TEGRA_AHUB_APBDMA_LIVE_STATUS_CH3_TX_DMA_FIFO_FULL = 1 << 14,
+ TEGRA_AHUB_APBDMA_LIVE_STATUS_CH2_RX_DMA_FIFO_FULL = 1 << 13,
+ TEGRA_AHUB_APBDMA_LIVE_STATUS_CH2_TX_DMA_FIFO_FULL = 1 << 12,
+ TEGRA_AHUB_APBDMA_LIVE_STATUS_CH1_RX_DMA_FIFO_FULL = 1 << 11,
+ TEGRA_AHUB_APBDMA_LIVE_STATUS_CH1_TX_DMA_FIFO_FULL = 1 << 10,
+ TEGRA_AHUB_APBDMA_LIVE_STATUS_CH0_RX_DMA_FIFO_FULL = 1 << 9,
+ TEGRA_AHUB_APBDMA_LIVE_STATUS_CH0_TX_DMA_FIFO_FULL = 1 << 8,
+ TEGRA_AHUB_APBDMA_LIVE_STATUS_CH3_RX_DMA_FIFO_EMPTY = 1 << 7,
+ TEGRA_AHUB_APBDMA_LIVE_STATUS_CH3_TX_DMA_FIFO_EMPTY = 1 << 6,
+ TEGRA_AHUB_APBDMA_LIVE_STATUS_CH2_RX_DMA_FIFO_EMPTY = 1 << 5,
+ TEGRA_AHUB_APBDMA_LIVE_STATUS_CH2_TX_DMA_FIFO_EMPTY = 1 << 4,
+ TEGRA_AHUB_APBDMA_LIVE_STATUS_CH1_RX_DMA_FIFO_EMPTY = 1 << 3,
+ TEGRA_AHUB_APBDMA_LIVE_STATUS_CH1_TX_DMA_FIFO_EMPTY = 1 << 2,
+ TEGRA_AHUB_APBDMA_LIVE_STATUS_CH0_RX_DMA_FIFO_EMPTY = 1 << 1,
+ TEGRA_AHUB_APBDMA_LIVE_STATUS_CH0_TX_DMA_FIFO_EMPTY = 1 << 0,
+
+ TEGRA_AHUB_I2S_LIVE_STATUS = 0x8c,
+ TEGRA_AHUB_I2S_LIVE_STATUS_I2S4_RX_FIFO_FULL = 1 << 29,
+ TEGRA_AHUB_I2S_LIVE_STATUS_I2S4_TX_FIFO_FULL = 1 << 28,
+ TEGRA_AHUB_I2S_LIVE_STATUS_I2S3_RX_FIFO_FULL = 1 << 27,
+ TEGRA_AHUB_I2S_LIVE_STATUS_I2S3_TX_FIFO_FULL = 1 << 26,
+ TEGRA_AHUB_I2S_LIVE_STATUS_I2S2_RX_FIFO_FULL = 1 << 25,
+ TEGRA_AHUB_I2S_LIVE_STATUS_I2S2_TX_FIFO_FULL = 1 << 24,
+ TEGRA_AHUB_I2S_LIVE_STATUS_I2S1_RX_FIFO_FULL = 1 << 23,
+ TEGRA_AHUB_I2S_LIVE_STATUS_I2S1_TX_FIFO_FULL = 1 << 22,
+ TEGRA_AHUB_I2S_LIVE_STATUS_I2S0_RX_FIFO_FULL = 1 << 21,
+ TEGRA_AHUB_I2S_LIVE_STATUS_I2S0_TX_FIFO_FULL = 1 << 20,
+ TEGRA_AHUB_I2S_LIVE_STATUS_I2S4_RX_FIFO_ENABLED = 1 << 19,
+ TEGRA_AHUB_I2S_LIVE_STATUS_I2S4_TX_FIFO_ENABLED = 1 << 18,
+ TEGRA_AHUB_I2S_LIVE_STATUS_I2S3_RX_FIFO_ENABLED = 1 << 17,
+ TEGRA_AHUB_I2S_LIVE_STATUS_I2S3_TX_FIFO_ENABLED = 1 << 16,
+ TEGRA_AHUB_I2S_LIVE_STATUS_I2S2_RX_FIFO_ENABLED = 1 << 15,
+ TEGRA_AHUB_I2S_LIVE_STATUS_I2S2_TX_FIFO_ENABLED = 1 << 14,
+ TEGRA_AHUB_I2S_LIVE_STATUS_I2S1_RX_FIFO_ENABLED = 1 << 13,
+ TEGRA_AHUB_I2S_LIVE_STATUS_I2S1_TX_FIFO_ENABLED = 1 << 12,
+ TEGRA_AHUB_I2S_LIVE_STATUS_I2S0_RX_FIFO_ENABLED = 1 << 11,
+ TEGRA_AHUB_I2S_LIVE_STATUS_I2S0_TX_FIFO_ENABLED = 1 << 10,
+ TEGRA_AHUB_I2S_LIVE_STATUS_I2S4_RX_FIFO_EMPTY = 1 << 9,
+ TEGRA_AHUB_I2S_LIVE_STATUS_I2S4_TX_FIFO_EMPTY = 1 << 8,
+ TEGRA_AHUB_I2S_LIVE_STATUS_I2S3_RX_FIFO_EMPTY = 1 << 7,
+ TEGRA_AHUB_I2S_LIVE_STATUS_I2S3_TX_FIFO_EMPTY = 1 << 6,
+ TEGRA_AHUB_I2S_LIVE_STATUS_I2S2_RX_FIFO_EMPTY = 1 << 5,
+ TEGRA_AHUB_I2S_LIVE_STATUS_I2S2_TX_FIFO_EMPTY = 1 << 4,
+ TEGRA_AHUB_I2S_LIVE_STATUS_I2S1_RX_FIFO_EMPTY = 1 << 3,
+ TEGRA_AHUB_I2S_LIVE_STATUS_I2S1_TX_FIFO_EMPTY = 1 << 2,
+ TEGRA_AHUB_I2S_LIVE_STATUS_I2S0_RX_FIFO_EMPTY = 1 << 1,
+ TEGRA_AHUB_I2S_LIVE_STATUS_I2S0_TX_FIFO_EMPTY = 1 << 0,
+
+ TEGRA_AHUB_DAM_LIVE_STATUS = 0x90,
+ TEGRA_AHUB_DAM_LIVE_STATUS_STRIDE = 0x8,
+ TEGRA_AHUB_DAM_LIVE_STATUS_COUNT = 3,
+ TEGRA_AHUB_DAM_LIVE_STATUS_TX_ENABLED = 1 << 26,
+ TEGRA_AHUB_DAM_LIVE_STATUS_RX1_ENABLED = 1 << 25,
+ TEGRA_AHUB_DAM_LIVE_STATUS_RX0_ENABLED = 1 << 24,
+ TEGRA_AHUB_DAM_LIVE_STATUS_TXFIFO_FULL = 1 << 15,
+ TEGRA_AHUB_DAM_LIVE_STATUS_RX1FIFO_FULL = 1 << 9,
+ TEGRA_AHUB_DAM_LIVE_STATUS_RX0FIFO_FULL = 1 << 8,
+ TEGRA_AHUB_DAM_LIVE_STATUS_TXFIFO_EMPTY = 1 << 7,
+ TEGRA_AHUB_DAM_LIVE_STATUS_RX1FIFO_EMPTY = 1 << 1,
+ TEGRA_AHUB_DAM_LIVE_STATUS_RX0FIFO_EMPTY = 1 << 0,
+
+ TEGRA_AHUB_SPDIF_LIVE_STATUS = 0xa8,
+ TEGRA_AHUB_SPDIF_LIVE_STATUS_USER_TX_ENABLED = 1 << 11,
+ TEGRA_AHUB_SPDIF_LIVE_STATUS_USER_RX_ENABLED = 1 << 10,
+ TEGRA_AHUB_SPDIF_LIVE_STATUS_DATA_TX_ENABLED = 1 << 9,
+ TEGRA_AHUB_SPDIF_LIVE_STATUS_DATA_RX_ENABLED = 1 << 8,
+ TEGRA_AHUB_SPDIF_LIVE_STATUS_USER_TXFIFO_FULL = 1 << 7,
+ TEGRA_AHUB_SPDIF_LIVE_STATUS_USER_RXFIFO_FULL = 1 << 6,
+ TEGRA_AHUB_SPDIF_LIVE_STATUS_DATA_TXFIFO_FULL = 1 << 5,
+ TEGRA_AHUB_SPDIF_LIVE_STATUS_DATA_RXFIFO_FULL = 1 << 4,
+ TEGRA_AHUB_SPDIF_LIVE_STATUS_USER_TXFIFO_EMPTY = 1 << 3,
+ TEGRA_AHUB_SPDIF_LIVE_STATUS_USER_RXFIFO_EMPTY = 1 << 2,
+ TEGRA_AHUB_SPDIF_LIVE_STATUS_DATA_TXFIFO_EMPTY = 1 << 1,
+ TEGRA_AHUB_SPDIF_LIVE_STATUS_DATA_RXFIFO_EMPTY = 1 << 0,
+
+ TEGRA_AHUB_I2S_INT_MASK = 0xb0,
+ TEGRA_AHUB_DAM_INT_MASK = 0xb4,
+ TEGRA_AHUB_SPDIF_INT_MASK = 0xbc,
+ TEGRA_AHUB_APBIF_INT_MASK = 0xc0,
+ TEGRA_AHUB_I2S_INT_STATUS = 0xc8,
+ TEGRA_AHUB_DAM_INT_STATUS = 0xcc,
+ TEGRA_AHUB_SPDIF_INT_STATUS = 0xd4,
+ TEGRA_AHUB_APBIF_INT_STATUS = 0xd8,
+ TEGRA_AHUB_I2S_INT_SOURCE = 0xe0,
+ TEGRA_AHUB_DAM_INT_SOURCE = 0xe4,
+ TEGRA_AHUB_SPDIF_INT_SOURCE = 0xec,
+ TEGRA_AHUB_APBIF_INT_SOURCE = 0xf0,
+ TEGRA_AHUB_I2S_INT_SET = 0xf8,
+ TEGRA_AHUB_DAM_INT_SET = 0xfc,
+ TEGRA_AHUB_SPDIF_INT_SET = 0x100,
+ TEGRA_AHUB_APBIF_INT_SET = 0x104,
+
+ TEGRA_AHUB_AUDIO_RX = 0x0,
+ TEGRA_AHUB_AUDIO_RX_STRIDE = 0x4,
+ TEGRA_AHUB_AUDIO_RX_COUNT = 17,
+};
+
+#endif /* _TEGRA_I2C_H_ */
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+159
+/*
+ * Take from dc tegra_ahub.c
+ *
+ * Copyright 2018 Google LLC
+ */
+
+#define LOG_CATEGORY UCLASS_MISC
+
+#include <common.h>
+#include <dm.h>
+#include <i2s.h>
+#include <misc.h>
+#include <asm/io.h>
+#include <asm/arch-tegra/tegra_ahub.h>
+#include <asm/arch-tegra/tegra_i2s.h>
+#include "tegra_i2s_priv.h"
+
+struct tegra_ahub_priv {
+ struct apbif_regs *apbif_regs;
+ struct xbar_regs *xbar_regs;
+ u32 full_mask;
+ int capacity_words; /* FIFO capacity in words */
+
+ /*
+ * This is unset intially, but is set by tegra_ahub_ioctl() called
+ * from the misc_ioctl() in tegra_sound_probe()
+ */
+ struct udevice *i2s;
+ struct udevice *dma;
+};
+
+static int tegra_ahub_xbar_enable_i2s(struct xbar_regs *regs, int i2s_id)
+{
+ /*
+ * Enables I2S as the receiver of APBIF by writing APBIF_TX0 (0x01) to
+ * the rx0 register
+ */
+ switch (i2s_id) {
+ case 0:
+ writel(1, ®s->i2s0_rx0);
+ break;
+ case 1:
+ writel(1, ®s->i2s1_rx0);
+ break;
+ case 2:
+ writel(1, ®s->i2s2_rx0);
+ break;
+ case 3:
+ writel(1, ®s->i2s3_rx0);
+ break;
+ case 4:
+ writel(1, ®s->i2s4_rx0);
+ break;
+ default:
+ log_err("Invalid I2S component id: %d\n", i2s_id);
+ return -EINVAL;
+ }
+ return 0;
+}
+
+static int tegra_ahub_apbif_is_full(struct udevice *dev)
+{
+ struct tegra_ahub_priv *priv = dev_get_priv(dev);
+
+ return readl(&priv->apbif_regs->apbdma_live_stat) & priv->full_mask;
+}
+
+/**
+ * tegra_ahub_wait_for_space() - Wait for space in the FIFO
+ *
+ * @return 0 if OK, -ETIMEDOUT if no space was available in time
+ */
+static int tegra_ahub_wait_for_space(struct udevice *dev)
+{
+ int i = 100000;
+ ulong start;
+
+ /* Busy-wait initially, since this should take almost no time */
+ while (i--) {
+ if (!tegra_ahub_apbif_is_full(dev))
+ return 0;
+ }
+
+ /* Failed, so do a slower loop for 100ms */
+ start = get_timer(0);
+ while (tegra_ahub_apbif_is_full(dev)) {
+ if (get_timer(start) > 100)
+ return -ETIMEDOUT;
+ }
+
+ return 0;
+}
+
+static int tegra_ahub_apbif_send(struct udevice *dev, int offset,
+ const void *buf, int len)
+{
+ struct tegra_ahub_priv *priv = dev_get_priv(dev);
+ const u32 *data = (const u32 *)buf;
+ ssize_t written = 0;
+
+ if (len % sizeof(*data)) {
+ log_err("Data size (%zd) must be aligned to %zd.\n", len,
+ sizeof(*data));
+ return -EFAULT;
+ }
+ while (written < len) {
+ int ret = tegra_ahub_wait_for_space(dev);
+
+ if (ret)
+ return ret;
+
+ writel(*data++, &priv->apbif_regs->channel0_txfifo);
+ written += sizeof(*data);
+ }
+
+ return written;
+}
+
+static void tegra_ahub_apbif_set_cif(struct udevice *dev, u32 value)
+{
+ struct tegra_ahub_priv *priv = dev_get_priv(dev);
+
+ writel(value, &priv->apbif_regs->channel0_cif_tx0_ctrl);
+}
+
+static void tegra_ahub_apbif_enable_channel0(struct udevice *dev,
+ int fifo_threshold)
+{
+ struct tegra_ahub_priv *priv = dev_get_priv(dev);
+
+ u32 ctrl = TEGRA_AHUB_CHANNEL_CTRL_TX_PACK_EN |
+ TEGRA_AHUB_CHANNEL_CTRL_TX_PACK_16 |
+ TEGRA_AHUB_CHANNEL_CTRL_TX_EN;
+
+ fifo_threshold--; /* fifo_threshold starts from 1 */
+ ctrl |= (fifo_threshold << TEGRA_AHUB_CHANNEL_CTRL_TX_THRESHOLD_SHIFT);
+ writel(ctrl, &priv->apbif_regs->channel0_ctrl);
+}
+
+static u32 tegra_ahub_get_cif(bool is_receive, uint channels,
+ uint bits_per_sample, uint fifo_threshold)
+{
+ uint audio_bits = (bits_per_sample >> 2) - 1;
+ u32 val;
+
+ channels--; /* Channels in CIF starts from 1 */
+ fifo_threshold--; /* FIFO threshold starts from 1 */
+ /* Assume input and output are always using same channel / bits */
+ val = channels << TEGRA_AUDIOCIF_CTRL_AUDIO_CHANNELS_SHIFT |
+ channels << TEGRA_AUDIOCIF_CTRL_CLIENT_CHANNELS_SHIFT |
+ audio_bits << TEGRA_AUDIOCIF_CTRL_AUDIO_BITS_SHIFT |
+ audio_bits << TEGRA_AUDIOCIF_CTRL_CLIENT_BITS_SHIFT |
+ fifo_threshold << TEGRA_AUDIOCIF_CTRL_FIFO_THRESHOLD_SHIFT |
+ (is_receive ? TEGRA_AUDIOCIF_DIRECTION_RX <<
+ TEGRA_AUDIOCIF_CTRL_DIRECTION_SHIFT : 0);
+
+ return val;
+}
+
+static int tegra_ahub_enable(struct udevice *dev)
+{
+ struct tegra_ahub_priv *priv = dev_get_priv(dev);
+ struct i2s_uc_priv *uc_priv = dev_get_uclass_priv(priv->i2s);
+ u32 cif_ctrl = 0;
+ int ret;
+
+ /* We use APBIF channel0 as a sender */
+ priv->full_mask = TEGRA_AHUB_APBDMA_LIVE_STATUS_CH0_TX_CIF_FIFO_FULL;
+ priv->capacity_words = 8;
+
+ /*
+ * FIFO is inactive until (fifo_threshold) of words are sent. For
+ * better performance, we want to set it to half of capacity.
+ */
+ u32 fifo_threshold = priv->capacity_words / 2;
+
+ /*
+ * Setup audio client interface (ACIF): APBIF (channel0) as sender and
+ * I2S as receiver
+ */
+ cif_ctrl = tegra_ahub_get_cif(true, uc_priv->channels,
+ uc_priv->bitspersample, fifo_threshold);
+ tegra_i2s_set_cif_tx_ctrl(priv->i2s, cif_ctrl);
+
+ cif_ctrl = tegra_ahub_get_cif(false, uc_priv->channels,
+ uc_priv->bitspersample, fifo_threshold);
+ tegra_ahub_apbif_set_cif(dev, cif_ctrl);
+ tegra_ahub_apbif_enable_channel0(dev, fifo_threshold);
+
+ ret = tegra_ahub_xbar_enable_i2s(priv->xbar_regs, uc_priv->id);
+ if (ret)
+ return ret;
+ log_debug("ahub: channels=%d, bitspersample=%d, cif_ctrl=%x, fifo_threshold=%d, id=%d\n",
+ uc_priv->channels, uc_priv->bitspersample, cif_ctrl,
+ fifo_threshold, uc_priv->id);
+
+ return 0;
+}
+
+static int tegra_ahub_ioctl(struct udevice *dev, unsigned long request,
+ void *buf)
+{
+ struct tegra_ahub_priv *priv = dev_get_priv(dev);
+
+ if (request != AHUB_MISCOP_SET_I2S)
+ return -ENOSYS;
+
+ priv->i2s = *(struct udevice **)buf;
+ log_debug("i2s set to '%s'\n", priv->i2s->name);
+
+ return tegra_ahub_enable(dev);
+}
+
+static int tegra_ahub_probe(struct udevice *dev)
+{
+ struct tegra_ahub_priv *priv = dev_get_priv(dev);
+ ulong addr;
+
+ addr = dev_read_addr_index(dev, 0);
+ if (addr == FDT_ADDR_T_NONE) {
+ log_debug("Invalid apbif address\n");
+ return -EINVAL;
+ }
+ priv->apbif_regs = (struct apbif_regs *)addr;
+
+ addr = dev_read_addr_index(dev, 1);
+ if (addr == FDT_ADDR_T_NONE) {
+ log_debug("Invalid xbar address\n");
+ return -EINVAL;
+ }
+ priv->xbar_regs = (struct xbar_regs *)addr;
+ log_debug("ahub apbif_regs=%p, xbar_regs=%p\n", priv->apbif_regs,
+ priv->xbar_regs);
+
+ return 0;
+}
+
+static struct misc_ops tegra_ahub_ops = {
+ .write = tegra_ahub_apbif_send,
+ .ioctl = tegra_ahub_ioctl,
+};
+
+static const struct udevice_id tegra_ahub_ids[] = {
+ { .compatible = "nvidia,tegra124-ahub" },
+ { }
+};
+
+U_BOOT_DRIVER(tegra_ahub) = {
+ .name = "tegra_ahub",
+ .id = UCLASS_MISC,
+ .of_match = tegra_ahub_ids,
+ .ops = &tegra_ahub_ops,
+ .probe = tegra_ahub_probe,
+ .priv_auto_alloc_size = sizeof(struct tegra_ahub_priv),
+};
projects / project / bcm63xx / u-boot.git / commitdiff