rpi3: Rename RPI3_IO_BASE to RPI_IO_BASE

The location of the MMIO window is different between a Raspberry Pi 3
and 4: the former has it just below 1GB, the latter below 4GB.
The relative location of the peripherals is mostly compatible though.

To allow sharing code between the two models, let's rename the symbol
used for the MMIO base to the more generic RPI_IO_BASE name.

Change-Id: I3c2762fb30fd56cca743348e79d72ef8c60ddb03
Signed-off-by: Andre Przywara <andre.przywara@arm.com>

diff --git a/plat/rpi/rpi3/include/platform_def.h b/plat/rpi/rpi3/include/platform_def.h
index 2a12fe726b93fbdb596493c079921e0e2abc5b67..e308f70a6185c6d96163fddde8b6c5dfcee71d1b 100644 (file)
--- a/plat/rpi/rpi3/include/platform_def.h
+++ b/plat/rpi/rpi3/include/platform_def.h
@@ -110,8 +110,8 @@
 /*
  * I/O registers.
  */
-#define DEVICE0_BASE                   RPI3_IO_BASE
-#define DEVICE0_SIZE                   RPI3_IO_SIZE
+#define DEVICE0_BASE                   RPI_IO_BASE
+#define DEVICE0_SIZE                   RPI_IO_SIZE
 
 /*
  * Arm TF lives in SRAM, partition it here

diff --git a/plat/rpi/rpi3/include/rpi_hw.h b/plat/rpi/rpi3/include/rpi_hw.h
index 7a3ea57bc094491e1d1f5640697c2fefdab52041..01d5b4a0f6b48f245796da4080c458b50b440a2f 100644 (file)
--- a/plat/rpi/rpi3/include/rpi_hw.h
+++ b/plat/rpi/rpi3/include/rpi_hw.h
@@ -13,14 +13,14 @@
  * Peripherals
  */
 
-#define RPI3_IO_BASE                   ULL(0x3F000000)
-#define RPI3_IO_SIZE                   ULL(0x01000000)
+#define RPI_IO_BASE                    ULL(0x3F000000)
+#define RPI_IO_SIZE                    ULL(0x01000000)
 
 /*
  * ARM <-> VideoCore mailboxes
  */
 #define RPI3_MBOX_OFFSET               ULL(0x0000B880)
-#define RPI3_MBOX_BASE                 (RPI3_IO_BASE + RPI3_MBOX_OFFSET)
+#define RPI3_MBOX_BASE                 (RPI_IO_BASE + RPI3_MBOX_OFFSET)
 /* VideoCore -> ARM */
 #define RPI3_MBOX0_READ_OFFSET         ULL(0x00000000)
 #define RPI3_MBOX0_PEEK_OFFSET         ULL(0x00000010)
@@ -41,7 +41,7 @@
  * Power management, reset controller, watchdog.
  */
 #define RPI3_IO_PM_OFFSET              ULL(0x00100000)
-#define RPI3_PM_BASE                   (RPI3_IO_BASE + RPI3_IO_PM_OFFSET)
+#define RPI3_PM_BASE                   (RPI_IO_BASE + RPI3_IO_PM_OFFSET)
 /* Registers on top of RPI3_PM_BASE. */
 #define RPI3_PM_RSTC_OFFSET            ULL(0x0000001C)
 #define RPI3_PM_RSTS_OFFSET            ULL(0x00000020)
@@ -62,7 +62,7 @@
  * Hardware random number generator.
  */
 #define RPI3_IO_RNG_OFFSET             ULL(0x00104000)
-#define RPI3_RNG_BASE                  (RPI3_IO_BASE + RPI3_IO_RNG_OFFSET)
+#define RPI3_RNG_BASE                  (RPI_IO_BASE + RPI3_IO_RNG_OFFSET)
 #define RPI3_RNG_CTRL_OFFSET           ULL(0x00000000)
 #define RPI3_RNG_STATUS_OFFSET         ULL(0x00000004)
 #define RPI3_RNG_DATA_OFFSET           ULL(0x00000008)
@@ -80,20 +80,20 @@
  * Serial port (called 'Mini UART' in the BCM docucmentation).
  */
 #define RPI3_IO_MINI_UART_OFFSET       ULL(0x00215040)
-#define RPI3_MINI_UART_BASE            (RPI3_IO_BASE + RPI3_IO_MINI_UART_OFFSET)
+#define RPI3_MINI_UART_BASE            (RPI_IO_BASE + RPI3_IO_MINI_UART_OFFSET)
 #define RPI3_MINI_UART_CLK_IN_HZ       ULL(500000000)
 
 /*
  * GPIO controller
  */
 #define RPI3_IO_GPIO_OFFSET            ULL(0x00200000)
-#define RPI3_GPIO_BASE                 (RPI3_IO_BASE + RPI3_IO_GPIO_OFFSET)
+#define RPI3_GPIO_BASE                 (RPI_IO_BASE + RPI3_IO_GPIO_OFFSET)
 
 /*
  * SDHost controller
  */
 #define RPI3_IO_SDHOST_OFFSET           ULL(0x00202000)
-#define RPI3_SDHOST_BASE                (RPI3_IO_BASE + RPI3_IO_SDHOST_OFFSET)
+#define RPI3_SDHOST_BASE                (RPI_IO_BASE + RPI3_IO_SDHOST_OFFSET)
 
 /*
  * Local interrupt controller