memory-controller@2000 {
compatible = "fsl,8540-memory-controller";
reg = <0x2000 0x1000>;
- interrupt-parent = <&MPIC>;
+ interrupt-parent = <&mpic>;
interrupts = <0x12 0x2>;
};
reg = <0x20000 0x1000>;
cache-line-size = <0x20>; /* 32 bytes */
cache-size = <0x40000>; /* L2, 256K */
- interrupt-parent = <&MPIC>;
+ interrupt-parent = <&mpic>;
interrupts = <0x10 0x2>;
};
compatible = "fsl-i2c";
reg = <0x3000 0x100>;
interrupts = <0x2b 0x2>;
- interrupt-parent = <&MPIC>;
+ interrupt-parent = <&mpic>;
dfsrr;
};
reg = <0x24520 0x20>;
PHY1: ethernet-phy@1 {
- interrupt-parent = <&MPIC>;
+ interrupt-parent = <&mpic>;
reg = <0x1>;
device_type = "ethernet-phy";
};
PHY2: ethernet-phy@2 {
- interrupt-parent = <&MPIC>;
+ interrupt-parent = <&mpic>;
reg = <0x2>;
device_type = "ethernet-phy";
};
/* Mac address filled in by bootwrapper */
local-mac-address = [ 00 00 00 00 00 00 ];
interrupts = <0x1d 0x2 0x1e 0x2 0x22 0x2>;
- interrupt-parent = <&MPIC>;
+ interrupt-parent = <&mpic>;
phy-handle = <&PHY1>;
};
/* Mac address filled in by bootwrapper */
local-mac-address = [ 00 00 00 00 00 00 ];
interrupts = <0x23 0x2 0x24 0x2 0x28 0x2>;
- interrupt-parent = <&MPIC>;
+ interrupt-parent = <&mpic>;
phy-handle = <&PHY2>;
};
- MPIC: pic@40000 {
+ mpic: pic@40000 {
#address-cells = <0>;
#interrupt-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
interrupt-controller;
interrupts = <0x2e 0x2>;
- interrupt-parent = <&MPIC>;
+ interrupt-parent = <&mpic>;
reg = <0x90c00 0x80>;
compatible = "fsl,mpc8560-cpm-pic", "fsl,cpm2-pic";
};
fsl,mdc-pin = <25>;
PHY0: ethernet-phy@0 {
- interrupt-parent = <&MPIC>;
+ interrupt-parent = <&mpic>;
reg = <0x0>;
device_type = "ethernet-phy";
};