drm/i915/tgl: Update cdclk voltage level settings
authorMatt Roper <matthew.d.roper@intel.com>
Fri, 7 Feb 2020 00:14:17 +0000 (16:14 -0800)
committerMatt Roper <matthew.d.roper@intel.com>
Mon, 10 Feb 2020 17:51:44 +0000 (09:51 -0800)
A recent bspec update added an extra voltage level that we didn't have
on ICL and new criteria for selecting the level.

Bspec: 49208
Cc: José Roberto de Souza <jose.souza@intel.com>
Cc: Anusha Srivatsa <anusha.srivatsa@intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20200207001417.1229251-2-matthew.d.roper@intel.com
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
drivers/gpu/drm/i915/display/intel_cdclk.c
drivers/gpu/drm/i915/display/intel_ddi.c

index 7154a22883106a62e2a8590e3f86461382fd4df0..55b5dd169c516a6f14a9a699b798eda9021908b4 100644 (file)
@@ -1295,6 +1295,18 @@ static u8 ehl_calc_voltage_level(int cdclk)
                return 0;
 }
 
+static u8 tgl_calc_voltage_level(int cdclk)
+{
+       if (cdclk > 556800)
+               return 3;
+       else if (cdclk > 326400)
+               return 2;
+       else if (cdclk > 312000)
+               return 1;
+       else
+               return 0;
+}
+
 static void cnl_readout_refclk(struct drm_i915_private *dev_priv,
                               struct intel_cdclk_config *cdclk_config)
 {
@@ -2711,7 +2723,12 @@ void intel_update_rawclk(struct drm_i915_private *dev_priv)
  */
 void intel_init_cdclk_hooks(struct drm_i915_private *dev_priv)
 {
-       if (IS_ELKHARTLAKE(dev_priv)) {
+       if (INTEL_GEN(dev_priv) >= 12) {
+               dev_priv->display.set_cdclk = bxt_set_cdclk;
+               dev_priv->display.modeset_calc_cdclk = bxt_modeset_calc_cdclk;
+               dev_priv->display.calc_voltage_level = tgl_calc_voltage_level;
+               dev_priv->cdclk.table = icl_cdclk_table;
+       } else if (IS_ELKHARTLAKE(dev_priv)) {
                dev_priv->display.set_cdclk = bxt_set_cdclk;
                dev_priv->display.modeset_calc_cdclk = bxt_modeset_calc_cdclk;
                dev_priv->display.calc_voltage_level = ehl_calc_voltage_level;
index ad319224dd54961b797b09d1277527dbc04a89e6..544e15603ef9e5d5333e3faa63cae06970cbb824 100644 (file)
@@ -4238,7 +4238,9 @@ static bool intel_ddi_is_audio_enabled(struct drm_i915_private *dev_priv,
 void intel_ddi_compute_min_voltage_level(struct drm_i915_private *dev_priv,
                                         struct intel_crtc_state *crtc_state)
 {
-       if (IS_ELKHARTLAKE(dev_priv) && crtc_state->port_clock > 594000)
+       if (INTEL_GEN(dev_priv) >= 12 && crtc_state->port_clock > 594000)
+               crtc_state->min_voltage_level = 2;
+       else if (IS_ELKHARTLAKE(dev_priv) && crtc_state->port_clock > 594000)
                crtc_state->min_voltage_level = 3;
        else if (INTEL_GEN(dev_priv) >= 11 && crtc_state->port_clock > 594000)
                crtc_state->min_voltage_level = 1;