drm/i915/fbc: fix FBC_COMPRESSION_MASK on BDW+

Its size is 11:0 instead of 10:0. Found by inspecting the spec. I'm
not aware of any real-world IGT failures caused by this.

Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/1477065346-13736-2-git-send-email-paulo.r.zanoni@intel.com

diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
index f85e6fbf27f4790814e22daa15ec2bbdd1dc2c2c..a5e575a7dbde8c7e105bfeea01fff069addb48f2 100644 (file)
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -1683,11 +1683,13 @@ static int i915_fbc_status(struct seq_file *m, void *unused)
                seq_printf(m, "FBC disabled: %s\n",
                           dev_priv->fbc.no_fbc_reason);
 
-       if (intel_fbc_is_active(dev_priv) &&
-           INTEL_GEN(dev_priv) >= 7)
+       if (intel_fbc_is_active(dev_priv) && INTEL_GEN(dev_priv) >= 7) {
+               uint32_t mask = INTEL_GEN(dev_priv) >= 8 ?
+                               BDW_FBC_COMPRESSION_MASK :
+                               IVB_FBC_COMPRESSION_MASK;
                seq_printf(m, "Compressing: %s\n",
-                          yesno(I915_READ(FBC_STATUS2) &
-                                FBC_COMPRESSION_MASK));
+                          yesno(I915_READ(FBC_STATUS2) & mask));
+       }
 
        mutex_unlock(&dev_priv->fbc.lock);
        intel_runtime_pm_put(dev_priv);

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 00efaa13974d93295275be42a06350afde86270e..a9be3f037f43c37eb0910575cf4edb323589fd2e 100644 (file)
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -2188,8 +2188,9 @@ enum skl_disp_power_wells {
 #define FBC_FENCE_OFF          _MMIO(0x3218) /* BSpec typo has 321Bh */
 #define FBC_TAG(i)             _MMIO(0x3300 + (i) * 4)
 
-#define FBC_STATUS2            _MMIO(0x43214)
-#define  FBC_COMPRESSION_MASK  0x7ff
+#define FBC_STATUS2                    _MMIO(0x43214)
+#define  IVB_FBC_COMPRESSION_MASK      0x7ff
+#define  BDW_FBC_COMPRESSION_MASK      0xfff
 
 #define FBC_LL_SIZE            (1536)