driver/ddr/fsl: Update DDR4 MR6 for Vref range

MR6 bit 6 is set accrodingly for range 1 or 2, per JEDEC spec.

Signed-off-by: York Sun <yorksun@freescale.com>

diff --git a/drivers/ddr/fsl/ctrl_regs.c b/drivers/ddr/fsl/ctrl_regs.c
index 8543679108751b1597137ecc8e859226d71fdb9b..36bf647791b29cd0ec9f33dab09d86e83a4bca95 100644 (file)
--- a/drivers/ddr/fsl/ctrl_regs.c
+++ b/drivers/ddr/fsl/ctrl_regs.c
@@ -1186,6 +1186,9 @@ static void set_ddr_sdram_mode_10(const unsigned int ctrl_num,
 
        esdmode6 = ((tccdl_min - 4) & 0x7) << 10;
 
+       if (popts->ddr_cdr2 & DDR_CDR2_VREF_RANGE_2)
+               esdmode6 |= 1 << 6;     /* Range 2 */
+
        ddr->ddr_sdram_mode_10 = (0
                                 | ((esdmode6 & 0xffff) << 16)
                                 | ((esdmode7 & 0xffff) << 0)