drm/nouveau/clk/gf100-: Clean up PLL locking test

Corresponds with GT215. Don't rely on the lock test logic being
unconditionally enabled, and disable test logic when done (presumably
to save power).

v2: Remove warning, nvkm_msec already warns on time-out

Signed-off-by: Roy Spliet <nouveau@spliet.org>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>

diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/clk/gf100.c b/drivers/gpu/drm/nouveau/nvkm/subdev/clk/gf100.c
index 78c449b417b74c18b6d03c0eacb9b1b4894026a9..026baffa3065a73cffb9a2084cb47f5204d7eb7c 100644 (file)
--- a/drivers/gpu/drm/nouveau/nvkm/subdev/clk/gf100.c
+++ b/drivers/gpu/drm/nouveau/nvkm/subdev/clk/gf100.c
@@ -366,11 +366,17 @@ gf100_clk_prog_2(struct gf100_clk *clk, int idx)
                if (info->coef) {
                        nvkm_wr32(device, addr + 0x04, info->coef);
                        nvkm_mask(device, addr + 0x00, 0x00000001, 0x00000001);
+
+                       /* Test PLL lock */
+                       nvkm_mask(device, addr + 0x00, 0x00000010, 0x00000000);
                        nvkm_msec(device, 2000,
                                if (nvkm_rd32(device, addr + 0x00) & 0x00020000)
                                        break;
                        );
-                       nvkm_mask(device, addr + 0x00, 0x00020004, 0x00000004);
+                       nvkm_mask(device, addr + 0x00, 0x00000010, 0x00000010);
+
+                       /* Enable sync mode */
+                       nvkm_mask(device, addr + 0x00, 0x00000004, 0x00000004);
                }
        }
 }

diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/clk/gk104.c b/drivers/gpu/drm/nouveau/nvkm/subdev/clk/gk104.c
index 975c401bccab8c4e3ab69e5daec2de65ffd09ea6..06bc0d2d6ae195bb6c9cf5f88141bfef8e572a31 100644 (file)
--- a/drivers/gpu/drm/nouveau/nvkm/subdev/clk/gk104.c
+++ b/drivers/gpu/drm/nouveau/nvkm/subdev/clk/gk104.c
@@ -393,11 +393,17 @@ gk104_clk_prog_2(struct gk104_clk *clk, int idx)
        if (info->coef) {
                nvkm_wr32(device, addr + 0x04, info->coef);
                nvkm_mask(device, addr + 0x00, 0x00000001, 0x00000001);
+
+               /* Test PLL lock */
+               nvkm_mask(device, addr + 0x00, 0x00000010, 0x00000000);
                nvkm_msec(device, 2000,
                        if (nvkm_rd32(device, addr + 0x00) & 0x00020000)
                                break;
                );
-               nvkm_mask(device, addr + 0x00, 0x00020004, 0x00000004);
+               nvkm_mask(device, addr + 0x00, 0x00000010, 0x00000010);
+
+               /* Enable sync mode */
+               nvkm_mask(device, addr + 0x00, 0x00000004, 0x00000004);
        }
 }