usb: dwc2: WA for Full speed ISOC IN in DDMA mode.

By clearing NAK status of EP, core will send ZLP
to IN token and assert NAK interrupt relying
on TxFIFO status only.

The WA applies only to core versions from 2.72a
to 4.00a (including both). Also for FS_IOT_1.00a
and HS_IOT_1.00a.

Signed-off-by: Artur Petrosyan <arturp@synopsys.com>
Signed-off-by: Minas Harutyunyan <hminas@synopsys.com>
Signed-off-by: Felipe Balbi <felipe.balbi@linux.intel.com>

diff --git a/drivers/usb/dwc2/core.h b/drivers/usb/dwc2/core.h
index d83be5651f870a5a45f8194693c105dfb474394e..a666e0758a99a4a662918c57489ad1fff46a4683 100644 (file)
--- a/drivers/usb/dwc2/core.h
+++ b/drivers/usb/dwc2/core.h
@@ -985,6 +985,7 @@ struct dwc2_hsotg {
 
        /* DWC OTG HW Release versions */
 #define DWC2_CORE_REV_2_71a    0x4f54271a
+#define DWC2_CORE_REV_2_72a     0x4f54272a
 #define DWC2_CORE_REV_2_80a    0x4f54280a
 #define DWC2_CORE_REV_2_90a    0x4f54290a
 #define DWC2_CORE_REV_2_91a    0x4f54291a
@@ -992,6 +993,7 @@ struct dwc2_hsotg {
 #define DWC2_CORE_REV_2_94a    0x4f54294a
 #define DWC2_CORE_REV_3_00a    0x4f54300a
 #define DWC2_CORE_REV_3_10a    0x4f54310a
+#define DWC2_CORE_REV_4_00a    0x4f54400a
 #define DWC2_FS_IOT_REV_1_00a  0x5531100a
 #define DWC2_HS_IOT_REV_1_00a  0x5532100a
 

diff --git a/drivers/usb/dwc2/gadget.c b/drivers/usb/dwc2/gadget.c
index 6c32bf26e48e9660cf5415f0eb8029953fa0aa3c..83cb5577a52f118b13c58bfd68bb0532279bda6f 100644 (file)
--- a/drivers/usb/dwc2/gadget.c
+++ b/drivers/usb/dwc2/gadget.c
@@ -3928,6 +3928,27 @@ static int dwc2_hsotg_ep_enable(struct usb_ep *ep,
        if (index && !hs_ep->isochronous)
                epctrl |= DXEPCTL_SETD0PID;
 
+       /* WA for Full speed ISOC IN in DDMA mode.
+        * By Clear NAK status of EP, core will send ZLP
+        * to IN token and assert NAK interrupt relying
+        * on TxFIFO status only
+        */
+
+       if (hsotg->gadget.speed == USB_SPEED_FULL &&
+           hs_ep->isochronous && dir_in) {
+               /* The WA applies only to core versions from 2.72a
+                * to 4.00a (including both). Also for FS_IOT_1.00a
+                * and HS_IOT_1.00a.
+                */
+               u32 gsnpsid = dwc2_readl(hsotg->regs + GSNPSID);
+
+               if ((gsnpsid >= DWC2_CORE_REV_2_72a &&
+                    gsnpsid <= DWC2_CORE_REV_4_00a) ||
+                    gsnpsid == DWC2_FS_IOT_REV_1_00a ||
+                    gsnpsid == DWC2_HS_IOT_REV_1_00a)
+                       epctrl |= DXEPCTL_CNAK;
+       }
+
        dev_dbg(hsotg->dev, "%s: write DxEPCTL=0x%08x\n",
                __func__, epctrl);