drm: meson: vpp: use proper macros instead of magic constants

This patch add new macros which are used to set the following
registers:
- VPP_OSD_SCALE_COEF_IDX
- VPP_DOLBY_CTRL
- VPP_OFIFO_SIZE
- VPP_HOLD_LINES
- VPP_SC_MISC
- VPP_VADJ_CTRL

Signed-off-by: Julien Masson <jmasson@baylibre.com>
Reviewed-by: Neil Armstrong <narmstrong@baylibre.com>
[narmstrong: put back 0x1020080 in VPP_DUMMY_DATA1 for GXM]
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Link: https://patchwork.freedesktop.org/patch/msgid/86tvcf82eu.fsf@baylibre.com

diff --git a/drivers/gpu/drm/meson/meson_registers.h b/drivers/gpu/drm/meson/meson_registers.h
index dfa693c3f16a6015566c12943d0c54119959ea77..ffaf04e1305b7ec277cb398b6489b9026dc42dd3 100644 (file)
--- a/drivers/gpu/drm/meson/meson_registers.h
+++ b/drivers/gpu/drm/meson/meson_registers.h
@@ -341,6 +341,7 @@
 #define VPP_LINE_IN_LENGTH 0x1d01
 #define VPP_PIC_IN_HEIGHT 0x1d02
 #define VPP_SCALE_COEF_IDX 0x1d03
+#define                VPP_SCALE_HORIZONTAL_COEF       BIT(8)
 #define VPP_SCALE_COEF 0x1d04
 #define VPP_VSC_REGION12_STARTP 0x1d05
 #define VPP_VSC_REGION34_STARTP 0x1d06
@@ -377,6 +378,8 @@
 #define VPP_PREBLEND_H_SIZE 0x1d20
 #define VPP_POSTBLEND_H_SIZE 0x1d21
 #define VPP_HOLD_LINES 0x1d22
+#define                VPP_POSTBLEND_HOLD_LINES(lines) (lines & 0xf)
+#define                VPP_PREBLEND_HOLD_LINES(lines)  ((lines & 0xf) << 8)
 #define VPP_BLEND_ONECOLOR_CTRL 0x1d23
 #define VPP_PREBLEND_CURRENT_XY 0x1d24
 #define VPP_POSTBLEND_CURRENT_XY 0x1d25
@@ -395,6 +398,8 @@
 #define                VPP_OSD2_PREBLEND       BIT(17)
 #define                VPP_COLOR_MNG_ENABLE    BIT(28)
 #define VPP_OFIFO_SIZE 0x1d27
+#define                VPP_OFIFO_SIZE_MASK             GENMASK(13, 0)
+#define                VPP_OFIFO_SIZE_DEFAULT          (0xfff << 20 | 0x1000)
 #define VPP_FIFO_STATUS 0x1d28
 #define VPP_SMOKE_CTRL 0x1d29
 #define VPP_SMOKE1_VAL 0x1d2a
@@ -410,6 +415,8 @@
 #define VPP_HSC_PHASE_CTRL1 0x1d34
 #define VPP_HSC_INI_PAT_CTRL 0x1d35
 #define VPP_VADJ_CTRL 0x1d40
+#define                VPP_MINUS_BLACK_LVL_VADJ1_ENABLE BIT(1)
+
 #define VPP_VADJ1_Y 0x1d41
 #define VPP_VADJ1_MA_MB 0x1d42
 #define VPP_VADJ1_MC_MD 0x1d43
@@ -469,6 +476,7 @@
 #define VPP_PEAKING_VGAIN 0x1d92
 #define VPP_PEAKING_NLP_1 0x1d93
 #define VPP_DOLBY_CTRL 0x1d93
+#define VPP_PPS_DUMMY_DATA_MODE (1 << 17)
 #define VPP_PEAKING_NLP_2 0x1d94
 #define VPP_PEAKING_NLP_3 0x1d95
 #define VPP_PEAKING_NLP_4 0x1d96

diff --git a/drivers/gpu/drm/meson/meson_vpp.c b/drivers/gpu/drm/meson/meson_vpp.c
index cbe6cf46e541d8777c8be80153c829eccfcffe3f..1429f3be602810f04f960ef8b69ef03a3beee2d5 100644 (file)
--- a/drivers/gpu/drm/meson/meson_vpp.c
+++ b/drivers/gpu/drm/meson/meson_vpp.c
@@ -56,7 +56,7 @@ static void meson_vpp_write_scaling_filter_coefs(struct meson_drm *priv,
 {
        int i;
 
-       writel_relaxed(is_horizontal ? BIT(8) : 0,
+       writel_relaxed(is_horizontal ? VPP_SCALE_HORIZONTAL_COEF : 0,
                        priv->io_base + _REG(VPP_OSD_SCALE_COEF_IDX));
        for (i = 0; i < 33; i++)
                writel_relaxed(coefs[i],
@@ -81,7 +81,7 @@ static void meson_vpp_write_vd_scaling_filter_coefs(struct meson_drm *priv,
 {
        int i;
 
-       writel_relaxed(is_horizontal ? BIT(8) : 0,
+       writel_relaxed(is_horizontal ? VPP_SCALE_HORIZONTAL_COEF : 0,
                        priv->io_base + _REG(VPP_SCALE_COEF_IDX));
        for (i = 0; i < 33; i++)
                writel_relaxed(coefs[i],
@@ -96,7 +96,8 @@ void meson_vpp_init(struct meson_drm *priv)
        else if (meson_vpu_is_compatible(priv, "amlogic,meson-gxm-vpu")) {
                writel_bits_relaxed(0xff << 16, 0xff << 16,
                                    priv->io_base + _REG(VIU_MISC_CTRL1));
-               writel_relaxed(0x20000, priv->io_base + _REG(VPP_DOLBY_CTRL));
+               writel_relaxed(VPP_PPS_DUMMY_DATA_MODE,
+                              priv->io_base + _REG(VPP_DOLBY_CTRL));
                writel_relaxed(0x1020080,
                                priv->io_base + _REG(VPP_DUMMY_DATA1));
        } else if (meson_vpu_is_compatible(priv, "amlogic,meson-g12a-vpu"))
@@ -104,12 +105,13 @@ void meson_vpp_init(struct meson_drm *priv)
 
        /* Initialize vpu fifo control registers */
        if (meson_vpu_is_compatible(priv, "amlogic,meson-g12a-vpu"))
-               writel_relaxed(0xfff << 20 | 0x1000,
+               writel_relaxed(VPP_OFIFO_SIZE_DEFAULT,
                               priv->io_base + _REG(VPP_OFIFO_SIZE));
        else
-               writel_relaxed(readl_relaxed(priv->io_base + _REG(VPP_OFIFO_SIZE)) |
-                               0x77f, priv->io_base + _REG(VPP_OFIFO_SIZE));
-       writel_relaxed(0x08080808, priv->io_base + _REG(VPP_HOLD_LINES));
+               writel_bits_relaxed(VPP_OFIFO_SIZE_MASK, 0x77f,
+                                   priv->io_base + _REG(VPP_OFIFO_SIZE));
+       writel_relaxed(VPP_POSTBLEND_HOLD_LINES(4) | VPP_PREBLEND_HOLD_LINES(4),
+                      priv->io_base + _REG(VPP_HOLD_LINES));
 
        if (!meson_vpu_is_compatible(priv, "amlogic,meson-g12a-vpu")) {
                /* Turn off preblend */
@@ -137,10 +139,15 @@ void meson_vpp_init(struct meson_drm *priv)
        writel_relaxed(0, priv->io_base + _REG(VPP_OSD_SC_CTRL0));
        writel_relaxed(0, priv->io_base + _REG(VPP_OSD_VSC_CTRL0));
        writel_relaxed(0, priv->io_base + _REG(VPP_OSD_HSC_CTRL0));
-       writel_relaxed(4 | (4 << 8) | BIT(15),
+
+       /* Set horizontal/vertical bank length and enable video scale out */
+       writel_relaxed(VPP_VSC_BANK_LENGTH(4) | VPP_HSC_BANK_LENGTH(4) |
+                      VPP_SC_VD_EN_ENABLE,
                       priv->io_base + _REG(VPP_SC_MISC));
 
-       writel_relaxed(1, priv->io_base + _REG(VPP_VADJ_CTRL));
+       /* Enable minus black level for vadj1 */
+       writel_relaxed(VPP_MINUS_BLACK_LVL_VADJ1_ENABLE,
+                      priv->io_base + _REG(VPP_VADJ_CTRL));
 
        /* Write in the proper filter coefficients. */
        meson_vpp_write_scaling_filter_coefs(priv,