Unmask SError interrupt and clear SCR_EL3.EA bit

This patch disables routing of external aborts from lower exception levels to
EL3 and ensures that a SError interrupt generated as a result of execution in
EL3 is taken locally instead of a lower exception level.

The SError interrupt is enabled in the TSP code only when the operation has not
been directly initiated by the normal world. This is to prevent the possibility
of an asynchronous external abort which originated in normal world from being
taken when execution is in S-EL1.

Fixes ARM-software/tf-issues#153

Change-Id: I157b996c75996d12fd86d27e98bc73dd8bce6cd5

diff --git a/bl1/aarch64/bl1_arch_setup.c b/bl1/aarch64/bl1_arch_setup.c
index eeaa24aff142d8aca573203d0808f40a40de9f7f..6a3f0623168e0760a12c57b62085bdf305b9c155 100644 (file)
--- a/bl1/aarch64/bl1_arch_setup.c
+++ b/bl1/aarch64/bl1_arch_setup.c
@@ -37,17 +37,8 @@
  ******************************************************************************/
 void bl1_arch_setup(void)
 {
-       /*
-        * Set the next EL to be AArch64, route external abort and SError
-        * interrupts to EL3
-        */
-       write_scr_el3(SCR_RES1_BITS | SCR_RW_BIT | SCR_EA_BIT);
-
-       /*
-        * Enable SError and Debug exceptions
-        */
-       enable_serror();
-       enable_debug_exceptions();
+       /* Set the next EL to be AArch64 */
+       write_scr_el3(SCR_RES1_BITS | SCR_RW_BIT);
 }
 
 /*******************************************************************************

diff --git a/bl1/aarch64/bl1_entrypoint.S b/bl1/aarch64/bl1_entrypoint.S
index dd7d78feb24152c1658e771c1272dbf903ba42e2..e7f92c71dd572160717d24b7b0d9d396e5a3bb83 100644 (file)
--- a/bl1/aarch64/bl1_entrypoint.S
+++ b/bl1/aarch64/bl1_entrypoint.S
@@ -76,6 +76,14 @@ func bl1_entrypoint
         */
        adr     x0, bl1_exceptions
        msr     vbar_el3, x0
+       isb
+
+       /* ---------------------------------------------
+        * Enable the SError interrupt now that the
+        * exception vectors have been setup.
+        * ---------------------------------------------
+        */
+       msr     daifclr, #DAIF_ABT_BIT
 
        /* ---------------------------------------------------------------------
         * The initial state of the Architectural feature trap register

diff --git a/bl1/aarch64/bl1_exceptions.S b/bl1/aarch64/bl1_exceptions.S
index 8ab9df8611fedd0b87ad437e832843388fbf4de5..13b34b79fa94fe8d2b9946bcccede70082c51ff6 100644 (file)
--- a/bl1/aarch64/bl1_exceptions.S
+++ b/bl1/aarch64/bl1_exceptions.S
@@ -112,6 +112,9 @@ SErrorSPx:
         */
        .align  7
 SynchronousExceptionA64:
+       /* Enable the SError interrupt */
+       msr     daifclr, #DAIF_ABT_BIT
+
        /* ------------------------------------------------
         * Only a single SMC exception from BL2 to ask
         * BL1 to pass EL3 control to BL31 is expected

diff --git a/bl2/aarch64/bl2_entrypoint.S b/bl2/aarch64/bl2_entrypoint.S
index d3b0f558cf9f33845c05fdb02e09135822e0f1f5..2f058da9fc9e2f586d315e39ed1d98eb575b0b2b 100644 (file)
--- a/bl2/aarch64/bl2_entrypoint.S
+++ b/bl2/aarch64/bl2_entrypoint.S
@@ -53,6 +53,14 @@ func bl2_entrypoint
         */
        adr     x0, early_exceptions
        msr     vbar_el1, x0
+       isb
+
+       /* ---------------------------------------------
+        * Enable the SError interrupt now that the
+        * exception vectors have been setup.
+        * ---------------------------------------------
+        */
+       msr     daifclr, #DAIF_ABT_BIT
 
        /* ---------------------------------------------
         * Enable the instruction cache, stack pointer

diff --git a/bl31/aarch64/bl31_arch_setup.c b/bl31/aarch64/bl31_arch_setup.c
index f67881e6bea022c2442f20a004b5aee8e3930a48..a88b029ea38f2f00f62c741d3ee850a8f648d362 100644 (file)
--- a/bl31/aarch64/bl31_arch_setup.c
+++ b/bl31/aarch64/bl31_arch_setup.c
@@ -42,18 +42,8 @@
  ******************************************************************************/
 void bl31_arch_setup(void)
 {
-       /*
-        * Route external abort and SError interrupts to EL3
-        * other SCR bits will be configured before exiting to a lower exception
-        * level
-        */
-       write_scr_el3(SCR_RES1_BITS | SCR_EA_BIT);
-
-       /*
-        * Enable SError and Debug exceptions
-        */
-       enable_serror();
-       enable_debug_exceptions();
+       /* Set the RES1 bits in the SCR_EL3 */
+       write_scr_el3(SCR_RES1_BITS);
 
        /* Program the counter frequency */
        write_cntfrq_el0(plat_get_syscnt_freq());

diff --git a/bl31/aarch64/bl31_entrypoint.S b/bl31/aarch64/bl31_entrypoint.S
index c3a09bf33c873f902064b5d8ed600d89036e1b5f..a088c2e03c24354cf4f9f17723aef1be10ef267c 100644 (file)
--- a/bl31/aarch64/bl31_entrypoint.S
+++ b/bl31/aarch64/bl31_entrypoint.S
@@ -98,6 +98,14 @@ func bl31_entrypoint
         */
        adr     x1, runtime_exceptions
        msr     vbar_el3, x1
+       isb
+
+       /* ---------------------------------------------
+        * Enable the SError interrupt now that the
+        * exception vectors have been setup.
+        * ---------------------------------------------
+        */
+       msr     daifclr, #DAIF_ABT_BIT
 
        /* ---------------------------------------------------------------------
         * The initial state of the Architectural feature trap register

diff --git a/bl31/aarch64/runtime_exceptions.S b/bl31/aarch64/runtime_exceptions.S
index 996dedcb5c9702c0edb3702f7fa698a20ae3fe1c..f5be9e077883f098474dcbe8422e0484c991ff75 100644 (file)
--- a/bl31/aarch64/runtime_exceptions.S
+++ b/bl31/aarch64/runtime_exceptions.S
@@ -44,6 +44,9 @@
         * -----------------------------------------------------
         */
        .macro  handle_sync_exception
+       /* Enable the SError interrupt */
+       msr     daifclr, #DAIF_ABT_BIT
+
        str     x30, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_LR]
        mrs     x30, esr_el3
        ubfx    x30, x30, #ESR_EC_SHIFT, #ESR_EC_LENGTH
@@ -70,6 +73,9 @@
         * -----------------------------------------------------
         */
        .macro  handle_interrupt_exception label
+       /* Enable the SError interrupt */
+       msr     daifclr, #DAIF_ABT_BIT
+
        str     x30, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_LR]
        bl      save_gp_registers
 

diff --git a/bl32/tsp/aarch64/tsp_entrypoint.S b/bl32/tsp/aarch64/tsp_entrypoint.S
index 75ee4434978ae485fdf3514d8561fc9fb576aaa7..002c41b81a5b2ed1cefcedda0d19ee08fc46ec7b 100644 (file)
--- a/bl32/tsp/aarch64/tsp_entrypoint.S
+++ b/bl32/tsp/aarch64/tsp_entrypoint.S
@@ -77,6 +77,14 @@ func tsp_entrypoint
         */
        adr     x0, tsp_exceptions
        msr     vbar_el1, x0
+       isb
+
+       /* ---------------------------------------------
+        * Enable the SError interrupt now that the
+        * exception vectors have been setup.
+        * ---------------------------------------------
+        */
+       msr     daifclr, #DAIF_ABT_BIT
 
        /* ---------------------------------------------
         * Enable the instruction cache, stack pointer
@@ -186,6 +194,10 @@ func tsp_cpu_on_entry
         */
        adr     x0, tsp_exceptions
        msr     vbar_el1, x0
+       isb
+
+       /* Enable the SError interrupt */
+       msr     daifclr, #DAIF_ABT_BIT
 
        /* ---------------------------------------------
         * Enable the instruction cache, stack pointer

diff --git a/bl32/tsp/aarch64/tsp_exceptions.S b/bl32/tsp/aarch64/tsp_exceptions.S
index f84b5e09901fb7571dc2e957cede506c2c4ddde2..4c0d4361e76ad726d98dc4fd9a30e997e7e76b55 100644 (file)
--- a/bl32/tsp/aarch64/tsp_exceptions.S
+++ b/bl32/tsp/aarch64/tsp_exceptions.S
@@ -120,6 +120,9 @@ sync_exception_sp_elx:
 
        .align  7
 irq_sp_elx:
+       /* Enable the SError interrupt */
+       msr     daifclr, #DAIF_ABT_BIT
+
        save_caller_regs_and_lr
        /* We just update some statistics in the handler */
        bl      tsp_irq_received
@@ -132,6 +135,9 @@ irq_sp_elx:
 
        .align  7
 fiq_sp_elx:
+       /* Enable the SError interrupt */
+       msr     daifclr, #DAIF_ABT_BIT
+
        save_caller_regs_and_lr
        bl      tsp_fiq_handler
        cbz     x0, fiq_sp_elx_done

diff --git a/services/std_svc/psci/psci_entry.S b/services/std_svc/psci/psci_entry.S
index e9ad1305b8587d61955669be1f4c897b6aedf312..68b917e3971eb61f3f037ad276e6496a0e9e90db 100644 (file)
--- a/services/std_svc/psci/psci_entry.S
+++ b/services/std_svc/psci/psci_entry.S
@@ -87,6 +87,13 @@ psci_aff_common_finish_entry:
        msr     vbar_el3, x0
        isb
 
+       /* ---------------------------------------------
+        * Enable the SError interrupt now that the
+        * exception vectors have been setup.
+        * ---------------------------------------------
+        */
+       msr     daifclr, #DAIF_ABT_BIT
+
        /* ---------------------------------------------
         * Use SP_EL0 for the C runtime stack.
         * ---------------------------------------------