ramips: dts: rt3050: reset FE and ESW cores together

Failing to do so will cause the DMA engine to not initialize properly
and fail to forward packets between them, and in some cases will cause
spurious transmission with size exceeding allowed packet size, causing a
kernel panic.

This is behaviour of downstream driver as well, however I
haven't observed bug reports about this SoC in the wild, so this
commit's purpose is to align this chip with all other SoC's - MT7620
were already using this arrangement.

Fixes: 60fadae62b64 ("ramips: ethernet: ralink: move reset of the esw into the esw instead of fe")
Signed-off-by: Lech Perczak <lech.perczak@gmail.com>
(cherry picked from commit c5a399f372535886582f89f3da624ae7465c8ff4)
Signed-off-by: Lech Perczak <lech.perczak@gmail.com>

diff --git a/target/linux/ramips/dts/rt3050.dtsi b/target/linux/ramips/dts/rt3050.dtsi
index 492474fdc43f74325df78f28cd6569dda0d18143..6077dd50085c5f057b57a06940d862761c2c429a 100644 (file)
--- a/target/linux/ramips/dts/rt3050.dtsi
+++ b/target/linux/ramips/dts/rt3050.dtsi
@@ -306,8 +306,8 @@
                compatible = "ralink,rt3050-eth";
                reg = <0x10100000 0x10000>;
 
-               resets = <&rstctrl 21>;
-               reset-names = "fe";
+               resets = <&rstctrl 21>, <&rstctrl 23>;
+               reset-names = "fe", "esw";
 
                interrupt-parent = <&cpuintc>;
                interrupts = <5>;
@@ -319,8 +319,8 @@
                compatible = "ralink,rt3050-esw";
                reg = <0x10110000 0x8000>;
 
-               resets = <&rstctrl 23 &rstctrl 24>;
-               reset-names = "esw", "ephy";
+               resets = <&rstctrl 24>;
+               reset-names = "ephy";
 
                interrupt-parent = <&intc>;
                interrupts = <17>;