Cortex-A17: Implement workaround for errata 852421

Change-Id: Ic3004fc43229d63c5a59ca74c1837fb0604e1f33
Signed-off-by: Ambroise Vincent <ambroise.vincent@arm.com>

diff --git a/docs/cpu-specific-build-macros.rst b/docs/cpu-specific-build-macros.rst
index 8c951de00f6b2a816ee9c3721fa42bde35d86468..ae0cfd9c2b87382126f4ed8a6e47f7dd99f55f2b 100644 (file)
--- a/docs/cpu-specific-build-macros.rst
+++ b/docs/cpu-specific-build-macros.rst
@@ -79,6 +79,11 @@ For Cortex-A15, the following errata build flags are defined :
 -  ``ERRATA_A15_827671``: This applies errata 827671 workaround to Cortex-A15
    CPU. This needs to be enabled only for revision >= r3p0 of the CPU.
 
+For Cortex-A17, the following errata build flags are defined :
+
+-  ``ERRATA_A17_852421``: This applies errata 852421 workaround to Cortex-A17
+   CPU. This needs to be enabled only for revision <= r1p2 of the CPU.
+
 For Cortex-A53, the following errata build flags are defined :
 
 -  ``ERRATA_A53_819472``: This applies errata 819472 workaround to all

diff --git a/include/lib/cpus/aarch32/cortex_a17.h b/include/lib/cpus/aarch32/cortex_a17.h
index 4b05216508ef56b9a159bc2d5501e031f72447e6..89a8eb6107cc4170ebde274caee2a98a4e3f2427 100644 (file)
--- a/include/lib/cpus/aarch32/cortex_a17.h
+++ b/include/lib/cpus/aarch32/cortex_a17.h
@@ -19,4 +19,9 @@
  ******************************************************************************/
 #define CORTEX_A17_ACTLR_SMP_BIT       (U(1) << 6)
 
+/*******************************************************************************
+ * Implementation defined register specific definitions.
+ ******************************************************************************/
+#define CORTEX_A17_IMP_DEF_REG1                p15, 0, c15, c0, 1
+
 #endif /* CORTEX_A17_H */

diff --git a/lib/cpus/aarch32/cortex_a17.S b/lib/cpus/aarch32/cortex_a17.S
index b84c1267198f9bdeb152df3bf6b1b37667cec0e3..87e8c8d02b1120c359158a717f3f3ba5af7798d0 100644 (file)
--- a/lib/cpus/aarch32/cortex_a17.S
+++ b/lib/cpus/aarch32/cortex_a17.S
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2017-2019, ARM Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -35,6 +35,34 @@ func cortex_a17_enable_smp
        bx      lr
 endfunc cortex_a17_enable_smp
 
+       /* ----------------------------------------------------
+        * Errata Workaround for Cortex A17 Errata #852421.
+        * This applies only to revision <= r1p2 of Cortex A17.
+        * Inputs:
+        * r0: variant[4:7] and revision[0:3] of current cpu.
+        * Shall clobber: r0-r3
+        * ----------------------------------------------------
+        */
+func errata_a17_852421_wa
+       /*
+        * Compare r0 against revision r1p2
+        */
+       mov     r2, lr
+       bl      check_errata_852421
+       cmp     r0, #ERRATA_NOT_APPLIES
+       beq     1f
+       ldcopr  r0, CORTEX_A17_IMP_DEF_REG1
+       orr     r0, r0, #(1<<24)
+       stcopr  r0, CORTEX_A17_IMP_DEF_REG1
+1:
+       bx      r2
+endfunc errata_a17_852421_wa
+
+func check_errata_852421
+       mov     r1, #0x12
+       b       cpu_rev_var_ls
+endfunc check_errata_852421
+
 func check_errata_cve_2017_5715
 #if WORKAROUND_CVE_2017_5715
        mov     r0, #ERRATA_APPLIES
@@ -58,6 +86,7 @@ func cortex_a17_errata_report
         * Report all errata. The revision-variant information is passed to
         * checking functions of each errata.
         */
+       report_errata ERRATA_A17_852421, cortex_a17, 852421
        report_errata WORKAROUND_CVE_2017_5715, cortex_a17, cve_2017_5715
 
        pop     {r12, lr}
@@ -66,12 +95,21 @@ endfunc cortex_a17_errata_report
 #endif
 
 func cortex_a17_reset_func
+       mov     r5, lr
+       bl      cpu_get_rev_var
+
+#if ERRATA_A17_852421
+       bl      errata_a17_852421_wa
+#endif
+
 #if IMAGE_BL32 && WORKAROUND_CVE_2017_5715
        ldr     r0, =workaround_bpiall_runtime_exceptions
        stcopr  r0, VBAR
        stcopr  r0, MVBAR
        /* isb will be applied in the course of the reset func */
 #endif
+
+       mov     lr, r5
        b       cortex_a17_enable_smp
 endfunc cortex_a17_reset_func
 

diff --git a/lib/cpus/cpu-ops.mk b/lib/cpus/cpu-ops.mk
index f178f1af2228044eb15385c925693da84bd5ab17..9ccd78779340530c25044933ba67180c899b4fc0 100644 (file)
--- a/lib/cpus/cpu-ops.mk
+++ b/lib/cpus/cpu-ops.mk
@@ -61,6 +61,10 @@ ERRATA_A15_816470    ?=0
 # only to revision >= r3p0 of the Cortex A15 cpu.
 ERRATA_A15_827671      ?=0
 
+# Flag to apply erratum 852421 workaround during reset. This erratum applies
+# only to revision <= r1p2 of the Cortex A17 cpu.
+ERRATA_A17_852421      ?=0
+
 # Flag to apply erratum 819472 workaround during reset. This erratum applies
 # only to revision <= r0p1 of the Cortex A53 cpu.
 ERRATA_A53_819472      ?=0
@@ -212,6 +216,10 @@ $(eval $(call add_define,ERRATA_A15_816470))
 $(eval $(call assert_boolean,ERRATA_A15_827671))
 $(eval $(call add_define,ERRATA_A15_827671))
 
+# Process ERRATA_A17_852421 flag
+$(eval $(call assert_boolean,ERRATA_A17_852421))
+$(eval $(call add_define,ERRATA_A17_852421))
+
 # Process ERRATA_A53_819472 flag
 $(eval $(call assert_boolean,ERRATA_A53_819472))
 $(eval $(call add_define,ERRATA_A53_819472))