ARM: atmel: sama5d4_xplained: enable spl support

Signed-off-by: Bo Shen <voice.shen@atmel.com>

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 8be14fe8e3507f7fb21620fb7d49434b04503e9c..5cfca1b831fe6e0155e5223e2f283d5aea8e912b 100644 (file)
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -525,6 +525,7 @@ config TARGET_SAMA5D3XEK
 config TARGET_SAMA5D4_XPLAINED
        bool "Support sama5d4_xplained"
        select CPU_V7
+       select SUPPORT_SPL
 
 config TARGET_SAMA5D4EK
        bool "Support sama5d4ek"

diff --git a/board/atmel/sama5d4_xplained/sama5d4_xplained.c b/board/atmel/sama5d4_xplained/sama5d4_xplained.c
index 1c5b92c8b580b7d5a433e95505e98fe1ed4117cc..bc2aa38b924c87fef536d79d7206c3ffb44dccd3 100644 (file)
--- a/board/atmel/sama5d4_xplained/sama5d4_xplained.c
+++ b/board/atmel/sama5d4_xplained/sama5d4_xplained.c
@@ -10,6 +10,7 @@
 #include <asm/arch/at91_common.h>
 #include <asm/arch/at91_pmc.h>
 #include <asm/arch/at91_rstc.h>
+#include <asm/arch/atmel_mpddrc.h>
 #include <asm/arch/atmel_usba_udc.h>
 #include <asm/arch/gpio.h>
 #include <asm/arch/clk.h>
@@ -326,3 +327,87 @@ int board_eth_init(bd_t *bis)
 
        return rc;
 }
+
+/* SPL */
+#ifdef CONFIG_SPL_BUILD
+void spl_board_init(void)
+{
+#ifdef CONFIG_SYS_USE_MMC
+       sama5d4_xplained_mci1_hw_init();
+#elif CONFIG_SYS_USE_NANDFLASH
+       sama5d4_xplained_nand_hw_init();
+#elif CONFIG_SYS_USE_SERIALFLASH
+       sama5d4_xplained_spi0_hw_init();
+#endif
+}
+
+static void ddr2_conf(struct atmel_mpddr *ddr2)
+{
+       ddr2->md = (ATMEL_MPDDRC_MD_DBW_32_BITS | ATMEL_MPDDRC_MD_DDR2_SDRAM);
+
+       ddr2->cr = (ATMEL_MPDDRC_CR_NC_COL_10 |
+                   ATMEL_MPDDRC_CR_NR_ROW_14 |
+                   ATMEL_MPDDRC_CR_CAS_DDR_CAS3 |
+                   ATMEL_MPDDRC_CR_NB_8BANKS |
+                   ATMEL_MPDDRC_CR_NDQS_DISABLED |
+                   ATMEL_MPDDRC_CR_DECOD_INTERLEAVED |
+                   ATMEL_MPDDRC_CR_UNAL_SUPPORTED);
+
+       ddr2->rtr = 0x2b0;
+
+       ddr2->tpr0 = (8 << ATMEL_MPDDRC_TPR0_TRAS_OFFSET |
+                     3 << ATMEL_MPDDRC_TPR0_TRCD_OFFSET |
+                     3 << ATMEL_MPDDRC_TPR0_TWR_OFFSET |
+                     10 << ATMEL_MPDDRC_TPR0_TRC_OFFSET |
+                     3 << ATMEL_MPDDRC_TPR0_TRP_OFFSET |
+                     2 << ATMEL_MPDDRC_TPR0_TRRD_OFFSET |
+                     2 << ATMEL_MPDDRC_TPR0_TWTR_OFFSET |
+                     2 << ATMEL_MPDDRC_TPR0_TMRD_OFFSET);
+
+       ddr2->tpr1 = (2 << ATMEL_MPDDRC_TPR1_TXP_OFFSET |
+                     200 << ATMEL_MPDDRC_TPR1_TXSRD_OFFSET |
+                     25 << ATMEL_MPDDRC_TPR1_TXSNR_OFFSET |
+                     23 << ATMEL_MPDDRC_TPR1_TRFC_OFFSET);
+
+       ddr2->tpr2 = (7 << ATMEL_MPDDRC_TPR2_TFAW_OFFSET |
+                     2 << ATMEL_MPDDRC_TPR2_TRTP_OFFSET |
+                     3 << ATMEL_MPDDRC_TPR2_TRPA_OFFSET |
+                     2 << ATMEL_MPDDRC_TPR2_TXARDS_OFFSET |
+                     8 << ATMEL_MPDDRC_TPR2_TXARD_OFFSET);
+}
+
+void mem_init(void)
+{
+       struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
+       struct atmel_mpddr ddr2;
+
+       ddr2_conf(&ddr2);
+
+       /* enable MPDDR clock */
+       at91_periph_clk_enable(ATMEL_ID_MPDDRC);
+       writel(0x4, &pmc->scer);
+
+       /* DDRAM2 Controller initialize */
+       ddr2_init(ATMEL_BASE_DDRCS, &ddr2);
+}
+
+void at91_pmc_init(void)
+{
+       struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
+       u32 tmp;
+
+       tmp = AT91_PMC_PLLAR_29 |
+             AT91_PMC_PLLXR_PLLCOUNT(0x3f) |
+             AT91_PMC_PLLXR_MUL(87) |
+             AT91_PMC_PLLXR_DIV(1);
+       at91_plla_init(tmp);
+
+       writel(0x0 << 8, &pmc->pllicpr);
+
+       tmp = AT91_PMC_MCKR_H32MXDIV |
+             AT91_PMC_MCKR_PLLADIV_2 |
+             AT91_PMC_MCKR_MDIV_3 |
+             AT91_PMC_MCKR_CSS_PLLA;
+       at91_mck_init(tmp);
+}
+#endif

diff --git a/configs/sama5d4_xplained_mmc_defconfig b/configs/sama5d4_xplained_mmc_defconfig
index 3720f3cfb40affea2bb62af99e82c5182423b6e2..73df28ccff1bf3e69fcfc7b24ea5dddc415586fb 100644 (file)
--- a/configs/sama5d4_xplained_mmc_defconfig
+++ b/configs/sama5d4_xplained_mmc_defconfig
@@ -1,3 +1,4 @@
+CONFIG_SPL=y
 CONFIG_SYS_EXTRA_OPTIONS="SAMA5D4,SYS_USE_MMC"
 +S:CONFIG_ARM=y
 +S:CONFIG_TARGET_SAMA5D4_XPLAINED=y

diff --git a/configs/sama5d4_xplained_nandflash_defconfig b/configs/sama5d4_xplained_nandflash_defconfig
index 5e13da7908f8be89adc947de2bb27f2a8efdfd3c..046fe0682e3a6fe885667305d987e88f9bac735c 100644 (file)
--- a/configs/sama5d4_xplained_nandflash_defconfig
+++ b/configs/sama5d4_xplained_nandflash_defconfig
@@ -1,3 +1,4 @@
+CONFIG_SPL=y
 CONFIG_SYS_EXTRA_OPTIONS="SAMA5D4,SYS_USE_NANDFLASH"
 +S:CONFIG_ARM=y
 +S:CONFIG_TARGET_SAMA5D4_XPLAINED=y

diff --git a/configs/sama5d4_xplained_spiflash_defconfig b/configs/sama5d4_xplained_spiflash_defconfig
index 3a4607c6768b00dfa7644187cde6e4379a967327..755dd8b55f85cc32fdd5184425d3430e6a7fe215 100644 (file)
--- a/configs/sama5d4_xplained_spiflash_defconfig
+++ b/configs/sama5d4_xplained_spiflash_defconfig
@@ -1,3 +1,4 @@
+CONFIG_SPL=y
 CONFIG_SYS_EXTRA_OPTIONS="SAMA5D4,SYS_USE_SERIALFLASH"
 +S:CONFIG_ARM=y
 +S:CONFIG_TARGET_SAMA5D4_XPLAINED=y

diff --git a/include/configs/sama5d4_xplained.h b/include/configs/sama5d4_xplained.h
index 996973d99b6cb236f848c7d12ad63f61069878f5..6493d567b4aad42232dfa684953d7f55884c8bb5 100644 (file)
--- a/include/configs/sama5d4_xplained.h
+++ b/include/configs/sama5d4_xplained.h
@@ -20,7 +20,9 @@
 
 #define CONFIG_ARCH_CPU_INIT
 
+#ifndef CONFIG_SPL_BUILD
 #define CONFIG_SKIP_LOWLEVEL_INIT
+#endif
 #define CONFIG_BOARD_EARLY_INIT_F
 #define CONFIG_DISPLAY_CPUINFO
 
@@ -66,8 +68,12 @@
 #define CONFIG_SYS_SDRAM_BASE           ATMEL_BASE_DDRCS
 #define CONFIG_SYS_SDRAM_SIZE          0x20000000
 
+#ifdef CONFIG_SPL_BUILD
+#define CONFIG_SYS_INIT_SP_ADDR                0x210000
+#else
 #define CONFIG_SYS_INIT_SP_ADDR \
        (CONFIG_SYS_SDRAM_BASE + 4 * 1024 - GENERATED_GBL_DATA_SIZE)
+#endif
 
 #define CONFIG_SYS_LOAD_ADDR           0x22000000 /* load address */
 
@@ -221,4 +227,54 @@
 /* Size of malloc() pool */
 #define CONFIG_SYS_MALLOC_LEN          (4 * 1024 * 1024)
 
+
+/* SPL */
+#define CONFIG_SPL_FRAMEWORK
+#define CONFIG_SPL_TEXT_BASE           0x200000
+#define CONFIG_SPL_MAX_SIZE            0x10000
+#define CONFIG_SPL_BSS_START_ADDR      0x20000000
+#define CONFIG_SPL_BSS_MAX_SIZE                0x80000
+#define CONFIG_SYS_SPL_MALLOC_START    0x20080000
+#define CONFIG_SYS_SPL_MALLOC_SIZE     0x80000
+
+#define CONFIG_SPL_LIBCOMMON_SUPPORT
+#define CONFIG_SPL_LIBGENERIC_SUPPORT
+#define CONFIG_SPL_GPIO_SUPPORT
+#define CONFIG_SPL_SERIAL_SUPPORT
+
+#define CONFIG_SPL_BOARD_INIT
+#define CONFIG_SYS_MONITOR_LEN         (512 << 10)
+
+#ifdef CONFIG_SYS_USE_MMC
+#define CONFIG_SPL_LDSCRIPT            arch/arm/cpu/at91-common/u-boot-spl.lds
+#define CONFIG_SPL_MMC_SUPPORT
+#define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS     0x400
+#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x200
+#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION     1
+#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME                "u-boot.img"
+#define CONFIG_SPL_FAT_SUPPORT
+#define CONFIG_SPL_LIBDISK_SUPPORT
+
+#elif CONFIG_SYS_USE_NANDFLASH
+#define CONFIG_SPL_NAND_SUPPORT
+#define CONFIG_SPL_NAND_DRIVERS
+#define CONFIG_SPL_NAND_BASE
+#define CONFIG_PMECC_CAP               8
+#define CONFIG_PMECC_SECTOR_SIZE       512
+#define CONFIG_SYS_NAND_U_BOOT_OFFS    0x40000
+#define CONFIG_SYS_NAND_5_ADDR_CYCLE
+#define CONFIG_SYS_NAND_PAGE_SIZE      0x1000
+#define CONFIG_SYS_NAND_PAGE_COUNT     64
+#define CONFIG_SYS_NAND_OOBSIZE                224
+#define CONFIG_SYS_NAND_BLOCK_SIZE     0x40000
+#define CONFIG_SYS_NAND_BAD_BLOCK_POS  0x0
+#define CONFIG_SPL_GENERATE_ATMEL_PMECC_HEADER
+
+#elif CONFIG_SYS_USE_SERIALFLASH
+#define CONFIG_SPL_SPI_SUPPORT
+#define CONFIG_SPL_SPI_FLASH_SUPPORT
+#define CONFIG_SPL_SPI_LOAD
+#define CONFIG_SYS_SPI_U_BOOT_OFFS     0x20000
+
+#endif
 #endif