Enhance MCAM to allow the driver to query which access regs are
supported. For now, expose the regs needed for FW flashing.
Signed-off-by: Or Gerlitz <ogerlitz@mellanox.com>
Reviewed-by: Gal Pressman <galp@mellanox.com>
Signed-off-by: Saeed Mahameed <saeedm@mellanox.com>
#define MLX5_CAP_PCAM_FEATURE(mdev, fld) \
MLX5_GET(pcam_reg, (mdev)->caps.pcam, feature_cap_mask.enhanced_features.fld)
+#define MLX5_CAP_MCAM_REG(mdev, reg) \
+ MLX5_GET(mcam_reg, (mdev)->caps.mcam, mng_access_reg_cap_mask.access_regs.reg)
+
#define MLX5_CAP_MCAM_FEATURE(mdev, fld) \
MLX5_GET(mcam_reg, (mdev)->caps.mcam, mng_feature_cap_mask.enhanced_features.fld)
u8 pcie_performance_group[0x1];
};
+struct mlx5_ifc_mcam_access_reg_bits {
+ u8 reserved_at_0[0x1c];
+ u8 mcda[0x1];
+ u8 mcc[0x1];
+ u8 mcqi[0x1];
+ u8 reserved_at_1f[0x1];
+
+ u8 regs_95_to_64[0x20];
+ u8 regs_63_to_32[0x20];
+ u8 regs_31_to_0[0x20];
+};
+
struct mlx5_ifc_mcam_reg_bits {
u8 reserved_at_0[0x8];
u8 feature_group[0x8];
u8 reserved_at_20[0x20];
union {
+ struct mlx5_ifc_mcam_access_reg_bits access_regs;
u8 reserved_at_0[0x80];
} mng_access_reg_cap_mask;