drm/nouveau/gr/gf100-: virtualise init_sked_hww_esr
authorBen Skeggs <bskeggs@redhat.com>
Tue, 8 May 2018 10:39:46 +0000 (20:39 +1000)
committerBen Skeggs <bskeggs@redhat.com>
Fri, 18 May 2018 05:01:23 +0000 (15:01 +1000)
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
12 files changed:
drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c
drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.h
drivers/gpu/drm/nouveau/nvkm/engine/gr/gk104.c
drivers/gpu/drm/nouveau/nvkm/engine/gr/gk110.c
drivers/gpu/drm/nouveau/nvkm/engine/gr/gk110b.c
drivers/gpu/drm/nouveau/nvkm/engine/gr/gk208.c
drivers/gpu/drm/nouveau/nvkm/engine/gr/gm107.c
drivers/gpu/drm/nouveau/nvkm/engine/gr/gm200.c
drivers/gpu/drm/nouveau/nvkm/engine/gr/gp100.c
drivers/gpu/drm/nouveau/nvkm/engine/gr/gp102.c
drivers/gpu/drm/nouveau/nvkm/engine/gr/gp107.c
drivers/gpu/drm/nouveau/nvkm/engine/gr/gp10b.c

index 1b067e600d74a4c955a4e4eb377fde1a63dd063a..7ccd8f21c1e0e52438f6f3489be22ba61adf77a9 100644 (file)
@@ -2036,6 +2036,10 @@ gf100_gr_init(struct gf100_gr *gr)
 
        nvkm_wr32(device, 0x404490, 0xc0000000);
        nvkm_wr32(device, 0x406018, 0xc0000000);
+
+       if (gr->func->init_sked_hww_esr)
+               gr->func->init_sked_hww_esr(gr);
+
        nvkm_wr32(device, 0x405840, 0xc0000000);
        nvkm_wr32(device, 0x405844, 0x00ffffff);
        nvkm_mask(device, 0x419cc0, 0x00000008, 0x00000008);
index 8c42a7aff1839f0a11fde03aec4656e25e978f7c..c292cf3bebb1c5e5fefc8caa8206f11844d32767 100644 (file)
@@ -133,6 +133,7 @@ struct gf100_gr_func {
        void (*init_fecs_exceptions)(struct gf100_gr *);
        void (*init_ds_hww_esr_2)(struct gf100_gr *);
        void (*init_40601c)(struct gf100_gr *);
+       void (*init_sked_hww_esr)(struct gf100_gr *);
        void (*init_ppc_exceptions)(struct gf100_gr *);
        void (*set_hww_esr_report_mask)(struct gf100_gr *);
        const struct gf100_gr_pack *mmio;
@@ -163,6 +164,7 @@ int gk104_gr_init(struct gf100_gr *);
 void gk104_gr_init_vsc_stream_master(struct gf100_gr *);
 void gk104_gr_init_rop_active_fbps(struct gf100_gr *);
 void gk104_gr_init_ppc_exceptions(struct gf100_gr *);
+void gk104_gr_init_sked_hww_esr(struct gf100_gr *);
 
 int gk20a_gr_init(struct gf100_gr *);
 
index 746ad3d0d1cee85db36c2d4467acc128884ca0b2..6ba604edaf952cc9590693cfbbaa8d4fba839adb 100644 (file)
@@ -380,6 +380,12 @@ gk104_clkgate_pack[] = {
  * PGRAPH engine/subdev functions
  ******************************************************************************/
 
+void
+gk104_gr_init_sked_hww_esr(struct gf100_gr *gr)
+{
+       nvkm_wr32(gr->base.engine.subdev.device, 0x407020, 0x40000000);
+}
+
 static void
 gk104_gr_init_fecs_exceptions(struct gf100_gr *gr)
 {
@@ -451,7 +457,7 @@ gk104_gr_init(struct gf100_gr *gr)
        nvkm_wr32(device, 0x408030, 0xc0000000);
        nvkm_wr32(device, 0x404490, 0xc0000000);
        nvkm_wr32(device, 0x406018, 0xc0000000);
-       nvkm_wr32(device, 0x407020, 0x40000000);
+       gr->func->init_sked_hww_esr(gr);
        nvkm_wr32(device, 0x405840, 0xc0000000);
        nvkm_wr32(device, 0x405844, 0x00ffffff);
        nvkm_mask(device, 0x419cc0, 0x00000008, 0x00000008);
@@ -527,6 +533,7 @@ gk104_gr = {
        .init_num_active_ltcs = gf100_gr_init_num_active_ltcs,
        .init_rop_active_fbps = gk104_gr_init_rop_active_fbps,
        .init_fecs_exceptions = gk104_gr_init_fecs_exceptions,
+       .init_sked_hww_esr = gk104_gr_init_sked_hww_esr,
        .init_ppc_exceptions = gk104_gr_init_ppc_exceptions,
        .mmio = gk104_gr_pack_mmio,
        .fecs.ucode = &gk104_gr_fecs_ucode,
index 8a6340d237662526330fee776b268e6f3ccd8652..7a07d24cc22792c17f9529e8f6364f2a66e3aef0 100644 (file)
@@ -343,6 +343,7 @@ gk110_gr = {
        .init_num_active_ltcs = gf100_gr_init_num_active_ltcs,
        .init_rop_active_fbps = gk104_gr_init_rop_active_fbps,
        .init_fecs_exceptions = gf100_gr_init_fecs_exceptions,
+       .init_sked_hww_esr = gk104_gr_init_sked_hww_esr,
        .init_ppc_exceptions = gk104_gr_init_ppc_exceptions,
        .mmio = gk110_gr_pack_mmio,
        .fecs.ucode = &gk110_gr_fecs_ucode,
index b50e68165df76e68b507b82d5e323ebd3f5d575d..1c9f59cde3d2c7fde47ef6ef19d7bc76d16d9728 100644 (file)
@@ -109,6 +109,7 @@ gk110b_gr = {
        .init_num_active_ltcs = gf100_gr_init_num_active_ltcs,
        .init_rop_active_fbps = gk104_gr_init_rop_active_fbps,
        .init_fecs_exceptions = gf100_gr_init_fecs_exceptions,
+       .init_sked_hww_esr = gk104_gr_init_sked_hww_esr,
        .init_ppc_exceptions = gk104_gr_init_ppc_exceptions,
        .mmio = gk110b_gr_pack_mmio,
        .fecs.ucode = &gk110_gr_fecs_ucode,
index 7a938bb3af9fab890ab7482d47dbd20968d3c7da..40c87242b54df5a88ff3521fc2b36dad60ab66ab 100644 (file)
@@ -168,6 +168,7 @@ gk208_gr = {
        .init_num_active_ltcs = gf100_gr_init_num_active_ltcs,
        .init_rop_active_fbps = gk104_gr_init_rop_active_fbps,
        .init_fecs_exceptions = gf100_gr_init_fecs_exceptions,
+       .init_sked_hww_esr = gk104_gr_init_sked_hww_esr,
        .init_ppc_exceptions = gk104_gr_init_ppc_exceptions,
        .mmio = gk208_gr_pack_mmio,
        .fecs.ucode = &gk208_gr_fecs_ucode,
index 9f2df29fd4e4b2da4ad9696a676edaca5cf1178e..3d180edbdcd76c43167ff02a16864c198864ba43 100644 (file)
@@ -378,7 +378,7 @@ gm107_gr_init(struct gf100_gr *gr)
        nvkm_wr32(device, 0x408030, 0xc0000000);
        nvkm_wr32(device, 0x404490, 0xc0000000);
        nvkm_wr32(device, 0x406018, 0xc0000000);
-       nvkm_wr32(device, 0x407020, 0x40000000);
+       gr->func->init_sked_hww_esr(gr);
        nvkm_wr32(device, 0x405840, 0xc0000000);
        nvkm_wr32(device, 0x405844, 0x00ffffff);
        nvkm_mask(device, 0x419cc0, 0x00000008, 0x00000008);
@@ -456,6 +456,7 @@ gm107_gr = {
        .init_rop_active_fbps = gk104_gr_init_rop_active_fbps,
        .init_bios_2 = gm107_gr_init_bios_2,
        .init_fecs_exceptions = gf100_gr_init_fecs_exceptions,
+       .init_sked_hww_esr = gk104_gr_init_sked_hww_esr,
        .init_ppc_exceptions = gk104_gr_init_ppc_exceptions,
        .mmio = gm107_gr_pack_mmio,
        .fecs.ucode = &gm107_gr_fecs_ucode,
index b5994dca5d03f597b96136237e079eee93041934..9436ab37aa9e57e2ac821092fe4c7d5bebc59e89 100644 (file)
@@ -106,7 +106,7 @@ gm200_gr_init(struct gf100_gr *gr)
        nvkm_wr32(device, 0x408030, 0xc0000000);
        nvkm_wr32(device, 0x404490, 0xc0000000);
        nvkm_wr32(device, 0x406018, 0xc0000000);
-       nvkm_wr32(device, 0x407020, 0x40000000);
+       gr->func->init_sked_hww_esr(gr);
        nvkm_wr32(device, 0x405840, 0xc0000000);
        nvkm_wr32(device, 0x405844, 0x00ffffff);
        nvkm_mask(device, 0x419cc0, 0x00000008, 0x00000008);
@@ -202,6 +202,7 @@ gm200_gr = {
        .init_rop_active_fbps = gm200_gr_init_rop_active_fbps,
        .init_fecs_exceptions = gf100_gr_init_fecs_exceptions,
        .init_ds_hww_esr_2 = gm200_gr_init_ds_hww_esr_2,
+       .init_sked_hww_esr = gk104_gr_init_sked_hww_esr,
        .init_ppc_exceptions = gk104_gr_init_ppc_exceptions,
        .rops = gm200_gr_rops,
        .ppc_nr = 2,
index 676f58a9aceeb2707a9cb27d25cb1d9d11151d98..72ea16ee842a74fd05ff60df3eb08cc3dd8efa52 100644 (file)
@@ -76,7 +76,7 @@ gp100_gr_init(struct gf100_gr *gr)
        nvkm_wr32(device, 0x408030, 0xc0000000);
        nvkm_wr32(device, 0x404490, 0xc0000000);
        nvkm_wr32(device, 0x406018, 0xc0000000);
-       nvkm_wr32(device, 0x407020, 0x40000000);
+       gr->func->init_sked_hww_esr(gr);
        nvkm_wr32(device, 0x405840, 0xc0000000);
        nvkm_wr32(device, 0x405844, 0x00ffffff);
        nvkm_mask(device, 0x419cc0, 0x00000008, 0x00000008);
@@ -134,6 +134,7 @@ gp100_gr = {
        .init_rop_active_fbps = gp100_gr_init_rop_active_fbps,
        .init_fecs_exceptions = gp100_gr_init_fecs_exceptions,
        .init_ds_hww_esr_2 = gm200_gr_init_ds_hww_esr_2,
+       .init_sked_hww_esr = gk104_gr_init_sked_hww_esr,
        .init_ppc_exceptions = gk104_gr_init_ppc_exceptions,
        .rops = gm200_gr_rops,
        .ppc_nr = 2,
index 3694687c85dbf80d5a42e57a25cedf97b4b481e9..309815bef601b02b245727eeb44b9b92f4b65117 100644 (file)
@@ -51,6 +51,7 @@ gp102_gr = {
        .init_swdx_pes_mask = gp102_gr_init_swdx_pes_mask,
        .init_fecs_exceptions = gp100_gr_init_fecs_exceptions,
        .init_ds_hww_esr_2 = gm200_gr_init_ds_hww_esr_2,
+       .init_sked_hww_esr = gk104_gr_init_sked_hww_esr,
        .init_ppc_exceptions = gk104_gr_init_ppc_exceptions,
        .rops = gm200_gr_rops,
        .ppc_nr = 3,
index c83ad01bad53bbb01ed68c0cb16c1a81ff5fee73..1ae9e7d991f935e678388962b04a4392e9fd4957 100644 (file)
@@ -37,6 +37,7 @@ gp107_gr = {
        .init_swdx_pes_mask = gp102_gr_init_swdx_pes_mask,
        .init_fecs_exceptions = gp100_gr_init_fecs_exceptions,
        .init_ds_hww_esr_2 = gm200_gr_init_ds_hww_esr_2,
+       .init_sked_hww_esr = gk104_gr_init_sked_hww_esr,
        .init_ppc_exceptions = gk104_gr_init_ppc_exceptions,
        .rops = gm200_gr_rops,
        .ppc_nr = 1,
index 8fef3b56cf8c2f5cd9b4b47465567d0140ac3810..68e212823063b22091666d7f42998f350c96a24a 100644 (file)
@@ -35,6 +35,7 @@ gp10b_gr = {
        .init_rop_active_fbps = gp100_gr_init_rop_active_fbps,
        .init_fecs_exceptions = gp100_gr_init_fecs_exceptions,
        .init_ds_hww_esr_2 = gm200_gr_init_ds_hww_esr_2,
+       .init_sked_hww_esr = gk104_gr_init_sked_hww_esr,
        .init_ppc_exceptions = gk104_gr_init_ppc_exceptions,
        .rops = gm200_gr_rops,
        .ppc_nr = 1,