ramips: mt7620: use DTS to set PHY base address for external PHYs
authorMichael Pratt <mcpratt@pm.me>
Sat, 3 Apr 2021 18:42:51 +0000 (14:42 -0400)
committerChuanhong Guo <gch981213@gmail.com>
Wed, 23 Jun 2021 06:22:18 +0000 (14:22 +0800)
Set the PHY base address to 12 for mt7530 and 8 for others,
which is based on the default setting for some devices
from printing the register with the following command
after it is written to by uboot during the boot cycle.

`md 0x10117014 1`

PHY_BASE option only uses 5 bits of the register,
bits 16 to 20, so use 8-bit integer type.

Set the option using the DTS property mediatek,ephy-base
and create the gsw node if missing.

Also, added a kernel message to display the EPHY base address.

Note:
If anything is written to a PHY address that is greater than 1 hex char (greater than 0xf)
then there is adverse effects with Atheros switches.

Signed-off-by: Michael Pratt <mcpratt@pm.me>
24 files changed:
target/linux/ramips/dts/mt7620a_dlink_dwr-118-a1.dts
target/linux/ramips/dts/mt7620a_dlink_dwr-118-a2.dts
target/linux/ramips/dts/mt7620a_dovado_tiny-ac.dts
target/linux/ramips/dts/mt7620a_edimax_br-6478ac-v2.dts
target/linux/ramips/dts/mt7620a_edimax_ew-7478apc.dts
target/linux/ramips/dts/mt7620a_edimax_ew-747x.dtsi
target/linux/ramips/dts/mt7620a_engenius_esr600.dts
target/linux/ramips/dts/mt7620a_fon_fon2601.dts
target/linux/ramips/dts/mt7620a_head-weblink_hdrm200.dts
target/linux/ramips/dts/mt7620a_iodata_wn-ac1167gr.dts
target/linux/ramips/dts/mt7620a_iptime_a1004ns.dts
target/linux/ramips/dts/mt7620a_lava_lr-25g001.dts
target/linux/ramips/dts/mt7620a_lb-link_bl-w1200.dts
target/linux/ramips/dts/mt7620a_lenovo_newifi-y1s.dts
target/linux/ramips/dts/mt7620a_linksys_e1700.dts
target/linux/ramips/dts/mt7620a_netis_wf2770.dts
target/linux/ramips/dts/mt7620a_ralink_mt7620a-evb.dts
target/linux/ramips/dts/mt7620a_ralink_mt7620a-mt7530-evb.dts
target/linux/ramips/dts/mt7620a_ralink_mt7620a-v22sg-evb.dts
target/linux/ramips/dts/mt7620a_sercomm_na930.dts
target/linux/ramips/dts/mt7620a_tplink_re210-v1.dts
target/linux/ramips/dts/mt7620a_wavlink_wl-wn579x3.dts
target/linux/ramips/dts/mt7620a_zyxel_keenetic-viva.dts
target/linux/ramips/files/drivers/net/ethernet/ralink/gsw_mt7620.c

index 71b532fc3456aa4804ecaabf7e60c6d69de2ebd1..b86ab1449b680a30b39215cbdfdb1dfce3dded29 100644 (file)
 
 &gsw {
        mediatek,port4-gmac;
+       mediatek,ephy-base = /bits/ 8 <8>;
 };
index 9ea28706aa1909ea8e534af74f99a6ee48e5e433..b0dd31cafcd8974bff7159325192b5dcf8e77fe5 100644 (file)
 
 &gsw {
        mediatek,port4-gmac;
-       mediatek,ephy-base-address = /bits/ 16 < 2 >;
+       mediatek,ephy-base = /bits/ 8 <2>;
 };
index 068f75bd96045e0a48584d47600562b18a21b7da..ba1a2becdab6b997e1ce83e023d0d505ff51182f 100644 (file)
 
 &gsw {
        mediatek,port4-gmac;
+       mediatek,ephy-base = /bits/ 8 <8>;
 };
 
 &pcie {
index 2337c0f9d360513d177af74ab212970dd900f45f..03a4c96f6baba26606fba96c2c904298aa732534 100644 (file)
        };
 };
 
+&gsw {
+       mediatek,ephy-base = /bits/ 8 <12>;
+};
+
 &wmac {
        ralink,mtd-eeprom = <&factory 0x0>;
 };
index 09763db388c13c2ac3f4b2dc3b7eeca8d6b73758..986b047e4775bae5637f1188d414d7616270e37a 100644 (file)
        };
 };
 
+&gsw {
+       mediatek,ephy-base = /bits/ 8 <12>;
+};
+
 &wmac {
        ralink,mtd-eeprom = <&factory 0x0>;
 };
index 07b03f5c066b2d8283b427db0e479f6492d335eb..5cb8451547a63a1cd42da84392f1243af9e7424f 100644 (file)
        };
 };
 
+&gsw {
+       mediatek,ephy-base = /bits/ 8 <8>;
+};
+
 &wmac {
        ralink,mtd-eeprom = <&factory 0x0>;
 };
index 35d0b3dbeca161de43e947a97fa4febb830515e8..2f0f9b256e953d86fb07117e431d3b4b1132fda7 100644 (file)
        };
 };
 
+&gsw {
+       mediatek,ephy-base = /bits/ 8 <8>;
+};
+
 &state_default {
        gpio {
                groups = "i2c", "uartf", "nd_sd", "wled";
index b47d63be85823be6463489d43e8244a3a6f5bfaa..373205e725483f907ce373e8d158ffb8ed68871c 100644 (file)
 
 &gsw {
        mediatek,port4-gmac;
+       mediatek,ephy-base = /bits/ 8 <8>;
 };
 
 &wmac {
index 487f6aaf6ebafb0e389ae6ad549a5498918b64c0..7d807bff4bbfeb082e7c69ba8be7ce1fb5cbaf3b 100644 (file)
 
 &gsw {
        mediatek,port4-gmac;
+       mediatek,ephy-base = /bits/ 8 <8>;
 };
 
 &wmac {
index 7044a511bcc97f32a0db83cbc7ab97e83df9cebd..d59b481a612787f8a315a74623cc4641a18c9c27 100644 (file)
        };
 };
 
+&gsw {
+       mediatek,ephy-base = /bits/ 8 <12>;
+};
+
 &state_default {
        gpio {
                groups = "i2c", "uartf";
index 20d055791634953490fa00ca53fef8db6a5572f5..6270af3b15895be3b4e440abcfde2b1a19fb74cc 100644 (file)
                };
        };
 };
+
+&gsw {
+       mediatek,ephy-base = /bits/ 8 <12>;
+};
index 962ef3371d6343a6f00c21c9e022a8006a242331..ee845c7b5ecda713bf37e4cc07b8ce3eae01c5e4 100644 (file)
        };
 };
 
+&gsw {
+       mediatek,ephy-base = /bits/ 8 <8>;
+};
+
 &pcie {
        status = "okay";
 };
index bb1303d4fb40a8d80322b727dc5992db96795711..9e0b817163350600e8da769b29d67a94bd3407ef 100644 (file)
        };
 };
 
+&gsw {
+       mediatek,ephy-base = /bits/ 8 <12>;
+};
+
 &wmac {
        ralink,mtd-eeprom = <&factory 0x0>;
 };
index 0997d8a00ec823389d32f25021b015617f93bcdc..0544550bf9d6e91cb065244352a856f56fde4a9e 100644 (file)
 
 &gsw {
        mediatek,port4-gmac;
+       mediatek,ephy-base = /bits/ 8 <8>;
 };
index 2672d54f360e4564061e3629929f2740d9c3338d..c38ea8082ca8f6b458b0723563bac1665d136488 100644 (file)
        };
 };
 
+&gsw {
+       mediatek,ephy-base = /bits/ 8 <12>;
+};
+
 &wmac {
        ralink,mtd-eeprom = <&factory 0x0>;
 };
index ab8c61b1d8260d65ad8f6f1ed09fbca67cc9f83e..f83904886566071448abc925f45c71a2ee034502 100644 (file)
        };
 };
 
+&gsw {
+       mediatek,ephy-base = /bits/ 8 <12>;
+};
+
 &pcie {
        status = "okay";
 };
index 4c5baf1e5080837cb8a7d71542210b73c0636d9b..ae3594150743fba5efd02766d57a31ac917d2d0f 100644 (file)
 
 &gsw {
        mediatek,port4-gmac;
+       mediatek,ephy-base = /bits/ 8 <8>;
 };
 
 &sdhci {
index b76ab2aa595a87014f454e76594cbcd1e42557b6..f7d8cae1602593438657343167c7520dbfef99ca 100644 (file)
        };
 };
 
+&gsw {
+       mediatek,ephy-base = /bits/ 8 <12>;
+};
+
 &pcie {
        status = "okay";
 };
index 6e8eff50bcf0b543df9f09bfec587f4bdaab7bb1..0e963e1f02aa239e3f519b7eb92f0c653a688874 100644 (file)
 
 &gsw {
        mediatek,port4-gmac;
+       mediatek,ephy-base = /bits/ 8 <8>;
 };
 
 &pcie {
index 329ecc5ea8a8b631be1aaf2853ac4100b67ef222..1ffc0a2bc815c03bb9ba0993218961093c3f70c2 100644 (file)
 
 &gsw {
        mediatek,port4-gmac;
+       mediatek,ephy-base = /bits/ 8 <8>;
 };
 
 &ehci {
index 247b5752ef1283010f1d39a59d9cd7be0240b7a9..57cd0ed539f8bc425f6f20e7f63030de30248bc4 100644 (file)
@@ -62,6 +62,7 @@
 
 &gsw {
        mediatek,port4-gmac;
+       mediatek,ephy-base = /bits/ 8 <8>;
 };
 
 &ethernet {
index 55ab939d157b2581388f6c6277a3eb633fa264bd..bfec806c125a1209ba1f1ef3639f9514541ee99b 100644 (file)
 
 &gsw {
        mediatek,port4-gmac;
+       mediatek,ephy-base = /bits/ 8 <8>;
 };
 
 &wmac {
index 506b828ec834c029238c37454a4c66c73a1444a8..1a5ff2d0dfc3e5125136e7d56f7fd97d6bf591a6 100644 (file)
 
 &gsw {
        mediatek,port4-gmac;
+       mediatek,ephy-base = /bits/ 8 <8>;
 };
 
 &wmac {
index 4b030f457bec52820bdde5b6cbe1bbf445025d69..54b8b204ebf87ec449750c3932267a540150bb15 100644 (file)
@@ -98,9 +98,6 @@ static void mt7620_hw_init(struct mt7620_gsw *gsw, int mdio_mode)
        mtk_switch_w32(gsw, mtk_switch_r32(gsw, GSW_REG_MIB_CNT_EN) | (1 << 1), GSW_REG_MIB_CNT_EN);
 
        if (mdio_mode) {
-               if (!gsw->ephy_base)
-                       gsw->ephy_base = 12;
-
                /* set MT7530 central align */
                val = mt7530_mdio_r32(gsw, 0x7830);
                val &= ~BIT(0);
@@ -115,11 +112,12 @@ static void mt7620_hw_init(struct mt7620_gsw *gsw, int mdio_mode)
        }
 
        if (gsw->ephy_base) {
-               /* set phy base addr to ephy_base */
                mtk_switch_w32(gsw, mtk_switch_r32(gsw, GSW_REG_GPC1) |
                        (gsw->ephy_base << 16),
                        GSW_REG_GPC1);
                fe_reset(BIT(24)); /* Resets the Ethernet PHY block. */
+
+               pr_info("gsw: ephy base address: %d\n", gsw->ephy_base);
        }
 
        /* global page 4 */
@@ -246,7 +244,7 @@ static int mt7620_gsw_probe(struct platform_device *pdev)
        struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
        struct mt7620_gsw *gsw;
        struct device_node *np = pdev->dev.of_node;
-       u16 val;
+       u8 val;
 
        gsw = devm_kzalloc(&pdev->dev, sizeof(struct mt7620_gsw), GFP_KERNEL);
        if (!gsw)
@@ -260,7 +258,7 @@ static int mt7620_gsw_probe(struct platform_device *pdev)
 
        gsw->port4_ephy = !of_property_read_bool(np, "mediatek,port4-gmac");
 
-       if (of_property_read_u16(np, "mediatek,ephy-base-address", &val) == 0)
+       if (of_property_read_u8(np, "mediatek,ephy-base", &val) == 0)
                gsw->ephy_base = val;
        else
                gsw->ephy_base = 0;