* byte addressing).
*/
if (pci_write_config_byte(pdev, LBCIF_CONTROL_REGISTER,
- LBCIF_CONTROL_LBCIF_ENABLE | LBCIF_CONTROL_I2C_WRITE))
+ LBCIF_CONTROL_LBCIF_ENABLE |
+ LBCIF_CONTROL_I2C_WRITE))
return -EIO;
/* Prepare EEPROM address for Step 3 */
-
for (retries = 0; retries < MAX_NUM_WRITE_RETRIES; retries++) {
/* Write the address to the LBCIF Address Register */
if (pci_write_config_dword(pdev, LBCIF_ADDRESS_REGISTER, addr))
while (1) {
if (pci_write_config_byte(pdev, LBCIF_CONTROL_REGISTER,
- LBCIF_CONTROL_LBCIF_ENABLE))
+ LBCIF_CONTROL_LBCIF_ENABLE))
writeok = 0;
/* Do read until internal ACK_ERROR goes away meaning write
addr);
do {
pci_read_config_dword(pdev,
- LBCIF_DATA_REGISTER, &val);
+ LBCIF_DATA_REGISTER,
+ &val);
} while ((val & 0x00010000) == 0);
} while (val & 0x00040000);
*/
if (pci_read_config_byte(pdev, ET1310_PCI_EEPROM_STATUS, &eestatus)) {
dev_err(&pdev->dev,
- "Could not read PCI config space for EEPROM Status\n");
+ "Could not read PCI config space for EEPROM Status\n");
return -EIO;
}
}
if (pdev->revision != 0x01 || write_failed) {
dev_err(&pdev->dev,
- "Fatal EEPROM Status Error - 0x%04x\n", eestatus);
+ "Fatal EEPROM Status Error - 0x%04x\n",
+ eestatus);
/* This error could mean that there was an error
* reading the eeprom or that the eeprom doesn't exist.
csr = readl(&adapter->regs->rxdma.csr);
if (csr & ET_RXDMA_CSR_HALT_STATUS) {
dev_err(&adapter->pdev->dev,
- "RX Dma failed to exit halt state. CSR 0x%08x\n",
+ "RX Dma failed to exit halt state. CSR 0x%08x\n",
csr);
}
}
csr = readl(&adapter->regs->rxdma.csr);
if (!(csr & ET_RXDMA_CSR_HALT_STATUS))
dev_err(&adapter->pdev->dev,
- "RX Dma failed to enter halt state. CSR 0x%08x\n",
- csr);
+ "RX Dma failed to enter halt state. CSR 0x%08x\n",
+ csr);
}
}
/* Setup the transmit dma configuration register for normal
* operation
*/
- writel(ET_TXDMA_SNGL_EPKT|(PARM_DMA_CACHE_DEF << ET_TXDMA_CACHE_SHIFT),
- &adapter->regs->txdma.csr);
+ writel(ET_TXDMA_SNGL_EPKT | (PARM_DMA_CACHE_DEF << ET_TXDMA_CACHE_SHIFT),
+ &adapter->regs->txdma.csr);
}
static inline void add_10bit(u32 *v, int n)
/* Initialize loop back to off */
cfg1 &= ~(ET_MAC_CFG1_LOOPBACK | ET_MAC_CFG1_RX_FLOW);
if (adapter->flowcontrol == FLOW_RXONLY ||
- adapter->flowcontrol == FLOW_BOTH)
+ adapter->flowcontrol == FLOW_BOTH)
cfg1 |= ET_MAC_CFG1_RX_FLOW;
writel(cfg1, &mac->cfg1);
if (delay == 100) {
dev_warn(&adapter->pdev->dev,
- "Syncd bits did not respond correctly cfg1 word 0x%08x\n",
- cfg1);
+ "Syncd bits did not respond correctly cfg1 word 0x%08x\n",
+ cfg1);
}
/* Enable txmac */
* @value: pointer to a 16-bit value in which the value will be stored
*/
static int et131x_phy_mii_read(struct et131x_adapter *adapter, u8 addr,
- u8 reg, u16 *value)
+ u8 reg, u16 *value)
{
struct mac_regs __iomem *mac = &adapter->regs->mac;
int status = 0;
/* If we hit the max delay, we could not read the register */
if (delay == 50) {
dev_warn(&adapter->pdev->dev,
- "reg 0x%08x could not be read\n", reg);
+ "reg 0x%08x could not be read\n", reg);
dev_warn(&adapter->pdev->dev, "status is 0x%08x\n",
- mii_indicator);
+ mii_indicator);
status = -EIO;
goto out;
u16 tmp;
dev_warn(&adapter->pdev->dev,
- "reg 0x%08x could not be written", reg);
+ "reg 0x%08x could not be written", reg);
dev_warn(&adapter->pdev->dev, "status is 0x%08x\n",
- mii_indicator);
+ mii_indicator);
dev_warn(&adapter->pdev->dev, "command is 0x%08x\n",
- readl(&mac->mii_mgmt_cmd));
+ readl(&mac->mii_mgmt_cmd));
et131x_mii_read(adapter, reg, &tmp);
{
/* Setup the transmit dma configuration register */
writel(ET_TXDMA_CSR_HALT | ET_TXDMA_SNGL_EPKT,
- &adapter->regs->txdma.csr);
+ &adapter->regs->txdma.csr);
}
/* et131x_enable_txrx - Enable tx/rx queues */
GFP_KERNEL);
if (!fbr->ring_virtaddr) {
dev_err(&adapter->pdev->dev,
- "Cannot alloc memory for Free Buffer Ring %d\n", id);
+ "Cannot alloc memory for Free Buffer Ring %d\n",
+ id);
return -ENOMEM;
}
}
if (!rx_ring->ps_ring_virtaddr) {
dev_err(&adapter->pdev->dev,
- "Cannot alloc memory for Packet Status Ring\n");
+ "Cannot alloc memory for Packet Status Ring\n");
return -ENOMEM;
}
GFP_KERNEL);
if (!rx_ring->rx_status_block) {
dev_err(&adapter->pdev->dev,
- "Cannot alloc memory for Status Block\n");
+ "Cannot alloc memory for Status Block\n");
return -ENOMEM;
}
rx_ring->num_rfd = NIC_DEFAULT_NUM_RFD;
rx_ring->psr_num_entries;
dma_free_coherent(&adapter->pdev->dev, pktstat_ringsize,
- rx_ring->ps_ring_virtaddr,
- rx_ring->ps_ring_physaddr);
+ rx_ring->ps_ring_virtaddr,
+ rx_ring->ps_ring_physaddr);
rx_ring->ps_ring_virtaddr = NULL;
}
/* Free area of memory for the writeback of status information */
if (rx_ring->rx_status_block) {
dma_free_coherent(&adapter->pdev->dev,
- sizeof(struct rx_status_block),
- rx_ring->rx_status_block, rx_ring->rx_status_bus);
+ sizeof(struct rx_status_block),
+ rx_ring->rx_status_block,
+ rx_ring->rx_status_bus);
rx_ring->rx_status_block = NULL;
}
writel(free_buff_ring, offset);
} else {
dev_err(&adapter->pdev->dev,
- "%s illegal Buffer Index returned\n", __func__);
+ "%s illegal Buffer Index returned\n", __func__);
}
/* The processing on this RFD is done, so put it back on the tail of
} else {
desc[frag].len_vlan = skb_headlen(skb) / 2;
dma_addr = dma_map_single(&adapter->pdev->dev,
- skb->data,
- (skb_headlen(skb) / 2),
- DMA_TO_DEVICE);
+ skb->data,
+ (skb_headlen(skb) / 2),
+ DMA_TO_DEVICE);
desc[frag].addr_lo = lower_32_bits(dma_addr);
desc[frag].addr_hi = upper_32_bits(dma_addr);
frag++;
desc[frag].len_vlan = skb_headlen(skb) / 2;
dma_addr = dma_map_single(&adapter->pdev->dev,
- skb->data +
- (skb_headlen(skb) / 2),
- (skb_headlen(skb) / 2),
- DMA_TO_DEVICE);
+ skb->data +
+ (skb_headlen(skb) / 2),
+ (skb_headlen(skb) / 2),
+ DMA_TO_DEVICE);
desc[frag].addr_lo = lower_32_bits(dma_addr);
desc[frag].addr_hi = upper_32_bits(dma_addr);
frag++;
add_10bit(&tx_ring->send_idx, thiscopy);
if (INDEX10(tx_ring->send_idx) == 0 ||
- INDEX10(tx_ring->send_idx) == NUM_DESC_PER_RING_TX) {
+ INDEX10(tx_ring->send_idx) == NUM_DESC_PER_RING_TX) {
tx_ring->send_idx &= ~ET_DMA10_MASK;
tx_ring->send_idx ^= ET_DMA10_WRAP;
}
* netif layer think we're good and drop the packet
*/
if ((adapter->flags & FMP_ADAPTER_FAIL_SEND_MASK) ||
- !netif_carrier_ok(netdev)) {
+ !netif_carrier_ok(netdev)) {
dev_kfree_skb_any(skb);
skb = NULL;
* Assumption - Send spinlock has been acquired
*/
static inline void free_send_packet(struct et131x_adapter *adapter,
- struct tcb *tcb)
+ struct tcb *tcb)
{
unsigned long flags;
struct tx_desc *desc = NULL;
* address into the permanent address
*/
memcpy(adapter->rom_addr,
- adapter->addr, ETH_ALEN);
+ adapter->addr, ETH_ALEN);
} else {
/* We do not have an override address, so set the
* current address to the permanent address and add
static const u16 replay[2] = { 0x1E0, 0x2ED };
if (pci_write_config_word(pdev, ET1310_PCI_ACK_NACK,
- acknak[max_payload])) {
+ acknak[max_payload])) {
dev_err(&pdev->dev,
- "Could not write PCI config space for ACK/NAK\n");
+ "Could not write PCI config space for ACK/NAK\n");
goto err_out;
}
if (pci_write_config_word(pdev, ET1310_PCI_REPLAY,
- replay[max_payload])) {
+ replay[max_payload])) {
dev_err(&pdev->dev,
- "Could not write PCI config space for Replay Timer\n");
+ "Could not write PCI config space for Replay Timer\n");
goto err_out;
}
}
*/
if (pci_write_config_byte(pdev, ET1310_PCI_L0L1LATENCY, 0x11)) {
dev_err(&pdev->dev,
- "Could not write PCI config space for Latency Timers\n");
+ "Could not write PCI config space for Latency Timers\n");
goto err_out;
}
for (i = 0; i < ETH_ALEN; i++) {
if (pci_read_config_byte(pdev, ET1310_PCI_MAC_ADDRESS + i,
- adapter->rom_addr + i)) {
+ adapter->rom_addr + i)) {
dev_err(&pdev->dev, "Could not read PCI config space for MAC address\n");
goto err_out;
}
status = et131x_tx_dma_memory_alloc(adapter);
if (status) {
dev_err(&adapter->pdev->dev,
- "et131x_tx_dma_memory_alloc FAILED\n");
+ "et131x_tx_dma_memory_alloc FAILED\n");
et131x_tx_dma_memory_free(adapter);
return status;
}
status = et131x_rx_dma_memory_alloc(adapter);
if (status) {
dev_err(&adapter->pdev->dev,
- "et131x_rx_dma_memory_alloc FAILED\n");
+ "et131x_rx_dma_memory_alloc FAILED\n");
et131x_adapter_memory_free(adapter);
return status;
}
u16 register18;
et131x_mii_read(adapter, PHY_MPHY_CONTROL_REG,
- ®ister18);
+ ®ister18);
et131x_mii_write(adapter, phydev->addr,
PHY_MPHY_CONTROL_REG, register18 | 0x4);
et131x_mii_write(adapter, phydev->addr, PHY_INDEX_REG,
u16 register18;
et131x_mii_read(adapter, PHY_MPHY_CONTROL_REG,
- ®ister18);
+ ®ister18);
et131x_mii_write(adapter, phydev->addr,
- PHY_MPHY_CONTROL_REG, register18 | 0x4);
+ PHY_MPHY_CONTROL_REG, register18 | 0x4);
et131x_mii_write(adapter, phydev->addr,
- PHY_INDEX_REG, register18 | 0x8402);
+ PHY_INDEX_REG, register18 | 0x8402);
et131x_mii_write(adapter, phydev->addr,
- PHY_DATA_REG, register18 | 511);
+ PHY_DATA_REG, register18 | 511);
et131x_mii_write(adapter, phydev->addr,
- PHY_MPHY_CONTROL_REG, register18);
+ PHY_MPHY_CONTROL_REG, register18);
}
/* Free the packets being actively sent & stopped */
u32 txdma_err = readl(&iomem->txdma.tx_dma_error);
dev_warn(&adapter->pdev->dev,
- "TXDMA_ERR interrupt, error = %d\n",
- txdma_err);
+ "TXDMA_ERR interrupt, error = %d\n",
+ txdma_err);
}
/* Handle Free Buffer Ring 0 and 1 Low interrupt */
/* TRAP();*/
dev_warn(&adapter->pdev->dev,
- "RxDMA_ERR interrupt, error %x\n",
- readl(&iomem->txmac.tx_test));
+ "RxDMA_ERR interrupt, error %x\n",
+ readl(&iomem->txmac.tx_test));
}
/* Handle the Wake on LAN Event */
flags);
dev_warn(&adapter->pdev->dev,
- "Send stuck - reset. tcb->WrIndex %x, flags 0x%08x\n",
- tcb->index,
- tcb->flags);
+ "Send stuck - reset. tcb->WrIndex %x, flags 0x%08x\n",
+ tcb->index,
+ tcb->flags);
adapter->netdev->stats.tx_errors++;
result = et131x_adapter_memory_alloc(adapter);
if (result != 0) {
dev_warn(&adapter->pdev->dev,
- "Change MTU failed; couldn't re-alloc DMA memory\n");
+ "Change MTU failed; couldn't re-alloc DMA memory\n");
return result;
}
adapter->mii_bus->name = "et131x_eth_mii";
snprintf(adapter->mii_bus->id, MII_BUS_ID_SIZE, "%x",
- (adapter->pdev->bus->number << 8) | adapter->pdev->devfn);
+ (adapter->pdev->bus->number << 8) | adapter->pdev->devfn);
adapter->mii_bus->priv = netdev;
adapter->mii_bus->read = et131x_mdio_read;
adapter->mii_bus->write = et131x_mdio_write;
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