cntl |= CNTL_LCDPWR;
writel(cntl, priv->regs + priv->ctrl);
- drm_crtc_vblank_on(crtc);
+ if (!priv->variant->broken_vblank)
+ drm_crtc_vblank_on(crtc);
}
void pl111_display_disable(struct drm_simple_display_pipe *pipe)
struct pl111_drm_dev_private *priv = drm->dev_private;
u32 cntl;
- drm_crtc_vblank_off(crtc);
+ if (!priv->variant->broken_vblank)
+ drm_crtc_vblank_off(crtc);
/* Power Down */
cntl = readl(priv->regs + priv->ctrl);
* BGR/RGB routing
* @broken_clockdivider: the clock divider is broken and we need to
* use the supplied clock directly
+ * @broken_vblank: the vblank IRQ is broken on this variant
* @formats: array of supported pixel formats on this variant
* @nformats: the length of the array of supported pixel formats
*/
bool is_pl110;
bool external_bgr;
bool broken_clockdivider;
+ bool broken_vblank;
const u32 *formats;
unsigned int nformats;
};
if (ret)
return ret;
- ret = drm_vblank_init(dev, 1);
- if (ret != 0) {
- dev_err(dev->dev, "Failed to init vblank\n");
- goto out_bridge;
+ if (!priv->variant->broken_vblank) {
+ ret = drm_vblank_init(dev, 1);
+ if (ret != 0) {
+ dev_err(dev->dev, "Failed to init vblank\n");
+ goto out_bridge;
+ }
}
drm_mode_config_reset(dev);
.dumb_create = drm_gem_cma_dumb_create,
.gem_free_object_unlocked = drm_gem_cma_free_object,
.gem_vm_ops = &drm_gem_cma_vm_ops,
-
- .enable_vblank = pl111_enable_vblank,
- .disable_vblank = pl111_disable_vblank,
-
.prime_handle_to_fd = drm_gem_prime_handle_to_fd,
.prime_fd_to_handle = drm_gem_prime_fd_to_handle,
.gem_prime_import = drm_gem_prime_import,
if (!priv)
return -ENOMEM;
+ if (!variant->broken_vblank) {
+ pl111_drm_driver.enable_vblank = pl111_enable_vblank;
+ pl111_drm_driver.disable_vblank = pl111_disable_vblank;
+ }
+
drm = drm_dev_alloc(&pl111_drm_driver, dev);
if (IS_ERR(drm))
return PTR_ERR(drm);
.name = "PL110 Integrator",
.is_pl110 = true,
.broken_clockdivider = true,
+ .broken_vblank = true,
.formats = pl110_integrator_pixel_formats,
.nformats = ARRAY_SIZE(pl110_integrator_pixel_formats),
};