arm64: tegra: Add INA3221 channel info for Jetson TX2
authorNicolin Chen <nicoleotsuka@gmail.com>
Mon, 17 Jun 2019 22:16:59 +0000 (15:16 -0700)
committerThierry Reding <treding@nvidia.com>
Thu, 20 Jun 2019 09:17:02 +0000 (11:17 +0200)
There are four INA3221 chips on the Jetson TX2 (p3310 + p2771).
And each INA3221 chip has three input channels to monitor power.

So this patch adds these 12 channels to the DT of Jetson TX2, by
following the DT binding of INA3221 and official documents from
https://developer.nvidia.com/embedded/downloads

tegra186-p3310:
https://developer.nvidia.com/embedded/dlc/jetson-tx2-series-modules-oem-product-design-guide

tegra186-p2771-0000:
http://developer.nvidia.com/embedded/dlc/jetson-tx1-tx2-developer-kit-carrier-board-spec-20180618

Signed-off-by: Nicolin Chen <nicoleotsuka@gmail.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
arch/arm64/boot/dts/nvidia/tegra186-p2771-0000.dts
arch/arm64/boot/dts/nvidia/tegra186-p3310.dtsi

index ab6648c72ad5ff87ffd12a9e59d0c106f475f280..9df4782c90f353935e12c38b5ee3820a86c75616 100644 (file)
                power-monitor@42 {
                        compatible = "ti,ina3221";
                        reg = <0x42>;
+                       #address-cells = <1>;
+                       #size-cells = <0>;
+
+                       channel@0 {
+                               reg = <0x0>;
+                               label = "VDD_MUX";
+                               shunt-resistor-micro-ohms = <20000>;
+                       };
+
+                       channel@1 {
+                               reg = <0x1>;
+                               label = "VDD_5V0_IO_SYS";
+                               shunt-resistor-micro-ohms = <5000>;
+                       };
+
+                       channel@2 {
+                               reg = <0x2>;
+                               label = "VDD_3V3_SYS";
+                               shunt-resistor-micro-ohms = <10000>;
+                       };
                };
 
                power-monitor@43 {
                        compatible = "ti,ina3221";
                        reg = <0x43>;
+                       #address-cells = <1>;
+                       #size-cells = <0>;
+
+                       channel@0 {
+                               reg = <0x0>;
+                               label = "VDD_3V3_IO_SLP";
+                               shunt-resistor-micro-ohms = <10000>;
+                       };
+
+                       channel@1 {
+                               reg = <0x1>;
+                               label = "VDD_1V8_IO";
+                               shunt-resistor-micro-ohms = <10000>;
+                       };
+
+                       channel@2 {
+                               reg = <0x2>;
+                               label = "VDD_M2_IN";
+                               shunt-resistor-micro-ohms = <10000>;
+                       };
                };
 
                exp1: gpio@74 {
index 4bbee83d9943fe27d69e283004b0c18f7905f1c3..5e18acf5cfad872bd5323f4c452bb3b4acdfc55a 100644 (file)
                power-monitor@40 {
                        compatible = "ti,ina3221";
                        reg = <0x40>;
+                       #address-cells = <1>;
+                       #size-cells = <0>;
+
+                       channel@0 {
+                               reg = <0x0>;
+                               label = "VDD_SYS_GPU";
+                               shunt-resistor-micro-ohms = <10000>;
+                       };
+
+                       channel@1 {
+                               reg = <0x1>;
+                               label = "VDD_SYS_SOC";
+                               shunt-resistor-micro-ohms = <10000>;
+                       };
+
+                       channel@2 {
+                               reg = <0x2>;
+                               label = "VDD_3V8_WIFI";
+                               shunt-resistor-micro-ohms = <10000>;
+                       };
                };
 
                power-monitor@41 {
                        compatible = "ti,ina3221";
                        reg = <0x41>;
+                       #address-cells = <1>;
+                       #size-cells = <0>;
+
+                       channel@0 {
+                               reg = <0x0>;
+                               label = "VDD_IN";
+                               shunt-resistor-micro-ohms = <5000>;
+                       };
+
+                       channel@1 {
+                               reg = <0x1>;
+                               label = "VDD_SYS_CPU";
+                               shunt-resistor-micro-ohms = <10000>;
+                       };
+
+                       channel@2 {
+                               reg = <0x2>;
+                               label = "VDD_5V0_DDR";
+                               shunt-resistor-micro-ohms = <10000>;
+                       };
                };
        };