Merge pull request #854 from rockchip-linux/pm_plat

rockchip: plat_pm.c: Change callbacks implement for our SOCs.

diff --cc plat/rockchip/common/include/plat_private.h
index 9638aae3feae05be1dbb5efb63487f2348988b8f,ce39d8fccc559bc1fc3a05b50f7a96ab5f511e54..7aa0d85dd7782d8c7d6af1643ac5d32d87ca92b5
--- 1/plat/rockchip/common/include/plat_private.h
--- 2/plat/rockchip/common/include/plat_private.h
+++ b/plat/rockchip/common/include/plat_private.h
@@@ -44,29 -44,7 +44,8 @@@
  
  extern uint32_t __bl31_sram_text_start, __bl31_sram_text_end;
  extern uint32_t __bl31_sram_data_start, __bl31_sram_data_end;
 +extern uint32_t __sram_incbin_start, __sram_incbin_end;
  
- /******************************************************************************
-  * For rockchip socs pm ops
-  ******************************************************************************/
- struct rockchip_pm_ops_cb {
-       int (*cores_pwr_dm_on)(unsigned long mpidr, uint64_t entrypoint);
-       int (*cores_pwr_dm_off)(void);
-       int (*cores_pwr_dm_on_finish)(void);
-       int (*cores_pwr_dm_suspend)(void);
-       int (*cores_pwr_dm_resume)(void);
-       /* hlvl is used for clusters or system level */
-       int (*hlvl_pwr_dm_suspend)(uint32_t lvl, plat_local_state_t lvl_state);
-       int (*hlvl_pwr_dm_resume)(uint32_t lvl, plat_local_state_t lvl_state);
-       int (*hlvl_pwr_dm_off)(uint32_t lvl, plat_local_state_t lvl_state);
-       int (*hlvl_pwr_dm_on_finish)(uint32_t lvl,
-                                    plat_local_state_t lvl_state);
-       int (*sys_pwr_dm_suspend)(void);
-       int (*sys_pwr_dm_resume)(void);
-       void (*sys_gbl_soft_reset)(void) __dead2;
-       void (*system_off)(void) __dead2;
-       void (*sys_pwr_down_wfi)(const psci_power_state_t *state_info) __dead2;
- };
  
  /******************************************************************************
   * The register have write-mask bits, it is mean, if you want to set the bits,

diff --cc plat/rockchip/rk3399/drivers/pmu/pmu.c
index e04d47445faf9e6a8f76cdf8c6abf90bd1ba0db3,5bb29b3b764b8b426373d6821f201b2b6ba4756c..31b4f07e30423403f684607261b4d119cd0ff604
--- 1/plat/rockchip/rk3399/drivers/pmu/pmu.c
--- 2/plat/rockchip/rk3399/drivers/pmu/pmu.c
+++ b/plat/rockchip/rk3399/drivers/pmu/pmu.c
@@@ -1067,13 -1066,39 +1068,13 @@@ static void resume_gpio(void
        }
  }
  
 -static void m0_clock_init(void)
 +static void m0_configure_suspend(void)
  {
 -      /* enable clocks for M0 */
 -      mmio_write_32(PMUCRU_BASE + PMUCRU_CLKGATE_CON2,
 -                    BITS_WITH_WMASK(0x0, 0x2f, 0));
 -
 -      /* switch the parent to xin24M and div == 1 */
 -      mmio_write_32(PMUCRU_BASE + PMUCRU_CLKSEL_CON0,
 -                    BIT_WITH_WMSK(15) | BITS_WITH_WMASK(0x0, 0x1f, 8));
 -
 -      /* start M0 */
 -      mmio_write_32(PMUCRU_BASE + PMUCRU_SOFTRST_CON0,
 -                    BITS_WITH_WMASK(0x0, 0x24, 0));
 -
 -      /* gating disable for M0 */
 -      mmio_write_32(PMUCRU_BASE + PMUCRU_GATEDIS_CON0, BIT_WITH_WMSK(1));
 -}
 -
 -static void m0_reset(void)
 -{
 -      /* stop M0 */
 -      mmio_write_32(PMUCRU_BASE + PMUCRU_SOFTRST_CON0,
 -                    BITS_WITH_WMASK(0x24, 0x24, 0));
 -
 -      /* recover gating bit for M0 */
 -      mmio_write_32(PMUCRU_BASE + PMUCRU_GATEDIS_CON0, WMSK_BIT(1));
 -
 -      /* disable clocks for M0 */
 -      mmio_write_32(PMUCRU_BASE + PMUCRU_CLKGATE_CON2,
 -                    BITS_WITH_WMASK(0x2f, 0x2f, 0));
 +      /* set PARAM to M0_FUNC_SUSPEND */
 +      mmio_write_32(M0_PARAM_ADDR + PARAM_M0_FUNC, M0_FUNC_SUSPEND);
  }
  
- static int sys_pwr_domain_suspend(void)
+ int rockchip_soc_sys_pwr_dm_suspend(void)
  {
        uint32_t wait_cnt = 0;
        uint32_t status = 0;