drm/amd/display: Fix hw state logging regression

Signed-off-by: Corbin McElhanney <corbin.mcelhanney@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Harry Wentland <Harry.Wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
index 292dfef91c9d4768b4f6daf8fb059dcc7625d75e..2fd9c33dbf1cef85e6923fb1940218327cb7f1b2 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
@@ -134,6 +134,7 @@ static void verify_allow_pstate_change_high(
        static unsigned int pstate_wait_timeout_us = 40;
        static unsigned int max_sampled_pstate_wait_us; /* data collection */
        static bool forced_pstate_allow; /* help with revert wa */
+       static bool should_log_hw_state; /* prevent hw state log by default */
 
        unsigned int debug_index = 0x7;
        unsigned int debug_data;
@@ -191,7 +192,9 @@ static void verify_allow_pstate_change_high(
        REG_WRITE(DCHUBBUB_ARB_DRAM_STATE_CNTL, force_allow_pstate);
        forced_pstate_allow = true;
 
-       dcn10_log_hw_state(DC_TO_CORE(hws->ctx->dc));
+       if (should_log_hw_state) {
+               dcn10_log_hw_state(DC_TO_CORE(hws->ctx->dc));
+       }
 
        BREAK_TO_DEBUGGER();
 }