gpio-stp-xway: Fix enabling the highest bit of the PHY LEDs

0x3 only masks two bits, but three bits have to be allowed. This fixes
GPHY0 LED2 (which is the highest bit of phy2) on my board.

Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Acked-by: John Crispin <blogic@openwrt.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>

diff --git a/drivers/gpio/gpio-stp-xway.c b/drivers/gpio/gpio-stp-xway.c
index 202361eb72797a92e92f4c02b395c70af0908a3f..6d4148f53b51a1567a08139713a264c066ad01c3 100644 (file)
--- a/drivers/gpio/gpio-stp-xway.c
+++ b/drivers/gpio/gpio-stp-xway.c
@@ -58,7 +58,7 @@
 #define XWAY_STP_ADSL_MASK     0x3
 
 /* 2 groups of 3 bits can be driven by the phys */
-#define XWAY_STP_PHY_MASK      0x3
+#define XWAY_STP_PHY_MASK      0x7
 #define XWAY_STP_PHY1_SHIFT    27
 #define XWAY_STP_PHY2_SHIFT    15