ath79: fix eth0 PLL registers on WD My Net Wi-Fi Range Extender

This replaces the register bits for RGMII delay on the MAC side in favor
of having the RGMII delay on the PHY side by setting the phy-mode
property to rgmii-id (RGMII internal delay), which is supported by the
at803x driver.  Speed 1000 is fixed as a result, so now all ethernet
speeds function.

Signed-off-by: Jonathan A. Kollasch <jakllsch@kollasch.net>
Reviewed-by: Michael Pratt <mcpratt@pm.me>
(cherry picked from commit f36990eae77c3a22842a2c418378c5dd40dec366)

diff --git a/target/linux/ath79/dts/ar9344_wd_mynet-wifi-rangeextender.dts b/target/linux/ath79/dts/ar9344_wd_mynet-wifi-rangeextender.dts
index 575c72ee7cd3741ca98a6a8b6371939d9ede3fb6..7313e9acc2843ea715631c1fea53b21027e5600d 100644 (file)
--- a/target/linux/ath79/dts/ar9344_wd_mynet-wifi-rangeextender.dts
+++ b/target/linux/ath79/dts/ar9344_wd_mynet-wifi-rangeextender.dts
@@ -144,10 +144,10 @@
 &eth0 {
        status = "okay";
 
-       pll-data = <0x0e000000 0x3c000101 0x3c001313>;
+       pll-data = <0x02000000 0x00000101 0x00001313>;
 
        /* ethernet MAC is stored in nvram */
-       phy-mode = "rgmii";
+       phy-mode = "rgmii-id";
        phy-handle = <&phy4>;
 
        gmac-config {