ARM: clk-imx6sl: Select appropriate parents for LCDIF clocks

PLL5 is well suited for being the parent of IMX6SL_CLK_LCDIF_PIX_SEL and
PLL2_PFD for IMX6SL_CLK_LCDIF_AXI_SEL.

Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Signed-off-by: Shawn Guo <shawn.guo@freescale.com>

diff --git a/arch/arm/mach-imx/clk-imx6sl.c b/arch/arm/mach-imx/clk-imx6sl.c
index ba3af22c1266b8d30b720c5bf3c2bf7b5abcaf2b..11908e8bf9ab6a44fb1fe6a1bda1799d8a4106c7 100644 (file)
--- a/arch/arm/mach-imx/clk-imx6sl.c
+++ b/arch/arm/mach-imx/clk-imx6sl.c
@@ -376,6 +376,13 @@ static void __init imx6sl_clocks_init(struct device_node *ccm_node)
        /* Audio-related clocks configuration */
        clk_set_parent(clks[IMX6SL_CLK_SPDIF0_SEL], clks[IMX6SL_CLK_PLL3_PFD3]);
 
+       /* set PLL5 video as lcdif pix parent clock */
+       clk_set_parent(clks[IMX6SL_CLK_LCDIF_PIX_SEL],
+                       clks[IMX6SL_CLK_PLL5_VIDEO_DIV]);
+
+       clk_set_parent(clks[IMX6SL_CLK_LCDIF_AXI_SEL],
+                      clks[IMX6SL_CLK_PLL2_PFD2]);
+
        /* Set initial power mode */
        imx6q_set_lpm(WAIT_CLOCKED);
 }