# Makefile for Display Core (dc) component.
#
-DC_LIBS = basics bios calcs dce gpio i2caux irq virtual
+DC_LIBS = basics bios calcs dce gpio irq virtual
ifdef CONFIG_DRM_AMD_DC_DCN1_0
DC_LIBS += dcn10 dml
if (dc->ctx->gpio_service)
dal_gpio_service_destroy(&dc->ctx->gpio_service);
- if (dc->ctx->i2caux)
- dal_i2caux_destroy(&dc->ctx->i2caux);
-
if (dc->ctx->created_bios)
dal_bios_parser_destroy(&dc->ctx->dc_bios);
dc_ctx->created_bios = true;
}
- /* Create I2C AUX */
- dc_ctx->i2caux = dal_i2caux_create(dc_ctx);
-
- if (!dc_ctx->i2caux) {
- ASSERT_CRITICAL(false);
- goto fail;
- }
-
dc_ctx->perf_trace = dc_perf_trace_create();
if (!dc_ctx->perf_trace) {
ASSERT_CRITICAL(false);
#include "include/vector.h"
#include "core_types.h"
#include "dc_link_ddc.h"
-#include "aux_engine.h"
#include "dce/dce_aux.h"
#define AUX_POWER_UP_WA_DELAY 500
struct dc_bios *dc_bios;
bool created_bios;
struct gpio_service *gpio_service;
- struct i2caux *i2caux;
uint32_t dc_sink_id_count;
uint32_t dc_stream_id_count;
uint64_t fbc_gpu_addr;
#ifndef __DAL_AUX_ENGINE_DCE110_H__
#define __DAL_AUX_ENGINE_DCE110_H__
-#include "aux_engine.h"
+
+#include "i2caux_interface.h"
+#include "inc/hw/aux_engine.h"
#define AUX_COMMON_REG_LIST(id)\
SRI(AUX_CONTROL, DP_AUX, id), \
+++ /dev/null
-/*
- * Copyright 2012-15 Advanced Micro Devices, Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- * Authors: AMD
- *
- */
-
-#include "dm_services.h"
-#include "dm_event_log.h"
-
-/*
- * Pre-requisites: headers required by header of this unit
- */
-#include "include/i2caux_interface.h"
-#include "engine.h"
-
-/*
- * Header of this unit
- */
-
-#include "aux_engine.h"
-
-/*
- * Post-requisites: headers required by this unit
- */
-
-#include "include/link_service_types.h"
-
-/*
- * This unit
- */
-
-enum {
- AUX_INVALID_REPLY_RETRY_COUNTER = 1,
- AUX_TIMED_OUT_RETRY_COUNTER = 2,
- AUX_DEFER_RETRY_COUNTER = 6
-};
-
-#define FROM_ENGINE(ptr) \
- container_of((ptr), struct aux_engine, base)
-#define DC_LOGGER \
- engine->base.ctx->logger
-
-enum i2caux_engine_type dal_aux_engine_get_engine_type(
- const struct engine *engine)
-{
- return I2CAUX_ENGINE_TYPE_AUX;
-}
-
-bool dal_aux_engine_acquire(
- struct engine *engine,
- struct ddc *ddc)
-{
- struct aux_engine *aux_engine = FROM_ENGINE(engine);
-
- enum gpio_result result;
- if (aux_engine->funcs->is_engine_available) {
- /*check whether SW could use the engine*/
- if (!aux_engine->funcs->is_engine_available(aux_engine)) {
- return false;
- }
- }
-
- result = dal_ddc_open(ddc, GPIO_MODE_HARDWARE,
- GPIO_DDC_CONFIG_TYPE_MODE_AUX);
-
- if (result != GPIO_RESULT_OK)
- return false;
-
- if (!aux_engine->funcs->acquire_engine(aux_engine)) {
- dal_ddc_close(ddc);
- return false;
- }
-
- engine->ddc = ddc;
-
- return true;
-}
-
-struct read_command_context {
- uint8_t *buffer;
- uint32_t current_read_length;
- uint32_t offset;
- enum i2caux_transaction_status status;
-
- struct aux_request_transaction_data request;
- struct aux_reply_transaction_data reply;
-
- uint8_t returned_byte;
-
- uint32_t timed_out_retry_aux;
- uint32_t invalid_reply_retry_aux;
- uint32_t defer_retry_aux;
- uint32_t defer_retry_i2c;
- uint32_t invalid_reply_retry_aux_on_ack;
-
- bool transaction_complete;
- bool operation_succeeded;
-};
-
-static void process_read_reply(
- struct aux_engine *engine,
- struct read_command_context *ctx)
-{
- engine->funcs->process_channel_reply(engine, &ctx->reply);
-
- switch (ctx->reply.status) {
- case AUX_TRANSACTION_REPLY_AUX_ACK:
- ctx->defer_retry_aux = 0;
- if (ctx->returned_byte > ctx->current_read_length) {
- ctx->status =
- I2CAUX_TRANSACTION_STATUS_FAILED_PROTOCOL_ERROR;
- ctx->operation_succeeded = false;
- } else if (ctx->returned_byte < ctx->current_read_length) {
- ctx->current_read_length -= ctx->returned_byte;
-
- ctx->offset += ctx->returned_byte;
-
- ++ctx->invalid_reply_retry_aux_on_ack;
-
- if (ctx->invalid_reply_retry_aux_on_ack >
- AUX_INVALID_REPLY_RETRY_COUNTER) {
- ctx->status =
- I2CAUX_TRANSACTION_STATUS_FAILED_PROTOCOL_ERROR;
- ctx->operation_succeeded = false;
- }
- } else {
- ctx->status = I2CAUX_TRANSACTION_STATUS_SUCCEEDED;
- ctx->transaction_complete = true;
- ctx->operation_succeeded = true;
- }
- break;
- case AUX_TRANSACTION_REPLY_AUX_NACK:
- ctx->status = I2CAUX_TRANSACTION_STATUS_FAILED_NACK;
- ctx->operation_succeeded = false;
- break;
- case AUX_TRANSACTION_REPLY_AUX_DEFER:
- ++ctx->defer_retry_aux;
-
- if (ctx->defer_retry_aux > AUX_DEFER_RETRY_COUNTER) {
- ctx->status = I2CAUX_TRANSACTION_STATUS_FAILED_TIMEOUT;
- ctx->operation_succeeded = false;
- }
- break;
- case AUX_TRANSACTION_REPLY_I2C_DEFER:
- ctx->defer_retry_aux = 0;
-
- ++ctx->defer_retry_i2c;
-
- if (ctx->defer_retry_i2c > AUX_DEFER_RETRY_COUNTER) {
- ctx->status = I2CAUX_TRANSACTION_STATUS_FAILED_TIMEOUT;
- ctx->operation_succeeded = false;
- }
- break;
- case AUX_TRANSACTION_REPLY_HPD_DISCON:
- ctx->status = I2CAUX_TRANSACTION_STATUS_FAILED_HPD_DISCON;
- ctx->operation_succeeded = false;
- break;
- default:
- ctx->status = I2CAUX_TRANSACTION_STATUS_UNKNOWN;
- ctx->operation_succeeded = false;
- }
-}
-
-static void process_read_request(
- struct aux_engine *engine,
- struct read_command_context *ctx)
-{
- enum aux_channel_operation_result operation_result;
-
- engine->funcs->submit_channel_request(engine, &ctx->request);
-
- operation_result = engine->funcs->get_channel_status(
- engine, &ctx->returned_byte);
-
- switch (operation_result) {
- case AUX_CHANNEL_OPERATION_SUCCEEDED:
- if (ctx->returned_byte > ctx->current_read_length) {
- ctx->status =
- I2CAUX_TRANSACTION_STATUS_FAILED_PROTOCOL_ERROR;
- ctx->operation_succeeded = false;
- } else {
- ctx->timed_out_retry_aux = 0;
- ctx->invalid_reply_retry_aux = 0;
-
- ctx->reply.length = ctx->returned_byte;
- ctx->reply.data = ctx->buffer;
-
- process_read_reply(engine, ctx);
- }
- break;
- case AUX_CHANNEL_OPERATION_FAILED_INVALID_REPLY:
- ++ctx->invalid_reply_retry_aux;
-
- if (ctx->invalid_reply_retry_aux >
- AUX_INVALID_REPLY_RETRY_COUNTER) {
- ctx->status =
- I2CAUX_TRANSACTION_STATUS_FAILED_PROTOCOL_ERROR;
- ctx->operation_succeeded = false;
- } else
- udelay(400);
- break;
- case AUX_CHANNEL_OPERATION_FAILED_TIMEOUT:
- ++ctx->timed_out_retry_aux;
-
- if (ctx->timed_out_retry_aux > AUX_TIMED_OUT_RETRY_COUNTER) {
- ctx->status = I2CAUX_TRANSACTION_STATUS_FAILED_TIMEOUT;
- ctx->operation_succeeded = false;
- } else {
- /* DP 1.2a, table 2-58:
- * "S3: AUX Request CMD PENDING:
- * retry 3 times, with 400usec wait on each"
- * The HW timeout is set to 550usec,
- * so we should not wait here */
- }
- break;
- case AUX_CHANNEL_OPERATION_FAILED_HPD_DISCON:
- ctx->status = I2CAUX_TRANSACTION_STATUS_FAILED_HPD_DISCON;
- ctx->operation_succeeded = false;
- break;
- default:
- ctx->status = I2CAUX_TRANSACTION_STATUS_UNKNOWN;
- ctx->operation_succeeded = false;
- }
-}
-
-static bool read_command(
- struct aux_engine *engine,
- struct i2caux_transaction_request *request,
- bool middle_of_transaction)
-{
- struct read_command_context ctx;
-
- ctx.buffer = request->payload.data;
- ctx.current_read_length = request->payload.length;
- ctx.offset = 0;
- ctx.timed_out_retry_aux = 0;
- ctx.invalid_reply_retry_aux = 0;
- ctx.defer_retry_aux = 0;
- ctx.defer_retry_i2c = 0;
- ctx.invalid_reply_retry_aux_on_ack = 0;
- ctx.transaction_complete = false;
- ctx.operation_succeeded = true;
-
- if (request->payload.address_space ==
- I2CAUX_TRANSACTION_ADDRESS_SPACE_DPCD) {
- ctx.request.type = AUX_TRANSACTION_TYPE_DP;
- ctx.request.action = I2CAUX_TRANSACTION_ACTION_DP_READ;
- ctx.request.address = request->payload.address;
- } else if (request->payload.address_space ==
- I2CAUX_TRANSACTION_ADDRESS_SPACE_I2C) {
- ctx.request.type = AUX_TRANSACTION_TYPE_I2C;
- ctx.request.action = middle_of_transaction ?
- I2CAUX_TRANSACTION_ACTION_I2C_READ_MOT :
- I2CAUX_TRANSACTION_ACTION_I2C_READ;
- ctx.request.address = request->payload.address >> 1;
- } else {
- /* in DAL2, there was no return in such case */
- BREAK_TO_DEBUGGER();
- return false;
- }
-
- ctx.request.delay = 0;
-
- do {
- memset(ctx.buffer + ctx.offset, 0, ctx.current_read_length);
-
- ctx.request.data = ctx.buffer + ctx.offset;
- ctx.request.length = ctx.current_read_length;
-
- process_read_request(engine, &ctx);
-
- request->status = ctx.status;
-
- if (ctx.operation_succeeded && !ctx.transaction_complete)
- if (ctx.request.type == AUX_TRANSACTION_TYPE_I2C)
- msleep(engine->delay);
- } while (ctx.operation_succeeded && !ctx.transaction_complete);
-
- if (request->payload.address_space ==
- I2CAUX_TRANSACTION_ADDRESS_SPACE_DPCD) {
- DC_LOG_I2C_AUX("READ: addr:0x%x value:0x%x Result:%d",
- request->payload.address,
- request->payload.data[0],
- ctx.operation_succeeded);
- }
-
- return ctx.operation_succeeded;
-}
-
-struct write_command_context {
- bool mot;
-
- uint8_t *buffer;
- uint32_t current_write_length;
- enum i2caux_transaction_status status;
-
- struct aux_request_transaction_data request;
- struct aux_reply_transaction_data reply;
-
- uint8_t returned_byte;
-
- uint32_t timed_out_retry_aux;
- uint32_t invalid_reply_retry_aux;
- uint32_t defer_retry_aux;
- uint32_t defer_retry_i2c;
- uint32_t max_defer_retry;
- uint32_t ack_m_retry;
-
- uint8_t reply_data[DEFAULT_AUX_MAX_DATA_SIZE];
-
- bool transaction_complete;
- bool operation_succeeded;
-};
-
-static void process_write_reply(
- struct aux_engine *engine,
- struct write_command_context *ctx)
-{
- engine->funcs->process_channel_reply(engine, &ctx->reply);
-
- switch (ctx->reply.status) {
- case AUX_TRANSACTION_REPLY_AUX_ACK:
- ctx->operation_succeeded = true;
-
- if (ctx->returned_byte) {
- ctx->request.action = ctx->mot ?
- I2CAUX_TRANSACTION_ACTION_I2C_STATUS_REQUEST_MOT :
- I2CAUX_TRANSACTION_ACTION_I2C_STATUS_REQUEST;
-
- ctx->current_write_length = 0;
-
- ++ctx->ack_m_retry;
-
- if (ctx->ack_m_retry > AUX_DEFER_RETRY_COUNTER) {
- ctx->status =
- I2CAUX_TRANSACTION_STATUS_FAILED_TIMEOUT;
- ctx->operation_succeeded = false;
- } else
- udelay(300);
- } else {
- ctx->status = I2CAUX_TRANSACTION_STATUS_SUCCEEDED;
- ctx->defer_retry_aux = 0;
- ctx->ack_m_retry = 0;
- ctx->transaction_complete = true;
- }
- break;
- case AUX_TRANSACTION_REPLY_AUX_NACK:
- ctx->status = I2CAUX_TRANSACTION_STATUS_FAILED_NACK;
- ctx->operation_succeeded = false;
- break;
- case AUX_TRANSACTION_REPLY_AUX_DEFER:
- ++ctx->defer_retry_aux;
-
- if (ctx->defer_retry_aux > ctx->max_defer_retry) {
- ctx->status = I2CAUX_TRANSACTION_STATUS_FAILED_TIMEOUT;
- ctx->operation_succeeded = false;
- }
- break;
- case AUX_TRANSACTION_REPLY_I2C_DEFER:
- ctx->defer_retry_aux = 0;
- ctx->current_write_length = 0;
-
- ctx->request.action = ctx->mot ?
- I2CAUX_TRANSACTION_ACTION_I2C_STATUS_REQUEST_MOT :
- I2CAUX_TRANSACTION_ACTION_I2C_STATUS_REQUEST;
-
- ++ctx->defer_retry_i2c;
-
- if (ctx->defer_retry_i2c > ctx->max_defer_retry) {
- ctx->status = I2CAUX_TRANSACTION_STATUS_FAILED_TIMEOUT;
- ctx->operation_succeeded = false;
- }
- break;
- case AUX_TRANSACTION_REPLY_HPD_DISCON:
- ctx->status = I2CAUX_TRANSACTION_STATUS_FAILED_HPD_DISCON;
- ctx->operation_succeeded = false;
- break;
- default:
- ctx->status = I2CAUX_TRANSACTION_STATUS_UNKNOWN;
- ctx->operation_succeeded = false;
- }
-}
-
-static void process_write_request(
- struct aux_engine *engine,
- struct write_command_context *ctx)
-{
- enum aux_channel_operation_result operation_result;
-
- engine->funcs->submit_channel_request(engine, &ctx->request);
-
- operation_result = engine->funcs->get_channel_status(
- engine, &ctx->returned_byte);
-
- switch (operation_result) {
- case AUX_CHANNEL_OPERATION_SUCCEEDED:
- ctx->timed_out_retry_aux = 0;
- ctx->invalid_reply_retry_aux = 0;
-
- ctx->reply.length = ctx->returned_byte;
- ctx->reply.data = ctx->reply_data;
-
- process_write_reply(engine, ctx);
- break;
- case AUX_CHANNEL_OPERATION_FAILED_INVALID_REPLY:
- ++ctx->invalid_reply_retry_aux;
-
- if (ctx->invalid_reply_retry_aux >
- AUX_INVALID_REPLY_RETRY_COUNTER) {
- ctx->status =
- I2CAUX_TRANSACTION_STATUS_FAILED_PROTOCOL_ERROR;
- ctx->operation_succeeded = false;
- } else
- udelay(400);
- break;
- case AUX_CHANNEL_OPERATION_FAILED_TIMEOUT:
- ++ctx->timed_out_retry_aux;
-
- if (ctx->timed_out_retry_aux > AUX_TIMED_OUT_RETRY_COUNTER) {
- ctx->status = I2CAUX_TRANSACTION_STATUS_FAILED_TIMEOUT;
- ctx->operation_succeeded = false;
- } else {
- /* DP 1.2a, table 2-58:
- * "S3: AUX Request CMD PENDING:
- * retry 3 times, with 400usec wait on each"
- * The HW timeout is set to 550usec,
- * so we should not wait here */
- }
- break;
- case AUX_CHANNEL_OPERATION_FAILED_HPD_DISCON:
- ctx->status = I2CAUX_TRANSACTION_STATUS_FAILED_HPD_DISCON;
- ctx->operation_succeeded = false;
- break;
- default:
- ctx->status = I2CAUX_TRANSACTION_STATUS_UNKNOWN;
- ctx->operation_succeeded = false;
- }
-}
-
-static bool write_command(
- struct aux_engine *engine,
- struct i2caux_transaction_request *request,
- bool middle_of_transaction)
-{
- struct write_command_context ctx;
-
- ctx.mot = middle_of_transaction;
- ctx.buffer = request->payload.data;
- ctx.current_write_length = request->payload.length;
- ctx.timed_out_retry_aux = 0;
- ctx.invalid_reply_retry_aux = 0;
- ctx.defer_retry_aux = 0;
- ctx.defer_retry_i2c = 0;
- ctx.ack_m_retry = 0;
- ctx.transaction_complete = false;
- ctx.operation_succeeded = true;
-
- if (request->payload.address_space ==
- I2CAUX_TRANSACTION_ADDRESS_SPACE_DPCD) {
- ctx.request.type = AUX_TRANSACTION_TYPE_DP;
- ctx.request.action = I2CAUX_TRANSACTION_ACTION_DP_WRITE;
- ctx.request.address = request->payload.address;
- } else if (request->payload.address_space ==
- I2CAUX_TRANSACTION_ADDRESS_SPACE_I2C) {
- ctx.request.type = AUX_TRANSACTION_TYPE_I2C;
- ctx.request.action = middle_of_transaction ?
- I2CAUX_TRANSACTION_ACTION_I2C_WRITE_MOT :
- I2CAUX_TRANSACTION_ACTION_I2C_WRITE;
- ctx.request.address = request->payload.address >> 1;
- } else {
- /* in DAL2, there was no return in such case */
- BREAK_TO_DEBUGGER();
- return false;
- }
-
- ctx.request.delay = 0;
-
- ctx.max_defer_retry =
- (engine->max_defer_write_retry > AUX_DEFER_RETRY_COUNTER) ?
- engine->max_defer_write_retry : AUX_DEFER_RETRY_COUNTER;
-
- do {
- ctx.request.data = ctx.buffer;
- ctx.request.length = ctx.current_write_length;
-
- process_write_request(engine, &ctx);
-
- request->status = ctx.status;
-
- if (ctx.operation_succeeded && !ctx.transaction_complete)
- if (ctx.request.type == AUX_TRANSACTION_TYPE_I2C)
- msleep(engine->delay);
- } while (ctx.operation_succeeded && !ctx.transaction_complete);
-
- if (request->payload.address_space ==
- I2CAUX_TRANSACTION_ADDRESS_SPACE_DPCD) {
- DC_LOG_I2C_AUX("WRITE: addr:0x%x value:0x%x Result:%d",
- request->payload.address,
- request->payload.data[0],
- ctx.operation_succeeded);
- }
-
- return ctx.operation_succeeded;
-}
-
-static bool end_of_transaction_command(
- struct aux_engine *engine,
- struct i2caux_transaction_request *request)
-{
- struct i2caux_transaction_request dummy_request;
- uint8_t dummy_data;
-
- /* [tcheng] We only need to send the stop (read with MOT = 0)
- * for I2C-over-Aux, not native AUX */
-
- if (request->payload.address_space !=
- I2CAUX_TRANSACTION_ADDRESS_SPACE_I2C)
- return false;
-
- dummy_request.operation = request->operation;
- dummy_request.payload.address_space = request->payload.address_space;
- dummy_request.payload.address = request->payload.address;
-
- /*
- * Add a dummy byte due to some receiver quirk
- * where one byte is sent along with MOT = 0.
- * Ideally this should be 0.
- */
-
- dummy_request.payload.length = 0;
- dummy_request.payload.data = &dummy_data;
-
- if (request->operation == I2CAUX_TRANSACTION_READ)
- return read_command(engine, &dummy_request, false);
- else
- return write_command(engine, &dummy_request, false);
-
- /* according Syed, it does not need now DoDummyMOT */
-}
-
-bool dal_aux_engine_submit_request(
- struct engine *engine,
- struct i2caux_transaction_request *request,
- bool middle_of_transaction)
-{
- struct aux_engine *aux_engine = FROM_ENGINE(engine);
-
- bool result;
- bool mot_used = true;
-
- switch (request->operation) {
- case I2CAUX_TRANSACTION_READ:
- result = read_command(aux_engine, request, mot_used);
- break;
- case I2CAUX_TRANSACTION_WRITE:
- result = write_command(aux_engine, request, mot_used);
- break;
- default:
- result = false;
- }
-
- /* [tcheng]
- * need to send stop for the last transaction to free up the AUX
- * if the above command fails, this would be the last transaction */
-
- if (!middle_of_transaction || !result)
- end_of_transaction_command(aux_engine, request);
-
- /* mask AUX interrupt */
-
- return result;
-}
-
-void dal_aux_engine_construct(
- struct aux_engine *engine,
- struct dc_context *ctx)
-{
- dal_i2caux_construct_engine(&engine->base, ctx);
- engine->delay = 0;
- engine->max_defer_write_retry = 0;
-}
-
-void dal_aux_engine_destruct(
- struct aux_engine *engine)
-{
- dal_i2caux_destruct_engine(&engine->base);
-}
+++ /dev/null
-/*
- * Copyright 2012-15 Advanced Micro Devices, Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- * Authors: AMD
- *
- */
-
-#ifndef __DAL_AUX_ENGINE_H__
-#define __DAL_AUX_ENGINE_H__
-
-#include "dc_ddc_types.h"
-
-struct aux_engine;
-
-struct aux_engine_funcs {
- void (*destroy)(
- struct aux_engine **ptr);
- bool (*acquire_engine)(
- struct aux_engine *engine);
- void (*configure)(
- struct aux_engine *engine,
- union aux_config cfg);
- void (*submit_channel_request)(
- struct aux_engine *engine,
- struct aux_request_transaction_data *request);
- void (*process_channel_reply)(
- struct aux_engine *engine,
- struct aux_reply_transaction_data *reply);
- int (*read_channel_reply)(
- struct aux_engine *engine,
- uint32_t size,
- uint8_t *buffer,
- uint8_t *reply_result,
- uint32_t *sw_status);
- enum aux_channel_operation_result (*get_channel_status)(
- struct aux_engine *engine,
- uint8_t *returned_bytes);
- bool (*is_engine_available) (
- struct aux_engine *engine);
-};
-
-struct aux_engine {
- struct engine base;
- const struct aux_engine_funcs *funcs;
- /* following values are expressed in milliseconds */
- uint32_t delay;
- uint32_t max_defer_write_retry;
-
- bool acquire_reset;
-};
-
-void dal_aux_engine_construct(
- struct aux_engine *engine,
- struct dc_context *ctx);
-
-void dal_aux_engine_destruct(
- struct aux_engine *engine);
-bool dal_aux_engine_submit_request(
- struct engine *ptr,
- struct i2caux_transaction_request *request,
- bool middle_of_transaction);
-bool dal_aux_engine_acquire(
- struct engine *ptr,
- struct ddc *ddc);
-enum i2caux_engine_type dal_aux_engine_get_engine_type(
- const struct engine *engine);
-
-#endif
+++ /dev/null
-/*
- * Copyright 2012-15 Advanced Micro Devices, Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- * Authors: AMD
- *
- */
-
-#include "dm_services.h"
-
-#include "include/i2caux_interface.h"
-#include "../i2caux.h"
-#include "../engine.h"
-#include "../i2c_engine.h"
-#include "../i2c_sw_engine.h"
-#include "../i2c_hw_engine.h"
-
-#include "../dce110/aux_engine_dce110.h"
-#include "../dce110/i2c_hw_engine_dce110.h"
-#include "../dce110/i2caux_dce110.h"
-
-#include "dce/dce_10_0_d.h"
-#include "dce/dce_10_0_sh_mask.h"
-
-/* set register offset */
-#define SR(reg_name)\
- .reg_name = mm ## reg_name
-
-/* set register offset with instance */
-#define SRI(reg_name, block, id)\
- .reg_name = mm ## block ## id ## _ ## reg_name
-
-#define aux_regs(id)\
-[id] = {\
- AUX_COMMON_REG_LIST(id), \
- .AUX_RESET_MASK = 0 \
-}
-
-#define hw_engine_regs(id)\
-{\
- I2C_HW_ENGINE_COMMON_REG_LIST(id) \
-}
-
-static const struct dce110_aux_registers dce100_aux_regs[] = {
- aux_regs(0),
- aux_regs(1),
- aux_regs(2),
- aux_regs(3),
- aux_regs(4),
- aux_regs(5),
-};
-
-static const struct dce110_i2c_hw_engine_registers dce100_hw_engine_regs[] = {
- hw_engine_regs(1),
- hw_engine_regs(2),
- hw_engine_regs(3),
- hw_engine_regs(4),
- hw_engine_regs(5),
- hw_engine_regs(6)
-};
-
-static const struct dce110_i2c_hw_engine_shift i2c_shift = {
- I2C_COMMON_MASK_SH_LIST_DCE100(__SHIFT)
-};
-
-static const struct dce110_i2c_hw_engine_mask i2c_mask = {
- I2C_COMMON_MASK_SH_LIST_DCE100(_MASK)
-};
-
-struct i2caux *dal_i2caux_dce100_create(
- struct dc_context *ctx)
-{
- struct i2caux_dce110 *i2caux_dce110 =
- kzalloc(sizeof(struct i2caux_dce110), GFP_KERNEL);
-
- if (!i2caux_dce110) {
- ASSERT_CRITICAL(false);
- return NULL;
- }
-
- dal_i2caux_dce110_construct(i2caux_dce110,
- ctx,
- ARRAY_SIZE(dce100_aux_regs),
- dce100_aux_regs,
- dce100_hw_engine_regs,
- &i2c_shift,
- &i2c_mask);
- return &i2caux_dce110->base;
-}
+++ /dev/null
-/*
- * Copyright 2012-15 Advanced Micro Devices, Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- * Authors: AMD
- *
- */
-
-#ifndef __DAL_I2C_AUX_DCE100_H__
-#define __DAL_I2C_AUX_DCE100_H__
-
-struct i2caux *dal_i2caux_dce100_create(
- struct dc_context *ctx);
-
-#endif /* __DAL_I2C_AUX_DCE100_H__ */
+++ /dev/null
-/*
- * Copyright 2012-15 Advanced Micro Devices, Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- * Authors: AMD
- *
- */
-
-#include "dm_services.h"
-#include "dm_event_log.h"
-
-/*
- * Pre-requisites: headers required by header of this unit
- */
-#include "include/i2caux_interface.h"
-#include "../engine.h"
-#include "../aux_engine.h"
-
-/*
- * Header of this unit
- */
-
-#include "aux_engine_dce110.h"
-
-/*
- * Post-requisites: headers required by this unit
- */
-#include "dce/dce_11_0_sh_mask.h"
-
-#define CTX \
- aux110->base.base.ctx
-#define REG(reg_name)\
- (aux110->regs->reg_name)
-#include "reg_helper.h"
-
-/*
- * This unit
- */
-
-/*
- * @brief
- * Cast 'struct aux_engine *'
- * to 'struct aux_engine_dce110 *'
- */
-#define FROM_AUX_ENGINE(ptr) \
- container_of((ptr), struct aux_engine_dce110, base)
-
-/*
- * @brief
- * Cast 'struct engine *'
- * to 'struct aux_engine_dce110 *'
- */
-#define FROM_ENGINE(ptr) \
- FROM_AUX_ENGINE(container_of((ptr), struct aux_engine, base))
-
-static void release_engine(
- struct engine *engine)
-{
- struct aux_engine_dce110 *aux110 = FROM_ENGINE(engine);
-
- REG_UPDATE(AUX_ARB_CONTROL, AUX_SW_DONE_USING_AUX_REG, 1);
-}
-
-static void destruct(
- struct aux_engine_dce110 *engine);
-
-static void destroy(
- struct aux_engine **aux_engine)
-{
- struct aux_engine_dce110 *engine = FROM_AUX_ENGINE(*aux_engine);
-
- destruct(engine);
-
- kfree(engine);
-
- *aux_engine = NULL;
-}
-
-#define SW_CAN_ACCESS_AUX 1
-#define DMCU_CAN_ACCESS_AUX 2
-
-static bool is_engine_available(
- struct aux_engine *engine)
-{
- struct aux_engine_dce110 *aux110 = FROM_AUX_ENGINE(engine);
-
- uint32_t value = REG_READ(AUX_ARB_CONTROL);
- uint32_t field = get_reg_field_value(
- value,
- AUX_ARB_CONTROL,
- AUX_REG_RW_CNTL_STATUS);
-
- return (field != DMCU_CAN_ACCESS_AUX);
-}
-static bool acquire_engine(
- struct aux_engine *engine)
-{
- struct aux_engine_dce110 *aux110 = FROM_AUX_ENGINE(engine);
-
- uint32_t value = REG_READ(AUX_ARB_CONTROL);
- uint32_t field = get_reg_field_value(
- value,
- AUX_ARB_CONTROL,
- AUX_REG_RW_CNTL_STATUS);
- if (field == DMCU_CAN_ACCESS_AUX)
- return false;
- /* enable AUX before request SW to access AUX */
- value = REG_READ(AUX_CONTROL);
- field = get_reg_field_value(value,
- AUX_CONTROL,
- AUX_EN);
-
- if (field == 0) {
- set_reg_field_value(
- value,
- 1,
- AUX_CONTROL,
- AUX_EN);
-
- if (REG(AUX_RESET_MASK)) {
- /*DP_AUX block as part of the enable sequence*/
- set_reg_field_value(
- value,
- 1,
- AUX_CONTROL,
- AUX_RESET);
- }
-
- REG_WRITE(AUX_CONTROL, value);
-
- if (REG(AUX_RESET_MASK)) {
- /*poll HW to make sure reset it done*/
-
- REG_WAIT(AUX_CONTROL, AUX_RESET_DONE, 1,
- 1, 11);
-
- set_reg_field_value(
- value,
- 0,
- AUX_CONTROL,
- AUX_RESET);
-
- REG_WRITE(AUX_CONTROL, value);
-
- REG_WAIT(AUX_CONTROL, AUX_RESET_DONE, 0,
- 1, 11);
- }
- } /*if (field)*/
-
- /* request SW to access AUX */
- REG_UPDATE(AUX_ARB_CONTROL, AUX_SW_USE_AUX_REG_REQ, 1);
-
- value = REG_READ(AUX_ARB_CONTROL);
- field = get_reg_field_value(
- value,
- AUX_ARB_CONTROL,
- AUX_REG_RW_CNTL_STATUS);
-
- return (field == SW_CAN_ACCESS_AUX);
-}
-
-#define COMPOSE_AUX_SW_DATA_16_20(command, address) \
- ((command) | ((0xF0000 & (address)) >> 16))
-
-#define COMPOSE_AUX_SW_DATA_8_15(address) \
- ((0xFF00 & (address)) >> 8)
-
-#define COMPOSE_AUX_SW_DATA_0_7(address) \
- (0xFF & (address))
-
-static void submit_channel_request(
- struct aux_engine *engine,
- struct aux_request_transaction_data *request)
-{
- struct aux_engine_dce110 *aux110 = FROM_AUX_ENGINE(engine);
- uint32_t value;
- uint32_t length;
-
- bool is_write =
- ((request->type == AUX_TRANSACTION_TYPE_DP) &&
- (request->action == I2CAUX_TRANSACTION_ACTION_DP_WRITE)) ||
- ((request->type == AUX_TRANSACTION_TYPE_I2C) &&
- ((request->action == I2CAUX_TRANSACTION_ACTION_I2C_WRITE) ||
- (request->action == I2CAUX_TRANSACTION_ACTION_I2C_WRITE_MOT)));
- if (REG(AUXN_IMPCAL)) {
- /* clear_aux_error */
- REG_UPDATE_SEQ(AUXN_IMPCAL, AUXN_CALOUT_ERROR_AK,
- 1,
- 0);
-
- REG_UPDATE_SEQ(AUXP_IMPCAL, AUXP_CALOUT_ERROR_AK,
- 1,
- 0);
-
- /* force_default_calibrate */
- REG_UPDATE_1BY1_2(AUXN_IMPCAL,
- AUXN_IMPCAL_ENABLE, 1,
- AUXN_IMPCAL_OVERRIDE_ENABLE, 0);
-
- /* bug? why AUXN update EN and OVERRIDE_EN 1 by 1 while AUX P toggles OVERRIDE? */
-
- REG_UPDATE_SEQ(AUXP_IMPCAL, AUXP_IMPCAL_OVERRIDE_ENABLE,
- 1,
- 0);
- }
- /* set the delay and the number of bytes to write */
-
- /* The length include
- * the 4 bit header and the 20 bit address
- * (that is 3 byte).
- * If the requested length is non zero this means
- * an addition byte specifying the length is required. */
-
- length = request->length ? 4 : 3;
- if (is_write)
- length += request->length;
-
- REG_UPDATE_2(AUX_SW_CONTROL,
- AUX_SW_START_DELAY, request->delay,
- AUX_SW_WR_BYTES, length);
-
- /* program action and address and payload data (if 'is_write') */
- value = REG_UPDATE_4(AUX_SW_DATA,
- AUX_SW_INDEX, 0,
- AUX_SW_DATA_RW, 0,
- AUX_SW_AUTOINCREMENT_DISABLE, 1,
- AUX_SW_DATA, COMPOSE_AUX_SW_DATA_16_20(request->action, request->address));
-
- value = REG_SET_2(AUX_SW_DATA, value,
- AUX_SW_AUTOINCREMENT_DISABLE, 0,
- AUX_SW_DATA, COMPOSE_AUX_SW_DATA_8_15(request->address));
-
- value = REG_SET(AUX_SW_DATA, value,
- AUX_SW_DATA, COMPOSE_AUX_SW_DATA_0_7(request->address));
-
- if (request->length) {
- value = REG_SET(AUX_SW_DATA, value,
- AUX_SW_DATA, request->length - 1);
- }
-
- if (is_write) {
- /* Load the HW buffer with the Data to be sent.
- * This is relevant for write operation.
- * For read, the data recived data will be
- * processed in process_channel_reply(). */
- uint32_t i = 0;
-
- while (i < request->length) {
- value = REG_SET(AUX_SW_DATA, value,
- AUX_SW_DATA, request->data[i]);
-
- ++i;
- }
- }
-
- REG_UPDATE(AUX_INTERRUPT_CONTROL, AUX_SW_DONE_ACK, 1);
- REG_WAIT(AUX_SW_STATUS, AUX_SW_DONE, 0,
- 10, aux110->timeout_period/10);
- REG_UPDATE(AUX_SW_CONTROL, AUX_SW_GO, 1);
- EVENT_LOG_AUX_REQ(engine->base.ddc->pin_data->en, EVENT_LOG_AUX_ORIGIN_NATIVE,
- request->action, request->address, request->length, request->data);
-}
-
-static int read_channel_reply(struct aux_engine *engine, uint32_t size,
- uint8_t *buffer, uint8_t *reply_result,
- uint32_t *sw_status)
-{
- struct aux_engine_dce110 *aux110 = FROM_AUX_ENGINE(engine);
- uint32_t bytes_replied;
- uint32_t reply_result_32;
-
- *sw_status = REG_GET(AUX_SW_STATUS, AUX_SW_REPLY_BYTE_COUNT,
- &bytes_replied);
-
- /* In case HPD is LOW, exit AUX transaction */
- if ((*sw_status & AUX_SW_STATUS__AUX_SW_HPD_DISCON_MASK))
- return -1;
-
- /* Need at least the status byte */
- if (!bytes_replied)
- return -1;
-
- REG_UPDATE_1BY1_3(AUX_SW_DATA,
- AUX_SW_INDEX, 0,
- AUX_SW_AUTOINCREMENT_DISABLE, 1,
- AUX_SW_DATA_RW, 1);
-
- REG_GET(AUX_SW_DATA, AUX_SW_DATA, &reply_result_32);
- reply_result_32 = reply_result_32 >> 4;
- *reply_result = (uint8_t)reply_result_32;
-
- if (reply_result_32 == 0) { /* ACK */
- uint32_t i = 0;
-
- /* First byte was already used to get the command status */
- --bytes_replied;
-
- /* Do not overflow buffer */
- if (bytes_replied > size)
- return -1;
-
- while (i < bytes_replied) {
- uint32_t aux_sw_data_val;
-
- REG_GET(AUX_SW_DATA, AUX_SW_DATA, &aux_sw_data_val);
- buffer[i] = aux_sw_data_val;
- ++i;
- }
-
- return i;
- }
-
- return 0;
-}
-
-static void process_channel_reply(
- struct aux_engine *engine,
- struct aux_reply_transaction_data *reply)
-{
- int bytes_replied;
- uint8_t reply_result;
- uint32_t sw_status;
-
- bytes_replied = read_channel_reply(engine, reply->length, reply->data,
- &reply_result, &sw_status);
- EVENT_LOG_AUX_REP(engine->base.ddc->pin_data->en,
- EVENT_LOG_AUX_ORIGIN_NATIVE, reply_result,
- bytes_replied, reply->data);
-
- /* in case HPD is LOW, exit AUX transaction */
- if ((sw_status & AUX_SW_STATUS__AUX_SW_HPD_DISCON_MASK)) {
- reply->status = AUX_TRANSACTION_REPLY_HPD_DISCON;
- return;
- }
-
- if (bytes_replied < 0) {
- /* Need to handle an error case...
- * Hopefully, upper layer function won't call this function if
- * the number of bytes in the reply was 0, because there was
- * surely an error that was asserted that should have been
- * handled for hot plug case, this could happens
- */
- if (!(sw_status & AUX_SW_STATUS__AUX_SW_HPD_DISCON_MASK)) {
- reply->status = AUX_TRANSACTION_REPLY_INVALID;
- ASSERT_CRITICAL(false);
- return;
- }
- } else {
-
- switch (reply_result) {
- case 0: /* ACK */
- reply->status = AUX_TRANSACTION_REPLY_AUX_ACK;
- break;
- case 1: /* NACK */
- reply->status = AUX_TRANSACTION_REPLY_AUX_NACK;
- break;
- case 2: /* DEFER */
- reply->status = AUX_TRANSACTION_REPLY_AUX_DEFER;
- break;
- case 4: /* AUX ACK / I2C NACK */
- reply->status = AUX_TRANSACTION_REPLY_I2C_NACK;
- break;
- case 8: /* AUX ACK / I2C DEFER */
- reply->status = AUX_TRANSACTION_REPLY_I2C_DEFER;
- break;
- default:
- reply->status = AUX_TRANSACTION_REPLY_INVALID;
- }
- }
-}
-
-static enum aux_channel_operation_result get_channel_status(
- struct aux_engine *engine,
- uint8_t *returned_bytes)
-{
- struct aux_engine_dce110 *aux110 = FROM_AUX_ENGINE(engine);
-
- uint32_t value;
-
- if (returned_bytes == NULL) {
- /*caller pass NULL pointer*/
- ASSERT_CRITICAL(false);
- return AUX_CHANNEL_OPERATION_FAILED_REASON_UNKNOWN;
- }
- *returned_bytes = 0;
-
- /* poll to make sure that SW_DONE is asserted */
- value = REG_WAIT(AUX_SW_STATUS, AUX_SW_DONE, 1,
- 10, aux110->timeout_period/10);
-
- /* in case HPD is LOW, exit AUX transaction */
- if ((value & AUX_SW_STATUS__AUX_SW_HPD_DISCON_MASK))
- return AUX_CHANNEL_OPERATION_FAILED_HPD_DISCON;
-
- /* Note that the following bits are set in 'status.bits'
- * during CTS 4.2.1.2 (FW 3.3.1):
- * AUX_SW_RX_MIN_COUNT_VIOL, AUX_SW_RX_INVALID_STOP,
- * AUX_SW_RX_RECV_NO_DET, AUX_SW_RX_RECV_INVALID_H.
- *
- * AUX_SW_RX_MIN_COUNT_VIOL is an internal,
- * HW debugging bit and should be ignored. */
- if (value & AUX_SW_STATUS__AUX_SW_DONE_MASK) {
- if ((value & AUX_SW_STATUS__AUX_SW_RX_TIMEOUT_STATE_MASK) ||
- (value & AUX_SW_STATUS__AUX_SW_RX_TIMEOUT_MASK))
- return AUX_CHANNEL_OPERATION_FAILED_TIMEOUT;
-
- else if ((value & AUX_SW_STATUS__AUX_SW_RX_INVALID_STOP_MASK) ||
- (value & AUX_SW_STATUS__AUX_SW_RX_RECV_NO_DET_MASK) ||
- (value &
- AUX_SW_STATUS__AUX_SW_RX_RECV_INVALID_H_MASK) ||
- (value & AUX_SW_STATUS__AUX_SW_RX_RECV_INVALID_L_MASK))
- return AUX_CHANNEL_OPERATION_FAILED_INVALID_REPLY;
-
- *returned_bytes = get_reg_field_value(value,
- AUX_SW_STATUS,
- AUX_SW_REPLY_BYTE_COUNT);
-
- if (*returned_bytes == 0)
- return
- AUX_CHANNEL_OPERATION_FAILED_INVALID_REPLY;
- else {
- *returned_bytes -= 1;
- return AUX_CHANNEL_OPERATION_SUCCEEDED;
- }
- } else {
- /*time_elapsed >= aux_engine->timeout_period
- * AUX_SW_STATUS__AUX_SW_HPD_DISCON = at this point
- */
- ASSERT_CRITICAL(false);
- return AUX_CHANNEL_OPERATION_FAILED_TIMEOUT;
- }
-}
-
-static const struct aux_engine_funcs aux_engine_funcs = {
- .destroy = destroy,
- .acquire_engine = acquire_engine,
- .submit_channel_request = submit_channel_request,
- .process_channel_reply = process_channel_reply,
- .read_channel_reply = read_channel_reply,
- .get_channel_status = get_channel_status,
- .is_engine_available = is_engine_available,
-};
-
-static const struct engine_funcs engine_funcs = {
- .release_engine = release_engine,
- .submit_request = dal_aux_engine_submit_request,
- .get_engine_type = dal_aux_engine_get_engine_type,
- .acquire = dal_aux_engine_acquire,
-};
-
-static void construct(
- struct aux_engine_dce110 *engine,
- const struct aux_engine_dce110_init_data *aux_init_data)
-{
- dal_aux_engine_construct(&engine->base, aux_init_data->ctx);
- engine->base.base.funcs = &engine_funcs;
- engine->base.funcs = &aux_engine_funcs;
-
- engine->timeout_period = aux_init_data->timeout_period;
- engine->regs = aux_init_data->regs;
-}
-
-static void destruct(
- struct aux_engine_dce110 *engine)
-{
- dal_aux_engine_destruct(&engine->base);
-}
-
-struct aux_engine *dal_aux_engine_dce110_create(
- const struct aux_engine_dce110_init_data *aux_init_data)
-{
- struct aux_engine_dce110 *engine;
-
- if (!aux_init_data) {
- ASSERT_CRITICAL(false);
- return NULL;
- }
-
- engine = kzalloc(sizeof(*engine), GFP_KERNEL);
-
- if (!engine) {
- ASSERT_CRITICAL(false);
- return NULL;
- }
-
- construct(engine, aux_init_data);
- return &engine->base;
-}
+++ /dev/null
-/*
- * Copyright 2012-15 Advanced Micro Devices, Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- * Authors: AMD
- *
- */
-
-#ifndef __DAL_AUX_ENGINE_DCE110_H__
-#define __DAL_AUX_ENGINE_DCE110_H__
-
-#include "../aux_engine.h"
-
-#define AUX_COMMON_REG_LIST(id)\
- SRI(AUX_CONTROL, DP_AUX, id), \
- SRI(AUX_ARB_CONTROL, DP_AUX, id), \
- SRI(AUX_SW_DATA, DP_AUX, id), \
- SRI(AUX_SW_CONTROL, DP_AUX, id), \
- SRI(AUX_INTERRUPT_CONTROL, DP_AUX, id), \
- SRI(AUX_SW_STATUS, DP_AUX, id), \
- SR(AUXN_IMPCAL), \
- SR(AUXP_IMPCAL)
-
-struct dce110_aux_registers {
- uint32_t AUX_CONTROL;
- uint32_t AUX_ARB_CONTROL;
- uint32_t AUX_SW_DATA;
- uint32_t AUX_SW_CONTROL;
- uint32_t AUX_INTERRUPT_CONTROL;
- uint32_t AUX_SW_STATUS;
- uint32_t AUXN_IMPCAL;
- uint32_t AUXP_IMPCAL;
-
- uint32_t AUX_RESET_MASK;
-};
-
-struct aux_engine_dce110 {
- struct aux_engine base;
- const struct dce110_aux_registers *regs;
- struct {
- uint32_t aux_control;
- uint32_t aux_arb_control;
- uint32_t aux_sw_data;
- uint32_t aux_sw_control;
- uint32_t aux_interrupt_control;
- uint32_t aux_sw_status;
- } addr;
- uint32_t timeout_period;
-};
-
-struct aux_engine_dce110_init_data {
- uint32_t engine_id;
- uint32_t timeout_period;
- struct dc_context *ctx;
- const struct dce110_aux_registers *regs;
-};
-
-struct aux_engine *dal_aux_engine_dce110_create(
- const struct aux_engine_dce110_init_data *aux_init_data);
-
-#endif
+++ /dev/null
-/*
- * Copyright 2012-15 Advanced Micro Devices, Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- * Authors: AMD
- *
- */
-
-#ifndef __DAL_I2C_HW_ENGINE_DCE110_H__
-#define __DAL_I2C_HW_ENGINE_DCE110_H__
-
-#define I2C_HW_ENGINE_COMMON_REG_LIST(id)\
- SRI(SETUP, DC_I2C_DDC, id),\
- SRI(SPEED, DC_I2C_DDC, id),\
- SR(DC_I2C_ARBITRATION),\
- SR(DC_I2C_CONTROL),\
- SR(DC_I2C_SW_STATUS),\
- SR(DC_I2C_TRANSACTION0),\
- SR(DC_I2C_TRANSACTION1),\
- SR(DC_I2C_TRANSACTION2),\
- SR(DC_I2C_TRANSACTION3),\
- SR(DC_I2C_DATA),\
- SR(MICROSECOND_TIME_BASE_DIV)
-
-#define I2C_SF(reg_name, field_name, post_fix)\
- .field_name = reg_name ## __ ## field_name ## post_fix
-
-#define I2C_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(mask_sh)\
- I2C_SF(DC_I2C_DDC1_SETUP, DC_I2C_DDC1_ENABLE, mask_sh),\
- I2C_SF(DC_I2C_DDC1_SETUP, DC_I2C_DDC1_TIME_LIMIT, mask_sh),\
- I2C_SF(DC_I2C_DDC1_SETUP, DC_I2C_DDC1_DATA_DRIVE_EN, mask_sh),\
- I2C_SF(DC_I2C_DDC1_SETUP, DC_I2C_DDC1_CLK_DRIVE_EN, mask_sh),\
- I2C_SF(DC_I2C_DDC1_SETUP, DC_I2C_DDC1_DATA_DRIVE_SEL, mask_sh),\
- I2C_SF(DC_I2C_DDC1_SETUP, DC_I2C_DDC1_INTRA_TRANSACTION_DELAY, mask_sh),\
- I2C_SF(DC_I2C_DDC1_SETUP, DC_I2C_DDC1_INTRA_BYTE_DELAY, mask_sh),\
- I2C_SF(DC_I2C_ARBITRATION, DC_I2C_SW_DONE_USING_I2C_REG, mask_sh),\
- I2C_SF(DC_I2C_ARBITRATION, DC_I2C_NO_QUEUED_SW_GO, mask_sh),\
- I2C_SF(DC_I2C_ARBITRATION, DC_I2C_SW_PRIORITY, mask_sh),\
- I2C_SF(DC_I2C_CONTROL, DC_I2C_SOFT_RESET, mask_sh),\
- I2C_SF(DC_I2C_CONTROL, DC_I2C_SW_STATUS_RESET, mask_sh),\
- I2C_SF(DC_I2C_CONTROL, DC_I2C_GO, mask_sh),\
- I2C_SF(DC_I2C_CONTROL, DC_I2C_SEND_RESET, mask_sh),\
- I2C_SF(DC_I2C_CONTROL, DC_I2C_TRANSACTION_COUNT, mask_sh),\
- I2C_SF(DC_I2C_CONTROL, DC_I2C_DDC_SELECT, mask_sh),\
- I2C_SF(DC_I2C_DDC1_SPEED, DC_I2C_DDC1_PRESCALE, mask_sh),\
- I2C_SF(DC_I2C_DDC1_SPEED, DC_I2C_DDC1_THRESHOLD, mask_sh),\
- I2C_SF(DC_I2C_SW_STATUS, DC_I2C_SW_STOPPED_ON_NACK, mask_sh),\
- I2C_SF(DC_I2C_SW_STATUS, DC_I2C_SW_TIMEOUT, mask_sh),\
- I2C_SF(DC_I2C_SW_STATUS, DC_I2C_SW_ABORTED, mask_sh),\
- I2C_SF(DC_I2C_SW_STATUS, DC_I2C_SW_DONE, mask_sh),\
- I2C_SF(DC_I2C_SW_STATUS, DC_I2C_SW_STATUS, mask_sh),\
- I2C_SF(DC_I2C_TRANSACTION0, DC_I2C_STOP_ON_NACK0, mask_sh),\
- I2C_SF(DC_I2C_TRANSACTION0, DC_I2C_START0, mask_sh),\
- I2C_SF(DC_I2C_TRANSACTION0, DC_I2C_RW0, mask_sh),\
- I2C_SF(DC_I2C_TRANSACTION0, DC_I2C_STOP0, mask_sh),\
- I2C_SF(DC_I2C_TRANSACTION0, DC_I2C_COUNT0, mask_sh),\
- I2C_SF(DC_I2C_DATA, DC_I2C_DATA_RW, mask_sh),\
- I2C_SF(DC_I2C_DATA, DC_I2C_DATA, mask_sh),\
- I2C_SF(DC_I2C_DATA, DC_I2C_INDEX, mask_sh),\
- I2C_SF(DC_I2C_DATA, DC_I2C_INDEX_WRITE, mask_sh),\
- I2C_SF(MICROSECOND_TIME_BASE_DIV, XTAL_REF_DIV, mask_sh)
-
-#define I2C_COMMON_MASK_SH_LIST_DCE100(mask_sh)\
- I2C_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(mask_sh)
-
-#define I2C_COMMON_MASK_SH_LIST_DCE110(mask_sh)\
- I2C_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(mask_sh),\
- I2C_SF(DC_I2C_DDC1_SPEED, DC_I2C_DDC1_START_STOP_TIMING_CNTL, mask_sh)
-
-struct dce110_i2c_hw_engine_shift {
- uint8_t DC_I2C_DDC1_ENABLE;
- uint8_t DC_I2C_DDC1_TIME_LIMIT;
- uint8_t DC_I2C_DDC1_DATA_DRIVE_EN;
- uint8_t DC_I2C_DDC1_CLK_DRIVE_EN;
- uint8_t DC_I2C_DDC1_DATA_DRIVE_SEL;
- uint8_t DC_I2C_DDC1_INTRA_TRANSACTION_DELAY;
- uint8_t DC_I2C_DDC1_INTRA_BYTE_DELAY;
- uint8_t DC_I2C_SW_DONE_USING_I2C_REG;
- uint8_t DC_I2C_NO_QUEUED_SW_GO;
- uint8_t DC_I2C_SW_PRIORITY;
- uint8_t DC_I2C_SOFT_RESET;
- uint8_t DC_I2C_SW_STATUS_RESET;
- uint8_t DC_I2C_GO;
- uint8_t DC_I2C_SEND_RESET;
- uint8_t DC_I2C_TRANSACTION_COUNT;
- uint8_t DC_I2C_DDC_SELECT;
- uint8_t DC_I2C_DDC1_PRESCALE;
- uint8_t DC_I2C_DDC1_THRESHOLD;
- uint8_t DC_I2C_DDC1_START_STOP_TIMING_CNTL;
- uint8_t DC_I2C_SW_STOPPED_ON_NACK;
- uint8_t DC_I2C_SW_TIMEOUT;
- uint8_t DC_I2C_SW_ABORTED;
- uint8_t DC_I2C_SW_DONE;
- uint8_t DC_I2C_SW_STATUS;
- uint8_t DC_I2C_STOP_ON_NACK0;
- uint8_t DC_I2C_START0;
- uint8_t DC_I2C_RW0;
- uint8_t DC_I2C_STOP0;
- uint8_t DC_I2C_COUNT0;
- uint8_t DC_I2C_DATA_RW;
- uint8_t DC_I2C_DATA;
- uint8_t DC_I2C_INDEX;
- uint8_t DC_I2C_INDEX_WRITE;
- uint8_t XTAL_REF_DIV;
-};
-
-struct dce110_i2c_hw_engine_mask {
- uint32_t DC_I2C_DDC1_ENABLE;
- uint32_t DC_I2C_DDC1_TIME_LIMIT;
- uint32_t DC_I2C_DDC1_DATA_DRIVE_EN;
- uint32_t DC_I2C_DDC1_CLK_DRIVE_EN;
- uint32_t DC_I2C_DDC1_DATA_DRIVE_SEL;
- uint32_t DC_I2C_DDC1_INTRA_TRANSACTION_DELAY;
- uint32_t DC_I2C_DDC1_INTRA_BYTE_DELAY;
- uint32_t DC_I2C_SW_DONE_USING_I2C_REG;
- uint32_t DC_I2C_NO_QUEUED_SW_GO;
- uint32_t DC_I2C_SW_PRIORITY;
- uint32_t DC_I2C_SOFT_RESET;
- uint32_t DC_I2C_SW_STATUS_RESET;
- uint32_t DC_I2C_GO;
- uint32_t DC_I2C_SEND_RESET;
- uint32_t DC_I2C_TRANSACTION_COUNT;
- uint32_t DC_I2C_DDC_SELECT;
- uint32_t DC_I2C_DDC1_PRESCALE;
- uint32_t DC_I2C_DDC1_THRESHOLD;
- uint32_t DC_I2C_DDC1_START_STOP_TIMING_CNTL;
- uint32_t DC_I2C_SW_STOPPED_ON_NACK;
- uint32_t DC_I2C_SW_TIMEOUT;
- uint32_t DC_I2C_SW_ABORTED;
- uint32_t DC_I2C_SW_DONE;
- uint32_t DC_I2C_SW_STATUS;
- uint32_t DC_I2C_STOP_ON_NACK0;
- uint32_t DC_I2C_START0;
- uint32_t DC_I2C_RW0;
- uint32_t DC_I2C_STOP0;
- uint32_t DC_I2C_COUNT0;
- uint32_t DC_I2C_DATA_RW;
- uint32_t DC_I2C_DATA;
- uint32_t DC_I2C_INDEX;
- uint32_t DC_I2C_INDEX_WRITE;
- uint32_t XTAL_REF_DIV;
-};
-
-struct dce110_i2c_hw_engine_registers {
- uint32_t SETUP;
- uint32_t SPEED;
- uint32_t DC_I2C_ARBITRATION;
- uint32_t DC_I2C_CONTROL;
- uint32_t DC_I2C_SW_STATUS;
- uint32_t DC_I2C_TRANSACTION0;
- uint32_t DC_I2C_TRANSACTION1;
- uint32_t DC_I2C_TRANSACTION2;
- uint32_t DC_I2C_TRANSACTION3;
- uint32_t DC_I2C_DATA;
- uint32_t MICROSECOND_TIME_BASE_DIV;
-};
-
-struct i2c_hw_engine_dce110 {
- struct i2c_hw_engine base;
- const struct dce110_i2c_hw_engine_registers *regs;
- const struct dce110_i2c_hw_engine_shift *i2c_shift;
- const struct dce110_i2c_hw_engine_mask *i2c_mask;
- struct {
- uint32_t DC_I2C_DDCX_SETUP;
- uint32_t DC_I2C_DDCX_SPEED;
- } addr;
- uint32_t engine_id;
- /* expressed in kilohertz */
- uint32_t reference_frequency;
- /* number of bytes currently used in HW buffer */
- uint32_t buffer_used_bytes;
- /* number of bytes used for write transaction in HW buffer
- * - this will be used as the index to read from*/
- uint32_t buffer_used_write;
- /* number of pending transactions (before GO) */
- uint32_t transaction_count;
- uint32_t engine_keep_power_up_count;
- uint32_t i2_setup_time_limit;
-};
-
-struct i2c_hw_engine_dce110_create_arg {
- uint32_t engine_id;
- uint32_t reference_frequency;
- uint32_t default_speed;
- struct dc_context *ctx;
- const struct dce110_i2c_hw_engine_registers *regs;
- const struct dce110_i2c_hw_engine_shift *i2c_shift;
- const struct dce110_i2c_hw_engine_mask *i2c_mask;
-};
-
-struct i2c_engine *dal_i2c_hw_engine_dce110_create(
- const struct i2c_hw_engine_dce110_create_arg *arg);
-
-enum {
- I2C_SETUP_TIME_LIMIT_DCE = 255,
- I2C_SETUP_TIME_LIMIT_DCN = 3,
- I2C_HW_BUFFER_SIZE = 538,
- I2C_SEND_RESET_LENGTH_9 = 9,
- I2C_SEND_RESET_LENGTH_10 = 10,
-};
-#endif
+++ /dev/null
-/*
- * Copyright 2012-15 Advanced Micro Devices, Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- * Authors: AMD
- *
- */
-
-#include "dm_services.h"
-
-/*
- * Pre-requisites: headers required by header of this unit
- */
-#include "include/i2caux_interface.h"
-#include "../engine.h"
-#include "../i2c_engine.h"
-#include "../i2c_sw_engine.h"
-
-/*
- * Header of this unit
- */
-
-#include "i2c_sw_engine_dce110.h"
-
-/*
- * Post-requisites: headers required by this unit
- */
-
-/*
- * This unit
- */
-
-/*
- * @brief
- * Cast 'struct i2c_sw_engine *'
- * to 'struct i2c_sw_engine_dce110 *'
- */
-#define FROM_I2C_SW_ENGINE(ptr) \
- container_of((ptr), struct i2c_sw_engine_dce110, base)
-/*
- * @brief
- * Cast 'struct i2c_engine *'
- * to 'struct i2c_sw_engine_dce80 *'
- */
-#define FROM_I2C_ENGINE(ptr) \
- FROM_I2C_SW_ENGINE(container_of((ptr), struct i2c_sw_engine, base))
-
-/*
- * @brief
- * Cast 'struct engine *'
- * to 'struct i2c_sw_engine_dce80 *'
- */
-#define FROM_ENGINE(ptr) \
- FROM_I2C_ENGINE(container_of((ptr), struct i2c_engine, base))
-
-static void release_engine(
- struct engine *engine)
-{
-}
-
-static void destruct(
- struct i2c_sw_engine_dce110 *engine)
-{
- dal_i2c_sw_engine_destruct(&engine->base);
-}
-
-static void destroy(
- struct i2c_engine **engine)
-{
- struct i2c_sw_engine_dce110 *sw_engine = FROM_I2C_ENGINE(*engine);
-
- destruct(sw_engine);
-
- kfree(sw_engine);
-
- *engine = NULL;
-}
-
-static bool acquire_engine(
- struct i2c_engine *engine,
- struct ddc *ddc_handle)
-{
- return dal_i2caux_i2c_sw_engine_acquire_engine(engine, ddc_handle);
-}
-
-static const struct i2c_engine_funcs i2c_engine_funcs = {
- .acquire_engine = acquire_engine,
- .destroy = destroy,
- .get_speed = dal_i2c_sw_engine_get_speed,
- .set_speed = dal_i2c_sw_engine_set_speed,
- .setup_engine = dal_i2c_engine_setup_i2c_engine,
- .submit_channel_request = dal_i2c_sw_engine_submit_channel_request,
- .process_channel_reply = dal_i2c_engine_process_channel_reply,
- .get_channel_status = dal_i2c_sw_engine_get_channel_status,
-};
-
-static const struct engine_funcs engine_funcs = {
- .release_engine = release_engine,
- .get_engine_type = dal_i2c_sw_engine_get_engine_type,
- .acquire = dal_i2c_engine_acquire,
- .submit_request = dal_i2c_sw_engine_submit_request,
-};
-
-static void construct(
- struct i2c_sw_engine_dce110 *engine_dce110,
- const struct i2c_sw_engine_dce110_create_arg *arg_dce110)
-{
- struct i2c_sw_engine_create_arg arg_base;
-
- arg_base.ctx = arg_dce110->ctx;
- arg_base.default_speed = arg_dce110->default_speed;
-
- dal_i2c_sw_engine_construct(&engine_dce110->base, &arg_base);
-
- /*struct engine struct engine_funcs*/
- engine_dce110->base.base.base.funcs = &engine_funcs;
- /*struct i2c_engine struct i2c_engine_funcs*/
- engine_dce110->base.base.funcs = &i2c_engine_funcs;
- engine_dce110->base.default_speed = arg_dce110->default_speed;
- engine_dce110->engine_id = arg_dce110->engine_id;
-}
-
-struct i2c_engine *dal_i2c_sw_engine_dce110_create(
- const struct i2c_sw_engine_dce110_create_arg *arg)
-{
- struct i2c_sw_engine_dce110 *engine_dce110;
-
- if (!arg) {
- ASSERT_CRITICAL(false);
- return NULL;
- }
-
- engine_dce110 = kzalloc(sizeof(struct i2c_sw_engine_dce110),
- GFP_KERNEL);
-
- if (!engine_dce110) {
- ASSERT_CRITICAL(false);
- return NULL;
- }
-
- construct(engine_dce110, arg);
- return &engine_dce110->base.base;
-}
+++ /dev/null
-/*
- * Copyright 2012-15 Advanced Micro Devices, Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- * Authors: AMD
- *
- */
-
-#ifndef __DAL_I2C_SW_ENGINE_DCE110_H__
-#define __DAL_I2C_SW_ENGINE_DCE110_H__
-
-struct i2c_sw_engine_dce110 {
- struct i2c_sw_engine base;
- uint32_t engine_id;
-};
-
-struct i2c_sw_engine_dce110_create_arg {
- uint32_t engine_id;
- uint32_t default_speed;
- struct dc_context *ctx;
-};
-
-struct i2c_engine *dal_i2c_sw_engine_dce110_create(
- const struct i2c_sw_engine_dce110_create_arg *arg);
-
-#endif
+++ /dev/null
-/*
- * Copyright 2012-15 Advanced Micro Devices, Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- * Authors: AMD
- *
- */
-
-#include "dm_services.h"
-
-/*
- * Pre-requisites: headers required by header of this unit
- */
-#include "include/i2caux_interface.h"
-#include "../i2caux.h"
-#include "../engine.h"
-#include "../i2c_engine.h"
-#include "../i2c_sw_engine.h"
-#include "../i2c_hw_engine.h"
-
-/*
- * Header of this unit
- */
-#include "i2caux_dce110.h"
-
-#include "i2c_sw_engine_dce110.h"
-#include "i2c_hw_engine_dce110.h"
-#include "aux_engine_dce110.h"
-#include "../../dc.h"
-#include "dc_types.h"
-
-
-/*
- * Post-requisites: headers required by this unit
- */
-
-/*
- * This unit
- */
-/*cast pointer to struct i2caux TO pointer to struct i2caux_dce110*/
-#define FROM_I2C_AUX(ptr) \
- container_of((ptr), struct i2caux_dce110, base)
-
-static void destruct(
- struct i2caux_dce110 *i2caux_dce110)
-{
- dal_i2caux_destruct(&i2caux_dce110->base);
-}
-
-static void destroy(
- struct i2caux **i2c_engine)
-{
- struct i2caux_dce110 *i2caux_dce110 = FROM_I2C_AUX(*i2c_engine);
-
- destruct(i2caux_dce110);
-
- kfree(i2caux_dce110);
-
- *i2c_engine = NULL;
-}
-
-static struct i2c_engine *acquire_i2c_hw_engine(
- struct i2caux *i2caux,
- struct ddc *ddc)
-{
- struct i2caux_dce110 *i2caux_dce110 = FROM_I2C_AUX(i2caux);
-
- struct i2c_engine *engine = NULL;
- /* generic hw engine is not used for EDID read
- * It may be needed for external i2c device, like thermal chip,
- * TODO will be implemented when needed.
- * check dce80 bool non_generic for generic hw engine;
- */
-
- if (!ddc)
- return NULL;
-
- if (ddc->hw_info.hw_supported) {
- enum gpio_ddc_line line = dal_ddc_get_line(ddc);
-
- if (line < GPIO_DDC_LINE_COUNT)
- engine = i2caux->i2c_hw_engines[line];
- }
-
- if (!engine)
- return NULL;
-
- if (!i2caux_dce110->i2c_hw_buffer_in_use &&
- engine->base.funcs->acquire(&engine->base, ddc)) {
- i2caux_dce110->i2c_hw_buffer_in_use = true;
- return engine;
- }
-
- return NULL;
-}
-
-static void release_engine(
- struct i2caux *i2caux,
- struct engine *engine)
-{
- struct i2caux_dce110 *i2caux_dce110 = FROM_I2C_AUX(i2caux);
-
- if (engine->funcs->get_engine_type(engine) ==
- I2CAUX_ENGINE_TYPE_I2C_DDC_HW)
- i2caux_dce110->i2c_hw_buffer_in_use = false;
-
- dal_i2caux_release_engine(i2caux, engine);
-}
-
-static const enum gpio_ddc_line hw_ddc_lines[] = {
- GPIO_DDC_LINE_DDC1,
- GPIO_DDC_LINE_DDC2,
- GPIO_DDC_LINE_DDC3,
- GPIO_DDC_LINE_DDC4,
- GPIO_DDC_LINE_DDC5,
- GPIO_DDC_LINE_DDC6,
-};
-
-static const enum gpio_ddc_line hw_aux_lines[] = {
- GPIO_DDC_LINE_DDC1,
- GPIO_DDC_LINE_DDC2,
- GPIO_DDC_LINE_DDC3,
- GPIO_DDC_LINE_DDC4,
- GPIO_DDC_LINE_DDC5,
- GPIO_DDC_LINE_DDC6,
-};
-
-/* function table */
-static const struct i2caux_funcs i2caux_funcs = {
- .destroy = destroy,
- .acquire_i2c_hw_engine = acquire_i2c_hw_engine,
- .release_engine = release_engine,
- .acquire_i2c_sw_engine = dal_i2caux_acquire_i2c_sw_engine,
- .acquire_aux_engine = dal_i2caux_acquire_aux_engine,
-};
-
-#include "dce/dce_11_0_d.h"
-#include "dce/dce_11_0_sh_mask.h"
-
-/* set register offset */
-#define SR(reg_name)\
- .reg_name = mm ## reg_name
-
-/* set register offset with instance */
-#define SRI(reg_name, block, id)\
- .reg_name = mm ## block ## id ## _ ## reg_name
-
-#define aux_regs(id)\
-[id] = {\
- AUX_COMMON_REG_LIST(id), \
- .AUX_RESET_MASK = AUX_CONTROL__AUX_RESET_MASK \
-}
-
-#define hw_engine_regs(id)\
-{\
- I2C_HW_ENGINE_COMMON_REG_LIST(id) \
-}
-
-static const struct dce110_aux_registers dce110_aux_regs[] = {
- aux_regs(0),
- aux_regs(1),
- aux_regs(2),
- aux_regs(3),
- aux_regs(4),
- aux_regs(5)
-};
-
-static const struct dce110_i2c_hw_engine_registers i2c_hw_engine_regs[] = {
- hw_engine_regs(1),
- hw_engine_regs(2),
- hw_engine_regs(3),
- hw_engine_regs(4),
- hw_engine_regs(5),
- hw_engine_regs(6)
-};
-
-static const struct dce110_i2c_hw_engine_shift i2c_shift = {
- I2C_COMMON_MASK_SH_LIST_DCE110(__SHIFT)
-};
-
-static const struct dce110_i2c_hw_engine_mask i2c_mask = {
- I2C_COMMON_MASK_SH_LIST_DCE110(_MASK)
-};
-
-void dal_i2caux_dce110_construct(
- struct i2caux_dce110 *i2caux_dce110,
- struct dc_context *ctx,
- unsigned int num_i2caux_inst,
- const struct dce110_aux_registers aux_regs[],
- const struct dce110_i2c_hw_engine_registers i2c_hw_engine_regs[],
- const struct dce110_i2c_hw_engine_shift *i2c_shift,
- const struct dce110_i2c_hw_engine_mask *i2c_mask)
-{
- uint32_t i = 0;
- uint32_t reference_frequency = 0;
- bool use_i2c_sw_engine = false;
- struct i2caux *base = NULL;
- /*TODO: For CZ bring up, if dal_i2caux_get_reference_clock
- * does not return 48KHz, we need hard coded for 48Khz.
- * Some BIOS setting incorrect cause this
- * For production, we always get value from BIOS*/
- reference_frequency =
- dal_i2caux_get_reference_clock(ctx->dc_bios) >> 1;
-
- base = &i2caux_dce110->base;
-
- dal_i2caux_construct(base, ctx);
-
- i2caux_dce110->base.funcs = &i2caux_funcs;
- i2caux_dce110->i2c_hw_buffer_in_use = false;
- /* Create I2C engines (DDC lines per connector)
- * different I2C/AUX usage cases, DDC, Generic GPIO, AUX.
- */
- do {
- enum gpio_ddc_line line_id = hw_ddc_lines[i];
-
- struct i2c_hw_engine_dce110_create_arg hw_arg_dce110;
-
- if (use_i2c_sw_engine) {
- struct i2c_sw_engine_dce110_create_arg sw_arg;
-
- sw_arg.engine_id = i;
- sw_arg.default_speed = base->default_i2c_sw_speed;
- sw_arg.ctx = ctx;
- base->i2c_sw_engines[line_id] =
- dal_i2c_sw_engine_dce110_create(&sw_arg);
- }
-
- hw_arg_dce110.engine_id = i;
- hw_arg_dce110.reference_frequency = reference_frequency;
- hw_arg_dce110.default_speed = base->default_i2c_hw_speed;
- hw_arg_dce110.ctx = ctx;
- hw_arg_dce110.regs = &i2c_hw_engine_regs[i];
- hw_arg_dce110.i2c_shift = i2c_shift;
- hw_arg_dce110.i2c_mask = i2c_mask;
-
- base->i2c_hw_engines[line_id] =
- dal_i2c_hw_engine_dce110_create(&hw_arg_dce110);
- if (base->i2c_hw_engines[line_id] != NULL) {
- switch (ctx->dce_version) {
- case DCN_VERSION_1_0:
- base->i2c_hw_engines[line_id]->setup_limit =
- I2C_SETUP_TIME_LIMIT_DCN;
- base->i2c_hw_engines[line_id]->send_reset_length = 0;
- break;
- default:
- base->i2c_hw_engines[line_id]->setup_limit =
- I2C_SETUP_TIME_LIMIT_DCE;
- base->i2c_hw_engines[line_id]->send_reset_length = 0;
- break;
- }
- }
- ++i;
- } while (i < num_i2caux_inst);
-
- /* Create AUX engines for all lines which has assisted HW AUX
- * 'i' (loop counter) used as DDC/AUX engine_id */
-
- i = 0;
-
- do {
- enum gpio_ddc_line line_id = hw_aux_lines[i];
-
- struct aux_engine_dce110_init_data aux_init_data;
-
- aux_init_data.engine_id = i;
- aux_init_data.timeout_period = base->aux_timeout_period;
- aux_init_data.ctx = ctx;
- aux_init_data.regs = &aux_regs[i];
-
- base->aux_engines[line_id] =
- dal_aux_engine_dce110_create(&aux_init_data);
-
- ++i;
- } while (i < num_i2caux_inst);
-
- /*TODO Generic I2C SW and HW*/
-}
-
-/*
- * dal_i2caux_dce110_create
- *
- * @brief
- * public interface to allocate memory for DCE11 I2CAUX
- *
- * @param
- * struct adapter_service *as - [in]
- * struct dc_context *ctx - [in]
- *
- * @return
- * pointer to the base struct of DCE11 I2CAUX
- */
-struct i2caux *dal_i2caux_dce110_create(
- struct dc_context *ctx)
-{
- struct i2caux_dce110 *i2caux_dce110 =
- kzalloc(sizeof(struct i2caux_dce110), GFP_KERNEL);
-
- if (!i2caux_dce110) {
- ASSERT_CRITICAL(false);
- return NULL;
- }
-
- dal_i2caux_dce110_construct(i2caux_dce110,
- ctx,
- ARRAY_SIZE(dce110_aux_regs),
- dce110_aux_regs,
- i2c_hw_engine_regs,
- &i2c_shift,
- &i2c_mask);
- return &i2caux_dce110->base;
-}
+++ /dev/null
-/*
- * Copyright 2012-15 Advanced Micro Devices, Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- * Authors: AMD
- *
- */
-
-#ifndef __DAL_I2C_AUX_DCE110_H__
-#define __DAL_I2C_AUX_DCE110_H__
-
-#include "../i2caux.h"
-
-struct i2caux_dce110 {
- struct i2caux base;
- /* indicate the I2C HW circular buffer is in use */
- bool i2c_hw_buffer_in_use;
-};
-
-struct dce110_aux_registers;
-struct dce110_i2c_hw_engine_registers;
-struct dce110_i2c_hw_engine_shift;
-struct dce110_i2c_hw_engine_mask;
-
-struct i2caux *dal_i2caux_dce110_create(
- struct dc_context *ctx);
-
-void dal_i2caux_dce110_construct(
- struct i2caux_dce110 *i2caux_dce110,
- struct dc_context *ctx,
- unsigned int num_i2caux_inst,
- const struct dce110_aux_registers *aux_regs,
- const struct dce110_i2c_hw_engine_registers *i2c_hw_engine_regs,
- const struct dce110_i2c_hw_engine_shift *i2c_shift,
- const struct dce110_i2c_hw_engine_mask *i2c_mask);
-
-#endif /* __DAL_I2C_AUX_DCE110_H__ */
+++ /dev/null
-/*
- * Copyright 2012-16 Advanced Micro Devices, Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- * Authors: AMD
- *
- */
-
-#include "dm_services.h"
-
-#include "include/i2caux_interface.h"
-#include "../i2caux.h"
-#include "../engine.h"
-#include "../i2c_engine.h"
-#include "../i2c_sw_engine.h"
-#include "../i2c_hw_engine.h"
-
-#include "../dce110/i2c_hw_engine_dce110.h"
-#include "../dce110/aux_engine_dce110.h"
-#include "../dce110/i2caux_dce110.h"
-
-#include "dce/dce_12_0_offset.h"
-#include "dce/dce_12_0_sh_mask.h"
-#include "soc15_hw_ip.h"
-#include "vega10_ip_offset.h"
-
-/* begin *********************
- * macros to expend register list macro defined in HW object header file */
-
-#define BASE_INNER(seg) \
- DCE_BASE__INST0_SEG ## seg
-
-/* compile time expand base address. */
-#define BASE(seg) \
- BASE_INNER(seg)
-
-#define SR(reg_name)\
- .reg_name = BASE(mm ## reg_name ## _BASE_IDX) + \
- mm ## reg_name
-
-#define SRI(reg_name, block, id)\
- .reg_name = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
- mm ## block ## id ## _ ## reg_name
-/* macros to expend register list macro defined in HW object header file
- * end *********************/
-
-#define aux_regs(id)\
-[id] = {\
- AUX_COMMON_REG_LIST(id), \
- .AUX_RESET_MASK = DP_AUX0_AUX_CONTROL__AUX_RESET_MASK \
-}
-
-static const struct dce110_aux_registers dce120_aux_regs[] = {
- aux_regs(0),
- aux_regs(1),
- aux_regs(2),
- aux_regs(3),
- aux_regs(4),
- aux_regs(5),
-};
-
-#define hw_engine_regs(id)\
-{\
- I2C_HW_ENGINE_COMMON_REG_LIST(id) \
-}
-
-static const struct dce110_i2c_hw_engine_registers dce120_hw_engine_regs[] = {
- hw_engine_regs(1),
- hw_engine_regs(2),
- hw_engine_regs(3),
- hw_engine_regs(4),
- hw_engine_regs(5),
- hw_engine_regs(6)
-};
-
-static const struct dce110_i2c_hw_engine_shift i2c_shift = {
- I2C_COMMON_MASK_SH_LIST_DCE110(__SHIFT)
-};
-
-static const struct dce110_i2c_hw_engine_mask i2c_mask = {
- I2C_COMMON_MASK_SH_LIST_DCE110(_MASK)
-};
-
-struct i2caux *dal_i2caux_dce120_create(
- struct dc_context *ctx)
-{
- struct i2caux_dce110 *i2caux_dce110 =
- kzalloc(sizeof(struct i2caux_dce110), GFP_KERNEL);
-
- if (!i2caux_dce110) {
- ASSERT_CRITICAL(false);
- return NULL;
- }
-
- dal_i2caux_dce110_construct(i2caux_dce110,
- ctx,
- ARRAY_SIZE(dce120_aux_regs),
- dce120_aux_regs,
- dce120_hw_engine_regs,
- &i2c_shift,
- &i2c_mask);
- return &i2caux_dce110->base;
-}
+++ /dev/null
-/*
- * Copyright 2012-16 Advanced Micro Devices, Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- * Authors: AMD
- *
- */
-
-#ifndef __DAL_I2C_AUX_DCE120_H__
-#define __DAL_I2C_AUX_DCE120_H__
-
-struct i2caux *dal_i2caux_dce120_create(
- struct dc_context *ctx);
-
-#endif /* __DAL_I2C_AUX_DCE120_H__ */
+++ /dev/null
-/*
- * Copyright 2012-15 Advanced Micro Devices, Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- * Authors: AMD
- *
- */
-
-#include "dm_services.h"
-
-/*
- * Pre-requisites: headers required by header of this unit
- */
-#include "include/i2caux_interface.h"
-#include "../engine.h"
-#include "../i2c_engine.h"
-#include "../i2c_hw_engine.h"
-#include "../i2c_generic_hw_engine.h"
-/*
- * Header of this unit
- */
-
-#include "i2c_hw_engine_dce80.h"
-
-/*
- * Post-requisites: headers required by this unit
- */
-
-#include "dce/dce_8_0_d.h"
-#include "dce/dce_8_0_sh_mask.h"
-/*
- * This unit
- */
-
-enum dc_i2c_status {
- DC_I2C_STATUS__DC_I2C_STATUS_IDLE,
- DC_I2C_STATUS__DC_I2C_STATUS_USED_BY_SW,
- DC_I2C_STATUS__DC_I2C_STATUS_USED_BY_HW
-};
-
-enum dc_i2c_arbitration {
- DC_I2C_ARBITRATION__DC_I2C_SW_PRIORITY_NORMAL,
- DC_I2C_ARBITRATION__DC_I2C_SW_PRIORITY_HIGH
-};
-
-enum {
- /* No timeout in HW
- * (timeout implemented in SW by querying status) */
- I2C_SETUP_TIME_LIMIT = 255,
- I2C_HW_BUFFER_SIZE = 144
-};
-
-/*
- * @brief
- * Cast 'struct i2c_hw_engine *'
- * to 'struct i2c_hw_engine_dce80 *'
- */
-#define FROM_I2C_HW_ENGINE(ptr) \
- container_of((ptr), struct i2c_hw_engine_dce80, base)
-
-/*
- * @brief
- * Cast pointer to 'struct i2c_engine *'
- * to pointer to 'struct i2c_hw_engine_dce80 *'
- */
-#define FROM_I2C_ENGINE(ptr) \
- FROM_I2C_HW_ENGINE(container_of((ptr), struct i2c_hw_engine, base))
-
-/*
- * @brief
- * Cast pointer to 'struct engine *'
- * to 'pointer to struct i2c_hw_engine_dce80 *'
- */
-#define FROM_ENGINE(ptr) \
- FROM_I2C_ENGINE(container_of((ptr), struct i2c_engine, base))
-
-static void disable_i2c_hw_engine(
- struct i2c_hw_engine_dce80 *engine)
-{
- const uint32_t addr = engine->addr.DC_I2C_DDCX_SETUP;
- uint32_t value = 0;
-
- struct dc_context *ctx = NULL;
-
- ctx = engine->base.base.base.ctx;
-
- value = dm_read_reg(ctx, addr);
-
- set_reg_field_value(
- value,
- 0,
- DC_I2C_DDC1_SETUP,
- DC_I2C_DDC1_ENABLE);
-
- dm_write_reg(ctx, addr, value);
-}
-
-static void release_engine(
- struct engine *engine)
-{
- struct i2c_hw_engine_dce80 *hw_engine = FROM_ENGINE(engine);
-
- struct i2c_engine *base = NULL;
- bool safe_to_reset;
- uint32_t value = 0;
-
- base = &hw_engine->base.base;
-
- /* Restore original HW engine speed */
-
- base->funcs->set_speed(base, hw_engine->base.original_speed);
-
- /* Release I2C */
- {
- value = dm_read_reg(engine->ctx, mmDC_I2C_ARBITRATION);
-
- set_reg_field_value(
- value,
- 1,
- DC_I2C_ARBITRATION,
- DC_I2C_SW_DONE_USING_I2C_REG);
-
- dm_write_reg(engine->ctx, mmDC_I2C_ARBITRATION, value);
- }
-
- /* Reset HW engine */
- {
- uint32_t i2c_sw_status = 0;
-
- value = dm_read_reg(engine->ctx, mmDC_I2C_SW_STATUS);
-
- i2c_sw_status = get_reg_field_value(
- value,
- DC_I2C_SW_STATUS,
- DC_I2C_SW_STATUS);
- /* if used by SW, safe to reset */
- safe_to_reset = (i2c_sw_status == 1);
- }
- {
- value = dm_read_reg(engine->ctx, mmDC_I2C_CONTROL);
-
- if (safe_to_reset)
- set_reg_field_value(
- value,
- 1,
- DC_I2C_CONTROL,
- DC_I2C_SOFT_RESET);
-
- set_reg_field_value(
- value,
- 1,
- DC_I2C_CONTROL,
- DC_I2C_SW_STATUS_RESET);
-
- dm_write_reg(engine->ctx, mmDC_I2C_CONTROL, value);
- }
-
- /* HW I2c engine - clock gating feature */
- if (!hw_engine->engine_keep_power_up_count)
- disable_i2c_hw_engine(hw_engine);
-}
-
-static void destruct(
- struct i2c_hw_engine_dce80 *engine)
-{
- dal_i2c_hw_engine_destruct(&engine->base);
-}
-
-static void destroy(
- struct i2c_engine **i2c_engine)
-{
- struct i2c_hw_engine_dce80 *engine = FROM_I2C_ENGINE(*i2c_engine);
-
- destruct(engine);
-
- kfree(engine);
-
- *i2c_engine = NULL;
-}
-
-static bool setup_engine(
- struct i2c_engine *i2c_engine)
-{
- uint32_t value = 0;
- struct i2c_hw_engine_dce80 *engine = FROM_I2C_ENGINE(i2c_engine);
-
- /* Program pin select */
- {
- const uint32_t addr = mmDC_I2C_CONTROL;
-
- value = dm_read_reg(i2c_engine->base.ctx, addr);
-
- set_reg_field_value(
- value,
- 0,
- DC_I2C_CONTROL,
- DC_I2C_GO);
-
- set_reg_field_value(
- value,
- 0,
- DC_I2C_CONTROL,
- DC_I2C_SOFT_RESET);
-
- set_reg_field_value(
- value,
- 0,
- DC_I2C_CONTROL,
- DC_I2C_SEND_RESET);
-
- set_reg_field_value(
- value,
- 0,
- DC_I2C_CONTROL,
- DC_I2C_SW_STATUS_RESET);
-
- set_reg_field_value(
- value,
- 0,
- DC_I2C_CONTROL,
- DC_I2C_TRANSACTION_COUNT);
-
- set_reg_field_value(
- value,
- engine->engine_id,
- DC_I2C_CONTROL,
- DC_I2C_DDC_SELECT);
-
- dm_write_reg(i2c_engine->base.ctx, addr, value);
- }
-
- /* Program time limit */
- {
- const uint32_t addr = engine->addr.DC_I2C_DDCX_SETUP;
-
- value = dm_read_reg(i2c_engine->base.ctx, addr);
-
- set_reg_field_value(
- value,
- I2C_SETUP_TIME_LIMIT,
- DC_I2C_DDC1_SETUP,
- DC_I2C_DDC1_TIME_LIMIT);
-
- set_reg_field_value(
- value,
- 1,
- DC_I2C_DDC1_SETUP,
- DC_I2C_DDC1_ENABLE);
-
- dm_write_reg(i2c_engine->base.ctx, addr, value);
- }
-
- /* Program HW priority
- * set to High - interrupt software I2C at any time
- * Enable restart of SW I2C that was interrupted by HW
- * disable queuing of software while I2C is in use by HW */
- {
- value = dm_read_reg(i2c_engine->base.ctx,
- mmDC_I2C_ARBITRATION);
-
- set_reg_field_value(
- value,
- 0,
- DC_I2C_ARBITRATION,
- DC_I2C_NO_QUEUED_SW_GO);
-
- set_reg_field_value(
- value,
- DC_I2C_ARBITRATION__DC_I2C_SW_PRIORITY_NORMAL,
- DC_I2C_ARBITRATION,
- DC_I2C_SW_PRIORITY);
-
- dm_write_reg(i2c_engine->base.ctx,
- mmDC_I2C_ARBITRATION, value);
- }
-
- return true;
-}
-
-static uint32_t get_speed(
- const struct i2c_engine *i2c_engine)
-{
- const struct i2c_hw_engine_dce80 *engine = FROM_I2C_ENGINE(i2c_engine);
-
- const uint32_t addr = engine->addr.DC_I2C_DDCX_SPEED;
-
- uint32_t pre_scale = 0;
-
- uint32_t value = dm_read_reg(i2c_engine->base.ctx, addr);
-
- pre_scale = get_reg_field_value(
- value,
- DC_I2C_DDC1_SPEED,
- DC_I2C_DDC1_PRESCALE);
-
- /* [anaumov] it seems following is unnecessary */
- /*ASSERT(value.bits.DC_I2C_DDC1_PRESCALE);*/
-
- return pre_scale ?
- engine->reference_frequency / pre_scale :
- engine->base.default_speed;
-}
-
-static void set_speed(
- struct i2c_engine *i2c_engine,
- uint32_t speed)
-{
- struct i2c_hw_engine_dce80 *engine = FROM_I2C_ENGINE(i2c_engine);
-
- if (speed) {
- const uint32_t addr = engine->addr.DC_I2C_DDCX_SPEED;
-
- uint32_t value = dm_read_reg(i2c_engine->base.ctx, addr);
-
- set_reg_field_value(
- value,
- engine->reference_frequency / speed,
- DC_I2C_DDC1_SPEED,
- DC_I2C_DDC1_PRESCALE);
-
- set_reg_field_value(
- value,
- 2,
- DC_I2C_DDC1_SPEED,
- DC_I2C_DDC1_THRESHOLD);
-
- dm_write_reg(i2c_engine->base.ctx, addr, value);
- }
-}
-
-static inline void reset_hw_engine(struct engine *engine)
-{
- uint32_t value = dm_read_reg(engine->ctx, mmDC_I2C_CONTROL);
-
- set_reg_field_value(
- value,
- 1,
- DC_I2C_CONTROL,
- DC_I2C_SOFT_RESET);
-
- set_reg_field_value(
- value,
- 1,
- DC_I2C_CONTROL,
- DC_I2C_SW_STATUS_RESET);
-
- dm_write_reg(engine->ctx, mmDC_I2C_CONTROL, value);
-}
-
-static bool is_hw_busy(struct engine *engine)
-{
- uint32_t i2c_sw_status = 0;
-
- uint32_t value = dm_read_reg(engine->ctx, mmDC_I2C_SW_STATUS);
-
- i2c_sw_status = get_reg_field_value(
- value,
- DC_I2C_SW_STATUS,
- DC_I2C_SW_STATUS);
-
- if (i2c_sw_status == DC_I2C_STATUS__DC_I2C_STATUS_IDLE)
- return false;
-
- reset_hw_engine(engine);
-
- value = dm_read_reg(engine->ctx, mmDC_I2C_SW_STATUS);
-
- i2c_sw_status = get_reg_field_value(
- value,
- DC_I2C_SW_STATUS,
- DC_I2C_SW_STATUS);
-
- return i2c_sw_status != DC_I2C_STATUS__DC_I2C_STATUS_IDLE;
-}
-
-/*
- * @brief
- * DC_GPIO_DDC MM register offsets
- */
-static const uint32_t transaction_addr[] = {
- mmDC_I2C_TRANSACTION0,
- mmDC_I2C_TRANSACTION1,
- mmDC_I2C_TRANSACTION2,
- mmDC_I2C_TRANSACTION3
-};
-
-static bool process_transaction(
- struct i2c_hw_engine_dce80 *engine,
- struct i2c_request_transaction_data *request)
-{
- uint32_t length = request->length;
- uint8_t *buffer = request->data;
-
- bool last_transaction = false;
- uint32_t value = 0;
-
- struct dc_context *ctx = NULL;
-
- ctx = engine->base.base.base.ctx;
-
- {
- const uint32_t addr =
- transaction_addr[engine->transaction_count];
-
- value = dm_read_reg(ctx, addr);
-
- set_reg_field_value(
- value,
- 1,
- DC_I2C_TRANSACTION0,
- DC_I2C_STOP_ON_NACK0);
-
- set_reg_field_value(
- value,
- 1,
- DC_I2C_TRANSACTION0,
- DC_I2C_START0);
-
- if ((engine->transaction_count == 3) ||
- (request->action == I2CAUX_TRANSACTION_ACTION_I2C_WRITE) ||
- (request->action & I2CAUX_TRANSACTION_ACTION_I2C_READ)) {
-
- set_reg_field_value(
- value,
- 1,
- DC_I2C_TRANSACTION0,
- DC_I2C_STOP0);
-
- last_transaction = true;
- } else
- set_reg_field_value(
- value,
- 0,
- DC_I2C_TRANSACTION0,
- DC_I2C_STOP0);
-
- set_reg_field_value(
- value,
- (0 != (request->action &
- I2CAUX_TRANSACTION_ACTION_I2C_READ)),
- DC_I2C_TRANSACTION0,
- DC_I2C_RW0);
-
- set_reg_field_value(
- value,
- length,
- DC_I2C_TRANSACTION0,
- DC_I2C_COUNT0);
-
- dm_write_reg(ctx, addr, value);
- }
-
- /* Write the I2C address and I2C data
- * into the hardware circular buffer, one byte per entry.
- * As an example, the 7-bit I2C slave address for CRT monitor
- * for reading DDC/EDID information is 0b1010001.
- * For an I2C send operation, the LSB must be programmed to 0;
- * for I2C receive operation, the LSB must be programmed to 1. */
-
- {
- value = 0;
-
- set_reg_field_value(
- value,
- false,
- DC_I2C_DATA,
- DC_I2C_DATA_RW);
-
- set_reg_field_value(
- value,
- request->address,
- DC_I2C_DATA,
- DC_I2C_DATA);
-
- if (engine->transaction_count == 0) {
- set_reg_field_value(
- value,
- 0,
- DC_I2C_DATA,
- DC_I2C_INDEX);
-
- /*enable index write*/
- set_reg_field_value(
- value,
- 1,
- DC_I2C_DATA,
- DC_I2C_INDEX_WRITE);
- }
-
- dm_write_reg(ctx, mmDC_I2C_DATA, value);
-
- if (!(request->action & I2CAUX_TRANSACTION_ACTION_I2C_READ)) {
-
- set_reg_field_value(
- value,
- 0,
- DC_I2C_DATA,
- DC_I2C_INDEX_WRITE);
-
- while (length) {
-
- set_reg_field_value(
- value,
- *buffer++,
- DC_I2C_DATA,
- DC_I2C_DATA);
-
- dm_write_reg(ctx, mmDC_I2C_DATA, value);
- --length;
- }
- }
- }
-
- ++engine->transaction_count;
- engine->buffer_used_bytes += length + 1;
-
- return last_transaction;
-}
-
-static void execute_transaction(
- struct i2c_hw_engine_dce80 *engine)
-{
- uint32_t value = 0;
- struct dc_context *ctx = NULL;
-
- ctx = engine->base.base.base.ctx;
-
- {
- const uint32_t addr = engine->addr.DC_I2C_DDCX_SETUP;
-
- value = dm_read_reg(ctx, addr);
-
- set_reg_field_value(
- value,
- 0,
- DC_I2C_DDC1_SETUP,
- DC_I2C_DDC1_DATA_DRIVE_EN);
-
- set_reg_field_value(
- value,
- 0,
- DC_I2C_DDC1_SETUP,
- DC_I2C_DDC1_CLK_DRIVE_EN);
-
- set_reg_field_value(
- value,
- 0,
- DC_I2C_DDC1_SETUP,
- DC_I2C_DDC1_DATA_DRIVE_SEL);
-
- set_reg_field_value(
- value,
- 0,
- DC_I2C_DDC1_SETUP,
- DC_I2C_DDC1_INTRA_TRANSACTION_DELAY);
-
- set_reg_field_value(
- value,
- 0,
- DC_I2C_DDC1_SETUP,
- DC_I2C_DDC1_INTRA_BYTE_DELAY);
-
- dm_write_reg(ctx, addr, value);
- }
-
- {
- const uint32_t addr = mmDC_I2C_CONTROL;
-
- value = dm_read_reg(ctx, addr);
-
- set_reg_field_value(
- value,
- 0,
- DC_I2C_CONTROL,
- DC_I2C_SOFT_RESET);
-
- set_reg_field_value(
- value,
- 0,
- DC_I2C_CONTROL,
- DC_I2C_SW_STATUS_RESET);
-
- set_reg_field_value(
- value,
- 0,
- DC_I2C_CONTROL,
- DC_I2C_SEND_RESET);
-
- set_reg_field_value(
- value,
- 0,
- DC_I2C_CONTROL,
- DC_I2C_GO);
-
- set_reg_field_value(
- value,
- engine->transaction_count - 1,
- DC_I2C_CONTROL,
- DC_I2C_TRANSACTION_COUNT);
-
- dm_write_reg(ctx, addr, value);
- }
-
- /* start I2C transfer */
- {
- const uint32_t addr = mmDC_I2C_CONTROL;
-
- value = dm_read_reg(ctx, addr);
-
- set_reg_field_value(
- value,
- 1,
- DC_I2C_CONTROL,
- DC_I2C_GO);
-
- dm_write_reg(ctx, addr, value);
- }
-
- /* all transactions were executed and HW buffer became empty
- * (even though it actually happens when status becomes DONE) */
- engine->transaction_count = 0;
- engine->buffer_used_bytes = 0;
-}
-
-static void submit_channel_request(
- struct i2c_engine *engine,
- struct i2c_request_transaction_data *request)
-{
- request->status = I2C_CHANNEL_OPERATION_SUCCEEDED;
-
- if (!process_transaction(FROM_I2C_ENGINE(engine), request))
- return;
-
- if (is_hw_busy(&engine->base)) {
- request->status = I2C_CHANNEL_OPERATION_ENGINE_BUSY;
- return;
- }
-
- execute_transaction(FROM_I2C_ENGINE(engine));
-}
-
-static void process_channel_reply(
- struct i2c_engine *engine,
- struct i2c_reply_transaction_data *reply)
-{
- uint32_t length = reply->length;
- uint8_t *buffer = reply->data;
-
- uint32_t value = 0;
-
- /*set index*/
- set_reg_field_value(
- value,
- length - 1,
- DC_I2C_DATA,
- DC_I2C_INDEX);
-
- set_reg_field_value(
- value,
- 1,
- DC_I2C_DATA,
- DC_I2C_DATA_RW);
-
- set_reg_field_value(
- value,
- 1,
- DC_I2C_DATA,
- DC_I2C_INDEX_WRITE);
-
- dm_write_reg(engine->base.ctx, mmDC_I2C_DATA, value);
-
- while (length) {
- /* after reading the status,
- * if the I2C operation executed successfully
- * (i.e. DC_I2C_STATUS_DONE = 1) then the I2C controller
- * should read data bytes from I2C circular data buffer */
-
- value = dm_read_reg(engine->base.ctx, mmDC_I2C_DATA);
-
- *buffer++ = get_reg_field_value(
- value,
- DC_I2C_DATA,
- DC_I2C_DATA);
-
- --length;
- }
-}
-
-static enum i2c_channel_operation_result get_channel_status(
- struct i2c_engine *engine,
- uint8_t *returned_bytes)
-{
- uint32_t i2c_sw_status = 0;
- uint32_t value = dm_read_reg(engine->base.ctx, mmDC_I2C_SW_STATUS);
-
- i2c_sw_status = get_reg_field_value(
- value,
- DC_I2C_SW_STATUS,
- DC_I2C_SW_STATUS);
-
- if (i2c_sw_status == DC_I2C_STATUS__DC_I2C_STATUS_USED_BY_SW)
- return I2C_CHANNEL_OPERATION_ENGINE_BUSY;
- else if (value & DC_I2C_SW_STATUS__DC_I2C_SW_STOPPED_ON_NACK_MASK)
- return I2C_CHANNEL_OPERATION_NO_RESPONSE;
- else if (value & DC_I2C_SW_STATUS__DC_I2C_SW_TIMEOUT_MASK)
- return I2C_CHANNEL_OPERATION_TIMEOUT;
- else if (value & DC_I2C_SW_STATUS__DC_I2C_SW_ABORTED_MASK)
- return I2C_CHANNEL_OPERATION_FAILED;
- else if (value & DC_I2C_SW_STATUS__DC_I2C_SW_DONE_MASK)
- return I2C_CHANNEL_OPERATION_SUCCEEDED;
-
- /*
- * this is the case when HW used for communication, I2C_SW_STATUS
- * could be zero
- */
- return I2C_CHANNEL_OPERATION_SUCCEEDED;
-}
-
-static uint32_t get_hw_buffer_available_size(
- const struct i2c_hw_engine *engine)
-{
- return I2C_HW_BUFFER_SIZE -
- FROM_I2C_HW_ENGINE(engine)->buffer_used_bytes;
-}
-
-static uint32_t get_transaction_timeout(
- const struct i2c_hw_engine *engine,
- uint32_t length)
-{
- uint32_t speed = engine->base.funcs->get_speed(&engine->base);
-
- uint32_t period_timeout;
- uint32_t num_of_clock_stretches;
-
- if (!speed)
- return 0;
-
- period_timeout = (1000 * TRANSACTION_TIMEOUT_IN_I2C_CLOCKS) / speed;
-
- num_of_clock_stretches = 1 + (length << 3) + 1;
- num_of_clock_stretches +=
- (FROM_I2C_HW_ENGINE(engine)->buffer_used_bytes << 3) +
- (FROM_I2C_HW_ENGINE(engine)->transaction_count << 1);
-
- return period_timeout * num_of_clock_stretches;
-}
-
-/*
- * @brief
- * DC_I2C_DDC1_SETUP MM register offsets
- *
- * @note
- * The indices of this offset array are DDC engine IDs
- */
-static const int32_t ddc_setup_offset[] = {
-
- mmDC_I2C_DDC1_SETUP - mmDC_I2C_DDC1_SETUP, /* DDC Engine 1 */
- mmDC_I2C_DDC2_SETUP - mmDC_I2C_DDC1_SETUP, /* DDC Engine 2 */
- mmDC_I2C_DDC3_SETUP - mmDC_I2C_DDC1_SETUP, /* DDC Engine 3 */
- mmDC_I2C_DDC4_SETUP - mmDC_I2C_DDC1_SETUP, /* DDC Engine 4 */
- mmDC_I2C_DDC5_SETUP - mmDC_I2C_DDC1_SETUP, /* DDC Engine 5 */
- mmDC_I2C_DDC6_SETUP - mmDC_I2C_DDC1_SETUP, /* DDC Engine 6 */
- mmDC_I2C_DDCVGA_SETUP - mmDC_I2C_DDC1_SETUP /* DDC Engine 7 */
-};
-
-/*
- * @brief
- * DC_I2C_DDC1_SPEED MM register offsets
- *
- * @note
- * The indices of this offset array are DDC engine IDs
- */
-static const int32_t ddc_speed_offset[] = {
- mmDC_I2C_DDC1_SPEED - mmDC_I2C_DDC1_SPEED, /* DDC Engine 1 */
- mmDC_I2C_DDC2_SPEED - mmDC_I2C_DDC1_SPEED, /* DDC Engine 2 */
- mmDC_I2C_DDC3_SPEED - mmDC_I2C_DDC1_SPEED, /* DDC Engine 3 */
- mmDC_I2C_DDC4_SPEED - mmDC_I2C_DDC1_SPEED, /* DDC Engine 4 */
- mmDC_I2C_DDC5_SPEED - mmDC_I2C_DDC1_SPEED, /* DDC Engine 5 */
- mmDC_I2C_DDC6_SPEED - mmDC_I2C_DDC1_SPEED, /* DDC Engine 6 */
- mmDC_I2C_DDCVGA_SPEED - mmDC_I2C_DDC1_SPEED /* DDC Engine 7 */
-};
-
-static const struct i2c_engine_funcs i2c_engine_funcs = {
- .destroy = destroy,
- .get_speed = get_speed,
- .set_speed = set_speed,
- .setup_engine = setup_engine,
- .submit_channel_request = submit_channel_request,
- .process_channel_reply = process_channel_reply,
- .get_channel_status = get_channel_status,
- .acquire_engine = dal_i2c_hw_engine_acquire_engine,
-};
-
-static const struct engine_funcs engine_funcs = {
- .release_engine = release_engine,
- .get_engine_type = dal_i2c_hw_engine_get_engine_type,
- .acquire = dal_i2c_engine_acquire,
- .submit_request = dal_i2c_hw_engine_submit_request,
-};
-
-static const struct i2c_hw_engine_funcs i2c_hw_engine_funcs = {
- .get_hw_buffer_available_size =
- get_hw_buffer_available_size,
- .get_transaction_timeout =
- get_transaction_timeout,
- .wait_on_operation_result =
- dal_i2c_hw_engine_wait_on_operation_result,
-};
-
-static void construct(
- struct i2c_hw_engine_dce80 *engine,
- const struct i2c_hw_engine_dce80_create_arg *arg)
-{
- dal_i2c_hw_engine_construct(&engine->base, arg->ctx);
-
- engine->base.base.base.funcs = &engine_funcs;
- engine->base.base.funcs = &i2c_engine_funcs;
- engine->base.funcs = &i2c_hw_engine_funcs;
- engine->base.default_speed = arg->default_speed;
- engine->addr.DC_I2C_DDCX_SETUP =
- mmDC_I2C_DDC1_SETUP + ddc_setup_offset[arg->engine_id];
- engine->addr.DC_I2C_DDCX_SPEED =
- mmDC_I2C_DDC1_SPEED + ddc_speed_offset[arg->engine_id];
-
- engine->engine_id = arg->engine_id;
- engine->reference_frequency = arg->reference_frequency;
- engine->buffer_used_bytes = 0;
- engine->transaction_count = 0;
- engine->engine_keep_power_up_count = 1;
-}
-
-struct i2c_engine *dal_i2c_hw_engine_dce80_create(
- const struct i2c_hw_engine_dce80_create_arg *arg)
-{
- struct i2c_hw_engine_dce80 *engine;
-
- if (!arg) {
- BREAK_TO_DEBUGGER();
- return NULL;
- }
-
- if ((arg->engine_id >= sizeof(ddc_setup_offset) / sizeof(int32_t)) ||
- (arg->engine_id >= sizeof(ddc_speed_offset) / sizeof(int32_t)) ||
- !arg->reference_frequency) {
- BREAK_TO_DEBUGGER();
- return NULL;
- }
-
- engine = kzalloc(sizeof(struct i2c_hw_engine_dce80), GFP_KERNEL);
-
- if (!engine) {
- BREAK_TO_DEBUGGER();
- return NULL;
- }
-
- construct(engine, arg);
- return &engine->base.base;
-}
+++ /dev/null
-/*
- * Copyright 2012-15 Advanced Micro Devices, Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- * Authors: AMD
- *
- */
-
-#ifndef __DAL_I2C_HW_ENGINE_DCE80_H__
-#define __DAL_I2C_HW_ENGINE_DCE80_H__
-
-struct i2c_hw_engine_dce80 {
- struct i2c_hw_engine base;
- struct {
- uint32_t DC_I2C_DDCX_SETUP;
- uint32_t DC_I2C_DDCX_SPEED;
- } addr;
- uint32_t engine_id;
- /* expressed in kilohertz */
- uint32_t reference_frequency;
- /* number of bytes currently used in HW buffer */
- uint32_t buffer_used_bytes;
- /* number of pending transactions (before GO) */
- uint32_t transaction_count;
- uint32_t engine_keep_power_up_count;
-};
-
-struct i2c_hw_engine_dce80_create_arg {
- uint32_t engine_id;
- uint32_t reference_frequency;
- uint32_t default_speed;
- struct dc_context *ctx;
-};
-
-struct i2c_engine *dal_i2c_hw_engine_dce80_create(
- const struct i2c_hw_engine_dce80_create_arg *arg);
-#endif
+++ /dev/null
-/*
- * Copyright 2012-15 Advanced Micro Devices, Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- * Authors: AMD
- *
- */
-
-#ifndef __DAL_I2C_SW_ENGINE_DCE80_H__
-#define __DAL_I2C_SW_ENGINE_DCE80_H__
-
-struct i2c_sw_engine_dce80 {
- struct i2c_sw_engine base;
- uint32_t engine_id;
-};
-
-struct i2c_sw_engine_dce80_create_arg {
- uint32_t engine_id;
- uint32_t default_speed;
- struct dc_context *ctx;
-};
-
-struct i2c_engine *dal_i2c_sw_engine_dce80_create(
- const struct i2c_sw_engine_dce80_create_arg *arg);
-
-#endif
+++ /dev/null
-/*
- * Copyright 2012-15 Advanced Micro Devices, Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- * Authors: AMD
- *
- */
-
-#include "dm_services.h"
-
-/*
- * Pre-requisites: headers required by header of this unit
- */
-#include "include/i2caux_interface.h"
-#include "../i2caux.h"
-
-/*
- * Header of this unit
- */
-
-#include "i2caux_dce80.h"
-
-/*
- * Post-requisites: headers required by this unit
- */
-
-#include "../engine.h"
-#include "../i2c_engine.h"
-#include "../i2c_sw_engine.h"
-#include "i2c_sw_engine_dce80.h"
-#include "../i2c_hw_engine.h"
-#include "i2c_hw_engine_dce80.h"
-#include "../i2c_generic_hw_engine.h"
-#include "../aux_engine.h"
-
-
-#include "../dce110/aux_engine_dce110.h"
-#include "../dce110/i2caux_dce110.h"
-
-#include "dce/dce_8_0_d.h"
-#include "dce/dce_8_0_sh_mask.h"
-
-
-/* set register offset */
-#define SR(reg_name)\
- .reg_name = mm ## reg_name
-
-/* set register offset with instance */
-#define SRI(reg_name, block, id)\
- .reg_name = mm ## block ## id ## _ ## reg_name
-
-#define aux_regs(id)\
-[id] = {\
- AUX_COMMON_REG_LIST(id), \
- .AUX_RESET_MASK = 0 \
-}
-
-static const struct dce110_aux_registers dce80_aux_regs[] = {
- aux_regs(0),
- aux_regs(1),
- aux_regs(2),
- aux_regs(3),
- aux_regs(4),
- aux_regs(5)
-};
-
-/*
- * This unit
- */
-
-#define FROM_I2C_AUX(ptr) \
- container_of((ptr), struct i2caux_dce80, base)
-
-static void destruct(
- struct i2caux_dce80 *i2caux_dce80)
-{
- dal_i2caux_destruct(&i2caux_dce80->base);
-}
-
-static void destroy(
- struct i2caux **i2c_engine)
-{
- struct i2caux_dce80 *i2caux_dce80 = FROM_I2C_AUX(*i2c_engine);
-
- destruct(i2caux_dce80);
-
- kfree(i2caux_dce80);
-
- *i2c_engine = NULL;
-}
-
-static struct i2c_engine *acquire_i2c_hw_engine(
- struct i2caux *i2caux,
- struct ddc *ddc)
-{
- struct i2caux_dce80 *i2caux_dce80 = FROM_I2C_AUX(i2caux);
-
- struct i2c_engine *engine = NULL;
- bool non_generic;
-
- if (!ddc)
- return NULL;
-
- if (ddc->hw_info.hw_supported) {
- enum gpio_ddc_line line = dal_ddc_get_line(ddc);
-
- if (line < GPIO_DDC_LINE_COUNT) {
- non_generic = true;
- engine = i2caux->i2c_hw_engines[line];
- }
- }
-
- if (!engine) {
- non_generic = false;
- engine = i2caux->i2c_generic_hw_engine;
- }
-
- if (!engine)
- return NULL;
-
- if (non_generic) {
- if (!i2caux_dce80->i2c_hw_buffer_in_use &&
- engine->base.funcs->acquire(&engine->base, ddc)) {
- i2caux_dce80->i2c_hw_buffer_in_use = true;
- return engine;
- }
- } else {
- if (engine->base.funcs->acquire(&engine->base, ddc))
- return engine;
- }
-
- return NULL;
-}
-
-static void release_engine(
- struct i2caux *i2caux,
- struct engine *engine)
-{
- if (engine->funcs->get_engine_type(engine) ==
- I2CAUX_ENGINE_TYPE_I2C_DDC_HW)
- FROM_I2C_AUX(i2caux)->i2c_hw_buffer_in_use = false;
-
- dal_i2caux_release_engine(i2caux, engine);
-}
-
-static const enum gpio_ddc_line hw_ddc_lines[] = {
- GPIO_DDC_LINE_DDC1,
- GPIO_DDC_LINE_DDC2,
- GPIO_DDC_LINE_DDC3,
- GPIO_DDC_LINE_DDC4,
- GPIO_DDC_LINE_DDC5,
- GPIO_DDC_LINE_DDC6,
- GPIO_DDC_LINE_DDC_VGA
-};
-
-static const enum gpio_ddc_line hw_aux_lines[] = {
- GPIO_DDC_LINE_DDC1,
- GPIO_DDC_LINE_DDC2,
- GPIO_DDC_LINE_DDC3,
- GPIO_DDC_LINE_DDC4,
- GPIO_DDC_LINE_DDC5,
- GPIO_DDC_LINE_DDC6
-};
-
-static const struct i2caux_funcs i2caux_funcs = {
- .destroy = destroy,
- .acquire_i2c_hw_engine = acquire_i2c_hw_engine,
- .release_engine = release_engine,
- .acquire_i2c_sw_engine = dal_i2caux_acquire_i2c_sw_engine,
- .acquire_aux_engine = dal_i2caux_acquire_aux_engine,
-};
-
-static void construct(
- struct i2caux_dce80 *i2caux_dce80,
- struct dc_context *ctx)
-{
- /* Entire family have I2C engine reference clock frequency
- * changed from XTALIN (27) to XTALIN/2 (13.5) */
-
- struct i2caux *base = &i2caux_dce80->base;
-
- uint32_t reference_frequency =
- dal_i2caux_get_reference_clock(ctx->dc_bios) >> 1;
-
- /*bool use_i2c_sw_engine = dal_adapter_service_is_feature_supported(as,
- FEATURE_RESTORE_USAGE_I2C_SW_ENGINE);*/
-
- /* Use SWI2C for dce8 currently, sicne we have bug with hwi2c */
- bool use_i2c_sw_engine = true;
-
- uint32_t i;
-
- dal_i2caux_construct(base, ctx);
-
- i2caux_dce80->base.funcs = &i2caux_funcs;
- i2caux_dce80->i2c_hw_buffer_in_use = false;
-
- /* Create I2C HW engines (HW + SW pairs)
- * for all lines which has assisted HW DDC
- * 'i' (loop counter) used as DDC/AUX engine_id */
-
- i = 0;
-
- do {
- enum gpio_ddc_line line_id = hw_ddc_lines[i];
-
- struct i2c_hw_engine_dce80_create_arg hw_arg;
-
- if (use_i2c_sw_engine) {
- struct i2c_sw_engine_dce80_create_arg sw_arg;
-
- sw_arg.engine_id = i;
- sw_arg.default_speed = base->default_i2c_sw_speed;
- sw_arg.ctx = ctx;
- base->i2c_sw_engines[line_id] =
- dal_i2c_sw_engine_dce80_create(&sw_arg);
- }
-
- hw_arg.engine_id = i;
- hw_arg.reference_frequency = reference_frequency;
- hw_arg.default_speed = base->default_i2c_hw_speed;
- hw_arg.ctx = ctx;
-
- base->i2c_hw_engines[line_id] =
- dal_i2c_hw_engine_dce80_create(&hw_arg);
-
- ++i;
- } while (i < ARRAY_SIZE(hw_ddc_lines));
-
- /* Create AUX engines for all lines which has assisted HW AUX
- * 'i' (loop counter) used as DDC/AUX engine_id */
-
- i = 0;
-
- do {
- enum gpio_ddc_line line_id = hw_aux_lines[i];
-
- struct aux_engine_dce110_init_data arg;
-
- arg.engine_id = i;
- arg.timeout_period = base->aux_timeout_period;
- arg.ctx = ctx;
- arg.regs = &dce80_aux_regs[i];
-
- base->aux_engines[line_id] =
- dal_aux_engine_dce110_create(&arg);
-
- ++i;
- } while (i < ARRAY_SIZE(hw_aux_lines));
-
- /* TODO Generic I2C SW and HW */
-}
-
-struct i2caux *dal_i2caux_dce80_create(
- struct dc_context *ctx)
-{
- struct i2caux_dce80 *i2caux_dce80 =
- kzalloc(sizeof(struct i2caux_dce80), GFP_KERNEL);
-
- if (!i2caux_dce80) {
- BREAK_TO_DEBUGGER();
- return NULL;
- }
-
- construct(i2caux_dce80, ctx);
- return &i2caux_dce80->base;
-}
+++ /dev/null
-/*
- * Copyright 2012-15 Advanced Micro Devices, Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- * Authors: AMD
- *
- */
-
-#ifndef __DAL_I2C_AUX_DCE80_H__
-#define __DAL_I2C_AUX_DCE80_H__
-
-struct i2caux_dce80 {
- struct i2caux base;
- /* indicate the I2C HW circular buffer is in use */
- bool i2c_hw_buffer_in_use;
-};
-
-struct i2caux *dal_i2caux_dce80_create(
- struct dc_context *ctx);
-
-#endif
+++ /dev/null
-/*
- * Copyright 2012-15 Advanced Micro Devices, Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- * Authors: AMD
- *
- */
-
-#include "dm_services.h"
-
-#include "include/i2caux_interface.h"
-#include "../i2caux.h"
-#include "../engine.h"
-#include "../i2c_engine.h"
-#include "../i2c_sw_engine.h"
-#include "../i2c_hw_engine.h"
-
-#include "../dce110/aux_engine_dce110.h"
-#include "../dce110/i2c_hw_engine_dce110.h"
-#include "../dce110/i2caux_dce110.h"
-
-#include "dcn/dcn_1_0_offset.h"
-#include "dcn/dcn_1_0_sh_mask.h"
-#include "soc15_hw_ip.h"
-#include "vega10_ip_offset.h"
-
-/* begin *********************
- * macros to expend register list macro defined in HW object header file */
-
-#define BASE_INNER(seg) \
- DCE_BASE__INST0_SEG ## seg
-
-/* compile time expand base address. */
-#define BASE(seg) \
- BASE_INNER(seg)
-
-#define SR(reg_name)\
- .reg_name = BASE(mm ## reg_name ## _BASE_IDX) + \
- mm ## reg_name
-
-#define SRI(reg_name, block, id)\
- .reg_name = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
- mm ## block ## id ## _ ## reg_name
-/* macros to expend register list macro defined in HW object header file
- * end *********************/
-
-#define aux_regs(id)\
-[id] = {\
- AUX_COMMON_REG_LIST(id), \
- .AUX_RESET_MASK = DP_AUX0_AUX_CONTROL__AUX_RESET_MASK \
-}
-
-#define hw_engine_regs(id)\
-{\
- I2C_HW_ENGINE_COMMON_REG_LIST(id) \
-}
-
-static const struct dce110_aux_registers dcn10_aux_regs[] = {
- aux_regs(0),
- aux_regs(1),
- aux_regs(2),
- aux_regs(3),
- aux_regs(4),
- aux_regs(5),
-};
-
-static const struct dce110_i2c_hw_engine_registers dcn10_hw_engine_regs[] = {
- hw_engine_regs(1),
- hw_engine_regs(2),
- hw_engine_regs(3),
- hw_engine_regs(4),
- hw_engine_regs(5),
- hw_engine_regs(6)
-};
-
-static const struct dce110_i2c_hw_engine_shift i2c_shift = {
- I2C_COMMON_MASK_SH_LIST_DCE110(__SHIFT)
-};
-
-static const struct dce110_i2c_hw_engine_mask i2c_mask = {
- I2C_COMMON_MASK_SH_LIST_DCE110(_MASK)
-};
-
-struct i2caux *dal_i2caux_dcn10_create(
- struct dc_context *ctx)
-{
- struct i2caux_dce110 *i2caux_dce110 =
- kzalloc(sizeof(struct i2caux_dce110), GFP_KERNEL);
-
- if (!i2caux_dce110) {
- ASSERT_CRITICAL(false);
- return NULL;
- }
-
- dal_i2caux_dce110_construct(i2caux_dce110,
- ctx,
- ARRAY_SIZE(dcn10_aux_regs),
- dcn10_aux_regs,
- dcn10_hw_engine_regs,
- &i2c_shift,
- &i2c_mask);
- return &i2caux_dce110->base;
-}
+++ /dev/null
-/*
- * Copyright 2012-15 Advanced Micro Devices, Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- * Authors: AMD
- *
- */
-
-#ifndef __DAL_I2C_AUX_DCN10_H__
-#define __DAL_I2C_AUX_DCN10_H__
-
-struct i2caux *dal_i2caux_dcn10_create(
- struct dc_context *ctx);
-
-#endif /* __DAL_I2C_AUX_DCN10_H__ */
+++ /dev/null
-/*
- * Copyright 2012-16 Advanced Micro Devices, Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- * Authors: AMD
- *
- */
-
-#include "dm_services.h"
-
-/*
- * Pre-requisites: headers required by header of this unit
- */
-#include "include/i2caux_interface.h"
-#include "../i2caux.h"
-#include "../engine.h"
-#include "../i2c_engine.h"
-#include "../i2c_sw_engine.h"
-#include "../i2c_hw_engine.h"
-
-/*
- * Header of this unit
- */
-#include "i2caux_diag.h"
-
-/*
- * Post-requisites: headers required by this unit
- */
-
-/*
- * This unit
- */
-
-static void destruct(
- struct i2caux *i2caux)
-{
- dal_i2caux_destruct(i2caux);
-}
-
-static void destroy(
- struct i2caux **i2c_engine)
-{
- destruct(*i2c_engine);
-
- kfree(*i2c_engine);
-
- *i2c_engine = NULL;
-}
-
-/* function table */
-static const struct i2caux_funcs i2caux_funcs = {
- .destroy = destroy,
- .acquire_i2c_hw_engine = NULL,
- .release_engine = NULL,
- .acquire_i2c_sw_engine = NULL,
- .acquire_aux_engine = NULL,
-};
-
-static void construct(
- struct i2caux *i2caux,
- struct dc_context *ctx)
-{
- dal_i2caux_construct(i2caux, ctx);
- i2caux->funcs = &i2caux_funcs;
-}
-
-struct i2caux *dal_i2caux_diag_fpga_create(
- struct dc_context *ctx)
-{
- struct i2caux *i2caux = kzalloc(sizeof(struct i2caux),
- GFP_KERNEL);
-
- if (!i2caux) {
- ASSERT_CRITICAL(false);
- return NULL;
- }
-
- construct(i2caux, ctx);
- return i2caux;
-}
+++ /dev/null
-/*
- * Copyright 2012-16 Advanced Micro Devices, Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- * Authors: AMD
- *
- */
-
-#ifndef __DAL_I2C_AUX_DIAG_FPGA_H__
-#define __DAL_I2C_AUX_DIAG_FPGA_H__
-
-struct i2caux *dal_i2caux_diag_fpga_create(
- struct dc_context *ctx);
-
-#endif /* __DAL_I2C_AUX_DIAG_FPGA_H__ */
+++ /dev/null
-/*
- * Copyright 2012-15 Advanced Micro Devices, Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- * Authors: AMD
- *
- */
-
-#ifndef __DAL_ENGINE_H__
-#define __DAL_ENGINE_H__
-
-#include "dc_ddc_types.h"
-
-enum i2caux_transaction_operation {
- I2CAUX_TRANSACTION_READ,
- I2CAUX_TRANSACTION_WRITE
-};
-
-enum i2caux_transaction_address_space {
- I2CAUX_TRANSACTION_ADDRESS_SPACE_I2C = 1,
- I2CAUX_TRANSACTION_ADDRESS_SPACE_DPCD
-};
-
-struct i2caux_transaction_payload {
- enum i2caux_transaction_address_space address_space;
- uint32_t address;
- uint32_t length;
- uint8_t *data;
-};
-
-enum i2caux_transaction_status {
- I2CAUX_TRANSACTION_STATUS_UNKNOWN = (-1L),
- I2CAUX_TRANSACTION_STATUS_SUCCEEDED,
- I2CAUX_TRANSACTION_STATUS_FAILED_CHANNEL_BUSY,
- I2CAUX_TRANSACTION_STATUS_FAILED_TIMEOUT,
- I2CAUX_TRANSACTION_STATUS_FAILED_PROTOCOL_ERROR,
- I2CAUX_TRANSACTION_STATUS_FAILED_NACK,
- I2CAUX_TRANSACTION_STATUS_FAILED_INCOMPLETE,
- I2CAUX_TRANSACTION_STATUS_FAILED_OPERATION,
- I2CAUX_TRANSACTION_STATUS_FAILED_INVALID_OPERATION,
- I2CAUX_TRANSACTION_STATUS_FAILED_BUFFER_OVERFLOW,
- I2CAUX_TRANSACTION_STATUS_FAILED_HPD_DISCON
-};
-
-struct i2caux_transaction_request {
- enum i2caux_transaction_operation operation;
- struct i2caux_transaction_payload payload;
- enum i2caux_transaction_status status;
-};
-
-enum i2caux_engine_type {
- I2CAUX_ENGINE_TYPE_UNKNOWN = (-1L),
- I2CAUX_ENGINE_TYPE_AUX,
- I2CAUX_ENGINE_TYPE_I2C_DDC_HW,
- I2CAUX_ENGINE_TYPE_I2C_GENERIC_HW,
- I2CAUX_ENGINE_TYPE_I2C_SW
-};
-
-enum i2c_default_speed {
- I2CAUX_DEFAULT_I2C_HW_SPEED = 50,
- I2CAUX_DEFAULT_I2C_SW_SPEED = 50
-};
-
-struct engine;
-
-struct engine_funcs {
- enum i2caux_engine_type (*get_engine_type)(
- const struct engine *engine);
- bool (*acquire)(
- struct engine *engine,
- struct ddc *ddc);
- bool (*submit_request)(
- struct engine *engine,
- struct i2caux_transaction_request *request,
- bool middle_of_transaction);
- void (*release_engine)(
- struct engine *engine);
-};
-
-struct engine {
- const struct engine_funcs *funcs;
- uint32_t inst;
- struct ddc *ddc;
- struct dc_context *ctx;
-};
-
-void dal_i2caux_construct_engine(
- struct engine *engine,
- struct dc_context *ctx);
-
-void dal_i2caux_destruct_engine(
- struct engine *engine);
-
-#endif
+++ /dev/null
-/*
- * Copyright 2012-15 Advanced Micro Devices, Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- * Authors: AMD
- *
- */
-
-#include "dm_services.h"
-
-/*
- * Pre-requisites: headers required by header of this unit
- */
-#include "include/i2caux_interface.h"
-
-/*
- * Header of this unit
- */
-
-#include "engine.h"
-
-void dal_i2caux_construct_engine(
- struct engine *engine,
- struct dc_context *ctx)
-{
- engine->ddc = NULL;
- engine->ctx = ctx;
-}
-
-void dal_i2caux_destruct_engine(
- struct engine *engine)
-{
- /* nothing to do */
-}
-
+++ /dev/null
-/*
- * Copyright 2012-15 Advanced Micro Devices, Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- * Authors: AMD
- *
- */
-
-#include "dm_services.h"
-
-/*
- * Pre-requisites: headers required by header of this unit
- */
-#include "include/i2caux_interface.h"
-#include "engine.h"
-
-/*
- * Header of this unit
- */
-
-#include "i2c_engine.h"
-
-/*
- * Post-requisites: headers required by this unit
- */
-
-/*
- * This unit
- */
-
-#define FROM_ENGINE(ptr) \
- container_of((ptr), struct i2c_engine, base)
-
-bool dal_i2c_engine_acquire(
- struct engine *engine,
- struct ddc *ddc_handle)
-{
- struct i2c_engine *i2c_engine = FROM_ENGINE(engine);
-
- uint32_t counter = 0;
- bool result;
-
- do {
- result = i2c_engine->funcs->acquire_engine(
- i2c_engine, ddc_handle);
-
- if (result)
- break;
-
- /* i2c_engine is busy by VBios, lets wait and retry */
-
- udelay(10);
-
- ++counter;
- } while (counter < 2);
-
- if (result) {
- if (!i2c_engine->funcs->setup_engine(i2c_engine)) {
- engine->funcs->release_engine(engine);
- result = false;
- }
- }
-
- return result;
-}
-
-bool dal_i2c_engine_setup_i2c_engine(
- struct i2c_engine *engine)
-{
- /* Derivative classes do not have to override this */
-
- return true;
-}
-
-void dal_i2c_engine_submit_channel_request(
- struct i2c_engine *engine,
- struct i2c_request_transaction_data *request)
-{
-
-}
-
-void dal_i2c_engine_process_channel_reply(
- struct i2c_engine *engine,
- struct i2c_reply_transaction_data *reply)
-{
-
-}
-
-void dal_i2c_engine_construct(
- struct i2c_engine *engine,
- struct dc_context *ctx)
-{
- dal_i2caux_construct_engine(&engine->base, ctx);
- engine->timeout_delay = 0;
-}
-
-void dal_i2c_engine_destruct(
- struct i2c_engine *engine)
-{
- dal_i2caux_destruct_engine(&engine->base);
-}
+++ /dev/null
-/*
- * Copyright 2012-15 Advanced Micro Devices, Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- * Authors: AMD
- *
- */
-
-#ifndef __DAL_I2C_ENGINE_H__
-#define __DAL_I2C_ENGINE_H__
-
-enum i2c_channel_operation_result {
- I2C_CHANNEL_OPERATION_SUCCEEDED,
- I2C_CHANNEL_OPERATION_FAILED,
- I2C_CHANNEL_OPERATION_NOT_GRANTED,
- I2C_CHANNEL_OPERATION_IS_BUSY,
- I2C_CHANNEL_OPERATION_NO_HANDLE_PROVIDED,
- I2C_CHANNEL_OPERATION_CHANNEL_IN_USE,
- I2C_CHANNEL_OPERATION_CHANNEL_CLIENT_MAX_ALLOWED,
- I2C_CHANNEL_OPERATION_ENGINE_BUSY,
- I2C_CHANNEL_OPERATION_TIMEOUT,
- I2C_CHANNEL_OPERATION_NO_RESPONSE,
- I2C_CHANNEL_OPERATION_HW_REQUEST_I2C_BUS,
- I2C_CHANNEL_OPERATION_WRONG_PARAMETER,
- I2C_CHANNEL_OPERATION_OUT_NB_OF_RETRIES,
- I2C_CHANNEL_OPERATION_NOT_STARTED
-};
-
-struct i2c_request_transaction_data {
- enum i2caux_transaction_action action;
- enum i2c_channel_operation_result status;
- uint8_t address;
- uint32_t length;
- uint8_t *data;
-};
-
-struct i2c_reply_transaction_data {
- uint32_t length;
- uint8_t *data;
-};
-
-struct i2c_engine;
-
-struct i2c_engine_funcs {
- void (*destroy)(
- struct i2c_engine **ptr);
- uint32_t (*get_speed)(
- const struct i2c_engine *engine);
- void (*set_speed)(
- struct i2c_engine *engine,
- uint32_t speed);
- bool (*acquire_engine)(
- struct i2c_engine *engine,
- struct ddc *ddc);
- bool (*setup_engine)(
- struct i2c_engine *engine);
- void (*submit_channel_request)(
- struct i2c_engine *engine,
- struct i2c_request_transaction_data *request);
- void (*process_channel_reply)(
- struct i2c_engine *engine,
- struct i2c_reply_transaction_data *reply);
- enum i2c_channel_operation_result (*get_channel_status)(
- struct i2c_engine *engine,
- uint8_t *returned_bytes);
-};
-
-struct i2c_engine {
- struct engine base;
- const struct i2c_engine_funcs *funcs;
- uint32_t timeout_delay;
- uint32_t setup_limit;
- uint32_t send_reset_length;
-};
-
-void dal_i2c_engine_construct(
- struct i2c_engine *engine,
- struct dc_context *ctx);
-
-void dal_i2c_engine_destruct(
- struct i2c_engine *engine);
-
-bool dal_i2c_engine_setup_i2c_engine(
- struct i2c_engine *engine);
-
-void dal_i2c_engine_submit_channel_request(
- struct i2c_engine *engine,
- struct i2c_request_transaction_data *request);
-
-void dal_i2c_engine_process_channel_reply(
- struct i2c_engine *engine,
- struct i2c_reply_transaction_data *reply);
-
-bool dal_i2c_engine_acquire(
- struct engine *ptr,
- struct ddc *ddc_handle);
-
-#endif
+++ /dev/null
-/*
- * Copyright 2012-15 Advanced Micro Devices, Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- * Authors: AMD
- *
- */
-
-#include "dm_services.h"
-
-/*
- * Pre-requisites: headers required by header of this unit
- */
-#include "include/i2caux_interface.h"
-#include "engine.h"
-#include "i2c_engine.h"
-#include "i2c_hw_engine.h"
-
-/*
- * Header of this unit
- */
-
-#include "i2c_generic_hw_engine.h"
-
-/*
- * Post-requisites: headers required by this unit
- */
-
-/*
- * This unit
- */
-
-/*
- * @brief
- * Cast 'struct i2c_hw_engine *'
- * to 'struct i2c_generic_hw_engine *'
- */
-#define FROM_I2C_HW_ENGINE(ptr) \
- container_of((ptr), struct i2c_generic_hw_engine, base)
-
-/*
- * @brief
- * Cast 'struct i2c_engine *'
- * to 'struct i2c_generic_hw_engine *'
- */
-#define FROM_I2C_ENGINE(ptr) \
- FROM_I2C_HW_ENGINE(container_of((ptr), struct i2c_hw_engine, base))
-
-/*
- * @brief
- * Cast 'struct engine *'
- * to 'struct i2c_generic_hw_engine *'
- */
-#define FROM_ENGINE(ptr) \
- FROM_I2C_ENGINE(container_of((ptr), struct i2c_engine, base))
-
-enum i2caux_engine_type dal_i2c_generic_hw_engine_get_engine_type(
- const struct engine *engine)
-{
- return I2CAUX_ENGINE_TYPE_I2C_GENERIC_HW;
-}
-
-/*
- * @brief
- * Single transaction handling.
- * Since transaction may be bigger than HW buffer size,
- * it divides transaction to sub-transactions
- * and uses batch transaction feature of the engine.
- */
-bool dal_i2c_generic_hw_engine_submit_request(
- struct engine *engine,
- struct i2caux_transaction_request *i2caux_request,
- bool middle_of_transaction)
-{
- struct i2c_generic_hw_engine *hw_engine = FROM_ENGINE(engine);
-
- struct i2c_hw_engine *base = &hw_engine->base;
-
- uint32_t max_payload_size =
- base->funcs->get_hw_buffer_available_size(base);
-
- bool initial_stop_bit = !middle_of_transaction;
-
- struct i2c_generic_transaction_attributes attributes;
-
- enum i2c_channel_operation_result operation_result =
- I2C_CHANNEL_OPERATION_FAILED;
-
- bool result = false;
-
- /* setup transaction initial properties */
-
- uint8_t address = i2caux_request->payload.address;
- uint8_t *current_payload = i2caux_request->payload.data;
- uint32_t remaining_payload_size = i2caux_request->payload.length;
-
- bool first_iteration = true;
-
- if (i2caux_request->operation == I2CAUX_TRANSACTION_READ)
- attributes.action = I2CAUX_TRANSACTION_ACTION_I2C_READ;
- else if (i2caux_request->operation == I2CAUX_TRANSACTION_WRITE)
- attributes.action = I2CAUX_TRANSACTION_ACTION_I2C_WRITE;
- else {
- i2caux_request->status =
- I2CAUX_TRANSACTION_STATUS_FAILED_INVALID_OPERATION;
- return false;
- }
-
- /* Do batch transaction.
- * Divide read/write data into payloads which fit HW buffer size.
- * 1. Single transaction:
- * start_bit = 1, stop_bit depends on session state, ack_on_read = 0;
- * 2. Start of batch transaction:
- * start_bit = 1, stop_bit = 0, ack_on_read = 1;
- * 3. Middle of batch transaction:
- * start_bit = 0, stop_bit = 0, ack_on_read = 1;
- * 4. End of batch transaction:
- * start_bit = 0, stop_bit depends on session state, ack_on_read = 0.
- * Session stop bit is set if 'middle_of_transaction' = 0. */
-
- while (remaining_payload_size) {
- uint32_t current_transaction_size;
- uint32_t current_payload_size;
-
- bool last_iteration;
- bool stop_bit;
-
- /* Calculate current transaction size and payload size.
- * Transaction size = total number of bytes in transaction,
- * including slave's address;
- * Payload size = number of data bytes in transaction. */
-
- if (first_iteration) {
- /* In the first sub-transaction we send slave's address
- * thus we need to reserve one byte for it */
- current_transaction_size =
- (remaining_payload_size > max_payload_size - 1) ?
- max_payload_size :
- remaining_payload_size + 1;
-
- current_payload_size = current_transaction_size - 1;
- } else {
- /* Second and further sub-transactions will have
- * entire buffer reserved for data */
- current_transaction_size =
- (remaining_payload_size > max_payload_size) ?
- max_payload_size :
- remaining_payload_size;
-
- current_payload_size = current_transaction_size;
- }
-
- last_iteration =
- (remaining_payload_size == current_payload_size);
-
- stop_bit = last_iteration ? initial_stop_bit : false;
-
- /* write slave device address */
-
- if (first_iteration)
- hw_engine->funcs->write_address(hw_engine, address);
-
- /* write current portion of data, if requested */
-
- if (i2caux_request->operation == I2CAUX_TRANSACTION_WRITE)
- hw_engine->funcs->write_data(
- hw_engine,
- current_payload,
- current_payload_size);
-
- /* execute transaction */
-
- attributes.start_bit = first_iteration;
- attributes.stop_bit = stop_bit;
- attributes.last_read = last_iteration;
- attributes.transaction_size = current_transaction_size;
-
- hw_engine->funcs->execute_transaction(hw_engine, &attributes);
-
- /* wait until transaction is processed; if it fails - quit */
-
- operation_result = base->funcs->wait_on_operation_result(
- base,
- base->funcs->get_transaction_timeout(
- base, current_transaction_size),
- I2C_CHANNEL_OPERATION_ENGINE_BUSY);
-
- if (operation_result != I2C_CHANNEL_OPERATION_SUCCEEDED)
- break;
-
- /* read current portion of data, if requested */
-
- /* the read offset should be 1 for first sub-transaction,
- * and 0 for any next one */
-
- if (i2caux_request->operation == I2CAUX_TRANSACTION_READ)
- hw_engine->funcs->read_data(hw_engine, current_payload,
- current_payload_size, first_iteration ? 1 : 0);
-
- /* update loop variables */
-
- first_iteration = false;
- current_payload += current_payload_size;
- remaining_payload_size -= current_payload_size;
- }
-
- /* update transaction status */
-
- switch (operation_result) {
- case I2C_CHANNEL_OPERATION_SUCCEEDED:
- i2caux_request->status =
- I2CAUX_TRANSACTION_STATUS_SUCCEEDED;
- result = true;
- break;
- case I2C_CHANNEL_OPERATION_NO_RESPONSE:
- i2caux_request->status =
- I2CAUX_TRANSACTION_STATUS_FAILED_NACK;
- break;
- case I2C_CHANNEL_OPERATION_TIMEOUT:
- i2caux_request->status =
- I2CAUX_TRANSACTION_STATUS_FAILED_TIMEOUT;
- break;
- case I2C_CHANNEL_OPERATION_FAILED:
- i2caux_request->status =
- I2CAUX_TRANSACTION_STATUS_FAILED_INCOMPLETE;
- break;
- default:
- i2caux_request->status =
- I2CAUX_TRANSACTION_STATUS_FAILED_OPERATION;
- }
-
- return result;
-}
-
-/*
- * @brief
- * Returns number of microseconds to wait until timeout to be considered
- */
-uint32_t dal_i2c_generic_hw_engine_get_transaction_timeout(
- const struct i2c_hw_engine *engine,
- uint32_t length)
-{
- const struct i2c_engine *base = &engine->base;
-
- uint32_t speed = base->funcs->get_speed(base);
-
- if (!speed)
- return 0;
-
- /* total timeout = period_timeout * (start + data bits count + stop) */
-
- return ((1000 * TRANSACTION_TIMEOUT_IN_I2C_CLOCKS) / speed) *
- (1 + (length << 3) + 1);
-}
-
-void dal_i2c_generic_hw_engine_construct(
- struct i2c_generic_hw_engine *engine,
- struct dc_context *ctx)
-{
- dal_i2c_hw_engine_construct(&engine->base, ctx);
-}
-
-void dal_i2c_generic_hw_engine_destruct(
- struct i2c_generic_hw_engine *engine)
-{
- dal_i2c_hw_engine_destruct(&engine->base);
-}
+++ /dev/null
-/*
- * Copyright 2012-15 Advanced Micro Devices, Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- * Authors: AMD
- *
- */
-
-#ifndef __DAL_I2C_GENERIC_HW_ENGINE_H__
-#define __DAL_I2C_GENERIC_HW_ENGINE_H__
-
-struct i2c_generic_transaction_attributes {
- enum i2caux_transaction_action action;
- uint32_t transaction_size;
- bool start_bit;
- bool stop_bit;
- bool last_read;
-};
-
-struct i2c_generic_hw_engine;
-
-struct i2c_generic_hw_engine_funcs {
- void (*write_address)(
- struct i2c_generic_hw_engine *engine,
- uint8_t address);
- void (*write_data)(
- struct i2c_generic_hw_engine *engine,
- const uint8_t *buffer,
- uint32_t length);
- void (*read_data)(
- struct i2c_generic_hw_engine *engine,
- uint8_t *buffer,
- uint32_t length,
- uint32_t offset);
- void (*execute_transaction)(
- struct i2c_generic_hw_engine *engine,
- struct i2c_generic_transaction_attributes *attributes);
-};
-
-struct i2c_generic_hw_engine {
- struct i2c_hw_engine base;
- const struct i2c_generic_hw_engine_funcs *funcs;
-};
-
-void dal_i2c_generic_hw_engine_construct(
- struct i2c_generic_hw_engine *engine,
- struct dc_context *ctx);
-
-void dal_i2c_generic_hw_engine_destruct(
- struct i2c_generic_hw_engine *engine);
-enum i2caux_engine_type dal_i2c_generic_hw_engine_get_engine_type(
- const struct engine *engine);
-bool dal_i2c_generic_hw_engine_submit_request(
- struct engine *ptr,
- struct i2caux_transaction_request *i2caux_request,
- bool middle_of_transaction);
-uint32_t dal_i2c_generic_hw_engine_get_transaction_timeout(
- const struct i2c_hw_engine *engine,
- uint32_t length);
-#endif
+++ /dev/null
-/*
- * Copyright 2012-15 Advanced Micro Devices, Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- * Authors: AMD
- *
- */
-
-#include "dm_services.h"
-#include "dm_event_log.h"
-
-/*
- * Pre-requisites: headers required by header of this unit
- */
-#include "include/i2caux_interface.h"
-#include "engine.h"
-#include "i2c_engine.h"
-
-/*
- * Header of this unit
- */
-
-#include "i2c_hw_engine.h"
-
-/*
- * Post-requisites: headers required by this unit
- */
-
-/*
- * This unit
- */
-
-/*
- * @brief
- * Cast 'struct i2c_engine *'
- * to 'struct i2c_hw_engine *'
- */
-#define FROM_I2C_ENGINE(ptr) \
- container_of((ptr), struct i2c_hw_engine, base)
-
-/*
- * @brief
- * Cast 'struct engine *'
- * to 'struct i2c_hw_engine *'
- */
-#define FROM_ENGINE(ptr) \
- FROM_I2C_ENGINE(container_of((ptr), struct i2c_engine, base))
-
-enum i2caux_engine_type dal_i2c_hw_engine_get_engine_type(
- const struct engine *engine)
-{
- return I2CAUX_ENGINE_TYPE_I2C_DDC_HW;
-}
-
-bool dal_i2c_hw_engine_submit_request(
- struct engine *engine,
- struct i2caux_transaction_request *i2caux_request,
- bool middle_of_transaction)
-{
- struct i2c_hw_engine *hw_engine = FROM_ENGINE(engine);
-
- struct i2c_request_transaction_data request;
-
- uint32_t transaction_timeout;
-
- enum i2c_channel_operation_result operation_result;
-
- bool result = false;
-
- /* We need following:
- * transaction length will not exceed
- * the number of free bytes in HW buffer (minus one for address)*/
-
- if (i2caux_request->payload.length >=
- hw_engine->funcs->get_hw_buffer_available_size(hw_engine)) {
- i2caux_request->status =
- I2CAUX_TRANSACTION_STATUS_FAILED_BUFFER_OVERFLOW;
- return false;
- }
-
- if (i2caux_request->operation == I2CAUX_TRANSACTION_READ)
- request.action = middle_of_transaction ?
- I2CAUX_TRANSACTION_ACTION_I2C_READ_MOT :
- I2CAUX_TRANSACTION_ACTION_I2C_READ;
- else if (i2caux_request->operation == I2CAUX_TRANSACTION_WRITE)
- request.action = middle_of_transaction ?
- I2CAUX_TRANSACTION_ACTION_I2C_WRITE_MOT :
- I2CAUX_TRANSACTION_ACTION_I2C_WRITE;
- else {
- i2caux_request->status =
- I2CAUX_TRANSACTION_STATUS_FAILED_INVALID_OPERATION;
- /* [anaumov] in DAL2, there was no "return false" */
- return false;
- }
-
- request.address = (uint8_t)i2caux_request->payload.address;
- request.length = i2caux_request->payload.length;
- request.data = i2caux_request->payload.data;
-
- /* obtain timeout value before submitting request */
-
- transaction_timeout = hw_engine->funcs->get_transaction_timeout(
- hw_engine, i2caux_request->payload.length + 1);
-
- hw_engine->base.funcs->submit_channel_request(
- &hw_engine->base, &request);
- /* EVENT_LOG_AUX_REQ(engine->ddc->pin_data->en, EVENT_LOG_AUX_ORIGIN_I2C, */
- /* request.action, request.address, request.length, request.data); */
-
- if ((request.status == I2C_CHANNEL_OPERATION_FAILED) ||
- (request.status == I2C_CHANNEL_OPERATION_ENGINE_BUSY)) {
- i2caux_request->status =
- I2CAUX_TRANSACTION_STATUS_FAILED_CHANNEL_BUSY;
- return false;
- }
-
- /* wait until transaction proceed */
-
- operation_result = hw_engine->funcs->wait_on_operation_result(
- hw_engine,
- transaction_timeout,
- I2C_CHANNEL_OPERATION_ENGINE_BUSY);
-
- /* update transaction status */
-
- switch (operation_result) {
- case I2C_CHANNEL_OPERATION_SUCCEEDED:
- i2caux_request->status =
- I2CAUX_TRANSACTION_STATUS_SUCCEEDED;
- result = true;
- break;
- case I2C_CHANNEL_OPERATION_NO_RESPONSE:
- i2caux_request->status =
- I2CAUX_TRANSACTION_STATUS_FAILED_NACK;
- break;
- case I2C_CHANNEL_OPERATION_TIMEOUT:
- i2caux_request->status =
- I2CAUX_TRANSACTION_STATUS_FAILED_TIMEOUT;
- break;
- case I2C_CHANNEL_OPERATION_FAILED:
- i2caux_request->status =
- I2CAUX_TRANSACTION_STATUS_FAILED_INCOMPLETE;
- break;
- default:
- i2caux_request->status =
- I2CAUX_TRANSACTION_STATUS_FAILED_OPERATION;
- }
-
- if (result && (i2caux_request->operation == I2CAUX_TRANSACTION_READ)) {
- struct i2c_reply_transaction_data reply;
-
- reply.data = i2caux_request->payload.data;
- reply.length = i2caux_request->payload.length;
-
- hw_engine->base.funcs->
- process_channel_reply(&hw_engine->base, &reply);
- /* EVENT_LOG_AUX_REP(engine->ddc->pin_data->en, EVENT_LOG_AUX_ORIGIN_I2C, */
- /* AUX_TRANSACTION_REPLY_I2C_ACK, reply.length, reply.data); */
- }
-
-
-
- return result;
-}
-
-bool dal_i2c_hw_engine_acquire_engine(
- struct i2c_engine *engine,
- struct ddc *ddc)
-{
- enum gpio_result result;
- uint32_t current_speed;
-
- result = dal_ddc_open(ddc, GPIO_MODE_HARDWARE,
- GPIO_DDC_CONFIG_TYPE_MODE_I2C);
-
- if (result != GPIO_RESULT_OK)
- return false;
-
- engine->base.ddc = ddc;
-
- current_speed = engine->funcs->get_speed(engine);
-
- if (current_speed)
- FROM_I2C_ENGINE(engine)->original_speed = current_speed;
-
- return true;
-}
-/*
- * @brief
- * Queries in a loop for current engine status
- * until retrieved status matches 'expected_result', or timeout occurs.
- * Timeout given in microseconds
- * and the status query frequency is also one per microsecond.
- */
-enum i2c_channel_operation_result dal_i2c_hw_engine_wait_on_operation_result(
- struct i2c_hw_engine *engine,
- uint32_t timeout,
- enum i2c_channel_operation_result expected_result)
-{
- enum i2c_channel_operation_result result;
- uint32_t i = 0;
-
- if (!timeout)
- return I2C_CHANNEL_OPERATION_SUCCEEDED;
-
- do {
- result = engine->base.funcs->get_channel_status(
- &engine->base, NULL);
-
- if (result != expected_result)
- break;
-
- udelay(1);
-
- ++i;
- } while (i < timeout);
-
- return result;
-}
-
-void dal_i2c_hw_engine_construct(
- struct i2c_hw_engine *engine,
- struct dc_context *ctx)
-{
- dal_i2c_engine_construct(&engine->base, ctx);
- engine->original_speed = I2CAUX_DEFAULT_I2C_HW_SPEED;
- engine->default_speed = I2CAUX_DEFAULT_I2C_HW_SPEED;
-}
-
-void dal_i2c_hw_engine_destruct(
- struct i2c_hw_engine *engine)
-{
- dal_i2c_engine_destruct(&engine->base);
-}
+++ /dev/null
-/*
- * Copyright 2012-15 Advanced Micro Devices, Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- * Authors: AMD
- *
- */
-
-#ifndef __DAL_I2C_HW_ENGINE_H__
-#define __DAL_I2C_HW_ENGINE_H__
-
-enum {
- TRANSACTION_TIMEOUT_IN_I2C_CLOCKS = 32
-};
-
-struct i2c_hw_engine;
-
-struct i2c_hw_engine_funcs {
- uint32_t (*get_hw_buffer_available_size)(
- const struct i2c_hw_engine *engine);
- enum i2c_channel_operation_result (*wait_on_operation_result)(
- struct i2c_hw_engine *engine,
- uint32_t timeout,
- enum i2c_channel_operation_result expected_result);
- uint32_t (*get_transaction_timeout)(
- const struct i2c_hw_engine *engine,
- uint32_t length);
-};
-
-struct i2c_hw_engine {
- struct i2c_engine base;
- const struct i2c_hw_engine_funcs *funcs;
-
- /* Values below are in kilohertz */
- uint32_t original_speed;
- uint32_t default_speed;
-};
-
-void dal_i2c_hw_engine_construct(
- struct i2c_hw_engine *engine,
- struct dc_context *ctx);
-
-void dal_i2c_hw_engine_destruct(
- struct i2c_hw_engine *engine);
-
-enum i2c_channel_operation_result dal_i2c_hw_engine_wait_on_operation_result(
- struct i2c_hw_engine *engine,
- uint32_t timeout,
- enum i2c_channel_operation_result expected_result);
-
-bool dal_i2c_hw_engine_acquire_engine(
- struct i2c_engine *engine,
- struct ddc *ddc);
-
-bool dal_i2c_hw_engine_submit_request(
- struct engine *ptr,
- struct i2caux_transaction_request *i2caux_request,
- bool middle_of_transaction);
-
-enum i2caux_engine_type dal_i2c_hw_engine_get_engine_type(
- const struct engine *engine);
-
-#endif
+++ /dev/null
-/*
- * Copyright 2012-15 Advanced Micro Devices, Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- * Authors: AMD
- *
- */
-
-#include "dm_services.h"
-
-/*
- * Pre-requisites: headers required by header of this unit
- */
-#include "include/i2caux_interface.h"
-#include "engine.h"
-#include "i2c_engine.h"
-
-/*
- * Header of this unit
- */
-
-#include "i2c_sw_engine.h"
-
-/*
- * Post-requisites: headers required by this unit
- */
-
-/*
- * This unit
- */
-
-#define SCL false
-#define SDA true
-
-static inline bool read_bit_from_ddc(
- struct ddc *ddc,
- bool data_nor_clock)
-{
- uint32_t value = 0;
-
- if (data_nor_clock)
- dal_gpio_get_value(ddc->pin_data, &value);
- else
- dal_gpio_get_value(ddc->pin_clock, &value);
-
- return (value != 0);
-}
-
-static inline void write_bit_to_ddc(
- struct ddc *ddc,
- bool data_nor_clock,
- bool bit)
-{
- uint32_t value = bit ? 1 : 0;
-
- if (data_nor_clock)
- dal_gpio_set_value(ddc->pin_data, value);
- else
- dal_gpio_set_value(ddc->pin_clock, value);
-}
-
-static bool wait_for_scl_high(
- struct dc_context *ctx,
- struct ddc *ddc,
- uint16_t clock_delay_div_4)
-{
- uint32_t scl_retry = 0;
- uint32_t scl_retry_max = I2C_SW_TIMEOUT_DELAY / clock_delay_div_4;
-
- udelay(clock_delay_div_4);
-
- /* 3 milliseconds delay
- * to wake up some displays from "low power" state.
- */
-
- do {
- if (read_bit_from_ddc(ddc, SCL))
- return true;
-
- udelay(clock_delay_div_4);
-
- ++scl_retry;
- } while (scl_retry <= scl_retry_max);
-
- return false;
-}
-
-static bool start_sync(
- struct dc_context *ctx,
- struct ddc *ddc_handle,
- uint16_t clock_delay_div_4)
-{
- uint32_t retry = 0;
-
- /* The I2C communications start signal is:
- * the SDA going low from high, while the SCL is high. */
-
- write_bit_to_ddc(ddc_handle, SCL, true);
-
- udelay(clock_delay_div_4);
-
- do {
- write_bit_to_ddc(ddc_handle, SDA, true);
-
- if (!read_bit_from_ddc(ddc_handle, SDA)) {
- ++retry;
- continue;
- }
-
- udelay(clock_delay_div_4);
-
- write_bit_to_ddc(ddc_handle, SCL, true);
-
- if (!wait_for_scl_high(ctx, ddc_handle, clock_delay_div_4))
- break;
-
- write_bit_to_ddc(ddc_handle, SDA, false);
-
- udelay(clock_delay_div_4);
-
- write_bit_to_ddc(ddc_handle, SCL, false);
-
- udelay(clock_delay_div_4);
-
- return true;
- } while (retry <= I2C_SW_RETRIES);
-
- return false;
-}
-
-static bool stop_sync(
- struct dc_context *ctx,
- struct ddc *ddc_handle,
- uint16_t clock_delay_div_4)
-{
- uint32_t retry = 0;
-
- /* The I2C communications stop signal is:
- * the SDA going high from low, while the SCL is high. */
-
- write_bit_to_ddc(ddc_handle, SCL, false);
-
- udelay(clock_delay_div_4);
-
- write_bit_to_ddc(ddc_handle, SDA, false);
-
- udelay(clock_delay_div_4);
-
- write_bit_to_ddc(ddc_handle, SCL, true);
-
- if (!wait_for_scl_high(ctx, ddc_handle, clock_delay_div_4))
- return false;
-
- write_bit_to_ddc(ddc_handle, SDA, true);
-
- do {
- udelay(clock_delay_div_4);
-
- if (read_bit_from_ddc(ddc_handle, SDA))
- return true;
-
- ++retry;
- } while (retry <= 2);
-
- return false;
-}
-
-static bool write_byte(
- struct dc_context *ctx,
- struct ddc *ddc_handle,
- uint16_t clock_delay_div_4,
- uint8_t byte)
-{
- int32_t shift = 7;
- bool ack;
-
- /* bits are transmitted serially, starting from MSB */
-
- do {
- udelay(clock_delay_div_4);
-
- write_bit_to_ddc(ddc_handle, SDA, (byte >> shift) & 1);
-
- udelay(clock_delay_div_4);
-
- write_bit_to_ddc(ddc_handle, SCL, true);
-
- if (!wait_for_scl_high(ctx, ddc_handle, clock_delay_div_4))
- return false;
-
- write_bit_to_ddc(ddc_handle, SCL, false);
-
- --shift;
- } while (shift >= 0);
-
- /* The display sends ACK by preventing the SDA from going high
- * after the SCL pulse we use to send our last data bit.
- * If the SDA goes high after that bit, it's a NACK */
-
- udelay(clock_delay_div_4);
-
- write_bit_to_ddc(ddc_handle, SDA, true);
-
- udelay(clock_delay_div_4);
-
- write_bit_to_ddc(ddc_handle, SCL, true);
-
- if (!wait_for_scl_high(ctx, ddc_handle, clock_delay_div_4))
- return false;
-
- /* read ACK bit */
-
- ack = !read_bit_from_ddc(ddc_handle, SDA);
-
- udelay(clock_delay_div_4 << 1);
-
- write_bit_to_ddc(ddc_handle, SCL, false);
-
- udelay(clock_delay_div_4 << 1);
-
- return ack;
-}
-
-static bool read_byte(
- struct dc_context *ctx,
- struct ddc *ddc_handle,
- uint16_t clock_delay_div_4,
- uint8_t *byte,
- bool more)
-{
- int32_t shift = 7;
-
- uint8_t data = 0;
-
- /* The data bits are read from MSB to LSB;
- * bit is read while SCL is high */
-
- do {
- write_bit_to_ddc(ddc_handle, SCL, true);
-
- if (!wait_for_scl_high(ctx, ddc_handle, clock_delay_div_4))
- return false;
-
- if (read_bit_from_ddc(ddc_handle, SDA))
- data |= (1 << shift);
-
- write_bit_to_ddc(ddc_handle, SCL, false);
-
- udelay(clock_delay_div_4 << 1);
-
- --shift;
- } while (shift >= 0);
-
- /* read only whole byte */
-
- *byte = data;
-
- udelay(clock_delay_div_4);
-
- /* send the acknowledge bit:
- * SDA low means ACK, SDA high means NACK */
-
- write_bit_to_ddc(ddc_handle, SDA, !more);
-
- udelay(clock_delay_div_4);
-
- write_bit_to_ddc(ddc_handle, SCL, true);
-
- if (!wait_for_scl_high(ctx, ddc_handle, clock_delay_div_4))
- return false;
-
- write_bit_to_ddc(ddc_handle, SCL, false);
-
- udelay(clock_delay_div_4);
-
- write_bit_to_ddc(ddc_handle, SDA, true);
-
- udelay(clock_delay_div_4);
-
- return true;
-}
-
-static bool i2c_write(
- struct dc_context *ctx,
- struct ddc *ddc_handle,
- uint16_t clock_delay_div_4,
- uint8_t address,
- uint32_t length,
- const uint8_t *data)
-{
- uint32_t i = 0;
-
- if (!write_byte(ctx, ddc_handle, clock_delay_div_4, address))
- return false;
-
- while (i < length) {
- if (!write_byte(ctx, ddc_handle, clock_delay_div_4, data[i]))
- return false;
- ++i;
- }
-
- return true;
-}
-
-static bool i2c_read(
- struct dc_context *ctx,
- struct ddc *ddc_handle,
- uint16_t clock_delay_div_4,
- uint8_t address,
- uint32_t length,
- uint8_t *data)
-{
- uint32_t i = 0;
-
- if (!write_byte(ctx, ddc_handle, clock_delay_div_4, address))
- return false;
-
- while (i < length) {
- if (!read_byte(ctx, ddc_handle, clock_delay_div_4, data + i,
- i < length - 1))
- return false;
- ++i;
- }
-
- return true;
-}
-
-/*
- * @brief
- * Cast 'struct i2c_engine *'
- * to 'struct i2c_sw_engine *'
- */
-#define FROM_I2C_ENGINE(ptr) \
- container_of((ptr), struct i2c_sw_engine, base)
-
-/*
- * @brief
- * Cast 'struct engine *'
- * to 'struct i2c_sw_engine *'
- */
-#define FROM_ENGINE(ptr) \
- FROM_I2C_ENGINE(container_of((ptr), struct i2c_engine, base))
-
-enum i2caux_engine_type dal_i2c_sw_engine_get_engine_type(
- const struct engine *engine)
-{
- return I2CAUX_ENGINE_TYPE_I2C_SW;
-}
-
-bool dal_i2c_sw_engine_submit_request(
- struct engine *engine,
- struct i2caux_transaction_request *i2caux_request,
- bool middle_of_transaction)
-{
- struct i2c_sw_engine *sw_engine = FROM_ENGINE(engine);
-
- struct i2c_engine *base = &sw_engine->base;
-
- struct i2c_request_transaction_data request;
- bool operation_succeeded = false;
-
- if (i2caux_request->operation == I2CAUX_TRANSACTION_READ)
- request.action = middle_of_transaction ?
- I2CAUX_TRANSACTION_ACTION_I2C_READ_MOT :
- I2CAUX_TRANSACTION_ACTION_I2C_READ;
- else if (i2caux_request->operation == I2CAUX_TRANSACTION_WRITE)
- request.action = middle_of_transaction ?
- I2CAUX_TRANSACTION_ACTION_I2C_WRITE_MOT :
- I2CAUX_TRANSACTION_ACTION_I2C_WRITE;
- else {
- i2caux_request->status =
- I2CAUX_TRANSACTION_STATUS_FAILED_INVALID_OPERATION;
- /* in DAL2, there was no "return false" */
- return false;
- }
-
- request.address = (uint8_t)i2caux_request->payload.address;
- request.length = i2caux_request->payload.length;
- request.data = i2caux_request->payload.data;
-
- base->funcs->submit_channel_request(base, &request);
-
- if ((request.status == I2C_CHANNEL_OPERATION_ENGINE_BUSY) ||
- (request.status == I2C_CHANNEL_OPERATION_FAILED))
- i2caux_request->status =
- I2CAUX_TRANSACTION_STATUS_FAILED_CHANNEL_BUSY;
- else {
- enum i2c_channel_operation_result operation_result;
-
- do {
- operation_result =
- base->funcs->get_channel_status(base, NULL);
-
- switch (operation_result) {
- case I2C_CHANNEL_OPERATION_SUCCEEDED:
- i2caux_request->status =
- I2CAUX_TRANSACTION_STATUS_SUCCEEDED;
- operation_succeeded = true;
- break;
- case I2C_CHANNEL_OPERATION_NO_RESPONSE:
- i2caux_request->status =
- I2CAUX_TRANSACTION_STATUS_FAILED_NACK;
- break;
- case I2C_CHANNEL_OPERATION_TIMEOUT:
- i2caux_request->status =
- I2CAUX_TRANSACTION_STATUS_FAILED_TIMEOUT;
- break;
- case I2C_CHANNEL_OPERATION_FAILED:
- i2caux_request->status =
- I2CAUX_TRANSACTION_STATUS_FAILED_INCOMPLETE;
- break;
- default:
- i2caux_request->status =
- I2CAUX_TRANSACTION_STATUS_FAILED_OPERATION;
- break;
- }
- } while (operation_result == I2C_CHANNEL_OPERATION_ENGINE_BUSY);
- }
-
- return operation_succeeded;
-}
-
-uint32_t dal_i2c_sw_engine_get_speed(
- const struct i2c_engine *engine)
-{
- return FROM_I2C_ENGINE(engine)->speed;
-}
-
-void dal_i2c_sw_engine_set_speed(
- struct i2c_engine *engine,
- uint32_t speed)
-{
- struct i2c_sw_engine *sw_engine = FROM_I2C_ENGINE(engine);
-
- ASSERT(speed);
-
- sw_engine->speed = speed ? speed : I2CAUX_DEFAULT_I2C_SW_SPEED;
-
- sw_engine->clock_delay = 1000 / sw_engine->speed;
-
- if (sw_engine->clock_delay < 12)
- sw_engine->clock_delay = 12;
-}
-
-bool dal_i2caux_i2c_sw_engine_acquire_engine(
- struct i2c_engine *engine,
- struct ddc *ddc)
-{
- enum gpio_result result;
-
- result = dal_ddc_open(ddc, GPIO_MODE_FAST_OUTPUT,
- GPIO_DDC_CONFIG_TYPE_MODE_I2C);
-
- if (result != GPIO_RESULT_OK)
- return false;
-
- engine->base.ddc = ddc;
-
- return true;
-}
-
-void dal_i2c_sw_engine_submit_channel_request(
- struct i2c_engine *engine,
- struct i2c_request_transaction_data *req)
-{
- struct i2c_sw_engine *sw_engine = FROM_I2C_ENGINE(engine);
-
- struct ddc *ddc = engine->base.ddc;
- uint16_t clock_delay_div_4 = sw_engine->clock_delay >> 2;
-
- /* send sync (start / repeated start) */
-
- bool result = start_sync(engine->base.ctx, ddc, clock_delay_div_4);
-
- /* process payload */
-
- if (result) {
- switch (req->action) {
- case I2CAUX_TRANSACTION_ACTION_I2C_WRITE:
- case I2CAUX_TRANSACTION_ACTION_I2C_WRITE_MOT:
- result = i2c_write(engine->base.ctx, ddc, clock_delay_div_4,
- req->address, req->length, req->data);
- break;
- case I2CAUX_TRANSACTION_ACTION_I2C_READ:
- case I2CAUX_TRANSACTION_ACTION_I2C_READ_MOT:
- result = i2c_read(engine->base.ctx, ddc, clock_delay_div_4,
- req->address, req->length, req->data);
- break;
- default:
- result = false;
- break;
- }
- }
-
- /* send stop if not 'mot' or operation failed */
-
- if (!result ||
- (req->action == I2CAUX_TRANSACTION_ACTION_I2C_WRITE) ||
- (req->action == I2CAUX_TRANSACTION_ACTION_I2C_READ))
- if (!stop_sync(engine->base.ctx, ddc, clock_delay_div_4))
- result = false;
-
- req->status = result ?
- I2C_CHANNEL_OPERATION_SUCCEEDED :
- I2C_CHANNEL_OPERATION_FAILED;
-}
-
-enum i2c_channel_operation_result dal_i2c_sw_engine_get_channel_status(
- struct i2c_engine *engine,
- uint8_t *returned_bytes)
-{
- /* No arbitration with VBIOS is performed since DCE 6.0 */
- return I2C_CHANNEL_OPERATION_SUCCEEDED;
-}
-
-void dal_i2c_sw_engine_destruct(
- struct i2c_sw_engine *engine)
-{
- dal_i2c_engine_destruct(&engine->base);
-}
-
-static void destroy(
- struct i2c_engine **ptr)
-{
- dal_i2c_sw_engine_destruct(FROM_I2C_ENGINE(*ptr));
-
- kfree(*ptr);
- *ptr = NULL;
-}
-
-static const struct i2c_engine_funcs i2c_engine_funcs = {
- .acquire_engine = dal_i2caux_i2c_sw_engine_acquire_engine,
- .destroy = destroy,
- .get_speed = dal_i2c_sw_engine_get_speed,
- .set_speed = dal_i2c_sw_engine_set_speed,
- .setup_engine = dal_i2c_engine_setup_i2c_engine,
- .submit_channel_request = dal_i2c_sw_engine_submit_channel_request,
- .process_channel_reply = dal_i2c_engine_process_channel_reply,
- .get_channel_status = dal_i2c_sw_engine_get_channel_status,
-};
-
-static void release_engine(
- struct engine *engine)
-{
-
-}
-
-static const struct engine_funcs engine_funcs = {
- .release_engine = release_engine,
- .get_engine_type = dal_i2c_sw_engine_get_engine_type,
- .acquire = dal_i2c_engine_acquire,
- .submit_request = dal_i2c_sw_engine_submit_request,
-};
-
-void dal_i2c_sw_engine_construct(
- struct i2c_sw_engine *engine,
- const struct i2c_sw_engine_create_arg *arg)
-{
- dal_i2c_engine_construct(&engine->base, arg->ctx);
- dal_i2c_sw_engine_set_speed(&engine->base, arg->default_speed);
- engine->base.funcs = &i2c_engine_funcs;
- engine->base.base.funcs = &engine_funcs;
-}
-
-struct i2c_engine *dal_i2c_sw_engine_create(
- const struct i2c_sw_engine_create_arg *arg)
-{
- struct i2c_sw_engine *engine;
-
- if (!arg) {
- BREAK_TO_DEBUGGER();
- return NULL;
- }
-
- engine = kzalloc(sizeof(struct i2c_sw_engine), GFP_KERNEL);
-
- if (!engine) {
- BREAK_TO_DEBUGGER();
- return NULL;
- }
-
- dal_i2c_sw_engine_construct(engine, arg);
- return &engine->base;
-}
+++ /dev/null
-/*
- * Copyright 2012-15 Advanced Micro Devices, Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- * Authors: AMD
- *
- */
-
-#ifndef __DAL_I2C_SW_ENGINE_H__
-#define __DAL_I2C_SW_ENGINE_H__
-
-enum {
- I2C_SW_RETRIES = 10,
- I2C_SW_SCL_READ_RETRIES = 128,
- /* following value is in microseconds */
- I2C_SW_TIMEOUT_DELAY = 3000
-};
-
-struct i2c_sw_engine;
-
-struct i2c_sw_engine {
- struct i2c_engine base;
- uint32_t clock_delay;
- /* Values below are in KHz */
- uint32_t speed;
- uint32_t default_speed;
-};
-
-struct i2c_sw_engine_create_arg {
- uint32_t default_speed;
- struct dc_context *ctx;
-};
-
-void dal_i2c_sw_engine_construct(
- struct i2c_sw_engine *engine,
- const struct i2c_sw_engine_create_arg *arg);
-
-bool dal_i2caux_i2c_sw_engine_acquire_engine(
- struct i2c_engine *engine,
- struct ddc *ddc_handle);
-
-void dal_i2c_sw_engine_destruct(
- struct i2c_sw_engine *engine);
-
-struct i2c_engine *dal_i2c_sw_engine_create(
- const struct i2c_sw_engine_create_arg *arg);
-enum i2caux_engine_type dal_i2c_sw_engine_get_engine_type(
- const struct engine *engine);
-bool dal_i2c_sw_engine_submit_request(
- struct engine *ptr,
- struct i2caux_transaction_request *i2caux_request,
- bool middle_of_transaction);
-uint32_t dal_i2c_sw_engine_get_speed(
- const struct i2c_engine *engine);
-void dal_i2c_sw_engine_set_speed(
- struct i2c_engine *ptr,
- uint32_t speed);
-void dal_i2c_sw_engine_submit_channel_request(
- struct i2c_engine *ptr,
- struct i2c_request_transaction_data *req);
-enum i2c_channel_operation_result dal_i2c_sw_engine_get_channel_status(
- struct i2c_engine *engine,
- uint8_t *returned_bytes);
-#endif
+++ /dev/null
-/*
- * Copyright 2012-15 Advanced Micro Devices, Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- * Authors: AMD
- *
- */
-
-#ifndef __DAL_I2C_AUX_H__
-#define __DAL_I2C_AUX_H__
-
-uint32_t dal_i2caux_get_reference_clock(
- struct dc_bios *bios);
-
-struct i2caux;
-
-struct engine;
-
-struct i2caux_funcs {
- void (*destroy)(struct i2caux **ptr);
- struct i2c_engine * (*acquire_i2c_sw_engine)(
- struct i2caux *i2caux,
- struct ddc *ddc);
- struct i2c_engine * (*acquire_i2c_hw_engine)(
- struct i2caux *i2caux,
- struct ddc *ddc);
- struct aux_engine * (*acquire_aux_engine)(
- struct i2caux *i2caux,
- struct ddc *ddc);
- void (*release_engine)(
- struct i2caux *i2caux,
- struct engine *engine);
-};
-
-struct i2c_engine;
-struct aux_engine;
-
-struct i2caux {
- struct dc_context *ctx;
- const struct i2caux_funcs *funcs;
- /* On ASIC we have certain amount of lines with HW DDC engine
- * (4, 6, or maybe more in the future).
- * For every such line, we create separate HW DDC engine
- * (since we have these engines in HW) and separate SW DDC engine
- * (to allow concurrent use of few lines).
- * In similar way we have AUX engines. */
-
- /* I2C SW engines, per DDC line.
- * Only lines with HW DDC support will be initialized */
- struct i2c_engine *i2c_sw_engines[GPIO_DDC_LINE_COUNT];
-
- /* I2C HW engines, per DDC line.
- * Only lines with HW DDC support will be initialized */
- struct i2c_engine *i2c_hw_engines[GPIO_DDC_LINE_COUNT];
-
- /* AUX engines, per DDC line.
- * Only lines with HW AUX support will be initialized */
- struct aux_engine *aux_engines[GPIO_DDC_LINE_COUNT];
-
- /* For all other lines, we can use
- * single instance of generic I2C HW engine
- * (since in HW, there is single instance of it)
- * or single instance of generic I2C SW engine.
- * AUX is not supported for other lines. */
-
- /* General-purpose I2C SW engine.
- * Can be assigned dynamically to any line per transaction */
- struct i2c_engine *i2c_generic_sw_engine;
-
- /* General-purpose I2C generic HW engine.
- * Can be assigned dynamically to almost any line per transaction */
- struct i2c_engine *i2c_generic_hw_engine;
-
- /* [anaumov] in DAL2, there is a Mutex */
-
- uint32_t aux_timeout_period;
-
- /* expressed in KHz */
- uint32_t default_i2c_sw_speed;
- uint32_t default_i2c_hw_speed;
-};
-
-void dal_i2caux_construct(
- struct i2caux *i2caux,
- struct dc_context *ctx);
-
-void dal_i2caux_release_engine(
- struct i2caux *i2caux,
- struct engine *engine);
-
-void dal_i2caux_destruct(
- struct i2caux *i2caux);
-
-void dal_i2caux_destroy(
- struct i2caux **ptr);
-
-struct i2c_engine *dal_i2caux_acquire_i2c_sw_engine(
- struct i2caux *i2caux,
- struct ddc *ddc);
-
-struct aux_engine *dal_i2caux_acquire_aux_engine(
- struct i2caux *i2caux,
- struct ddc *ddc);
-
-#endif
uint32_t raw;
};
-struct i2caux;
-
-struct i2caux *dal_i2caux_create(
- struct dc_context *ctx);
-
-bool dal_i2caux_submit_i2c_command(
- struct i2caux *i2caux,
- struct ddc *ddc,
- struct i2c_command *cmd);
-
-bool dal_i2caux_submit_aux_command(
- struct i2caux *i2caux,
- struct ddc *ddc,
- struct aux_command *cmd);
-
-void dal_i2caux_configure_aux(
- struct i2caux *i2caux,
- struct ddc *ddc,
- union aux_config cfg);
-
-void dal_i2caux_destroy(
- struct i2caux **ptr);
-
#endif
projects / openwrt / staging / blogic.git / commitdiff