Add compile-time errors for HW_ASSISTED_COHERENCY flag

This patch fixes this issue:
https://github.com/ARM-software/tf-issues/issues/660

The introduced changes are the following:

1) Some cores implement cache coherency maintenance operation on the
hardware level. For those cores, such as - but not only - the DynamIQ
cores, it is mandatory that TF-A is compiled with the
HW_ASSISTED_COHERENCY flag. If not, the core behaviour at runtime is
unpredictable. To prevent this, compile time checks have been added and
compilation errors are generated, if needed.

2) To enable this change for FVP, a logical separation has been done for
the core libraries. A system cannot contain cores of both groups, i.e.
cores that manage coherency on hardware and cores that don't do it. As
such, depending on the HW_ASSISTED_COHERENCY flag, FVP includes the
libraries only of the relevant cores.

3) The neoverse_e1.S file has been added to the FVP sources.

Change-Id: I787d15819b2add4ec0d238249e04bf0497dc12f3
Signed-off-by: John Tsichritzis <john.tsichritzis@arm.com>

diff --git a/docs/user-guide.rst b/docs/user-guide.rst
index 01cf17a23d2824a2728517d5a69c6bc4dc9a6118..ce12f0835a3fd8b858ab79213b0501598bcdde4a 100644 (file)
--- a/docs/user-guide.rst
+++ b/docs/user-guide.rst
@@ -530,13 +530,21 @@ Common build options
 
 -  ``HW_ASSISTED_COHERENCY``: On most Arm systems to-date, platform-specific
    software operations are required for CPUs to enter and exit coherency.
-   However, there exists newer systems where CPUs' entry to and exit from
-   coherency is managed in hardware. Such systems require software to only
-   initiate the operations, and the rest is managed in hardware, minimizing
-   active software management. In such systems, this boolean option enables
-   TF-A to carry out build and run-time optimizations during boot and power
-   management operations. This option defaults to 0 and if it is enabled,
-   then it implies ``WARMBOOT_ENABLE_DCACHE_EARLY`` is also enabled.
+   However, newer systems exist where CPUs' entry to and exit from coherency
+   is managed in hardware. Such systems require software to only initiate these
+   operations, and the rest is managed in hardware, minimizing active software
+   management. In such systems, this boolean option enables TF-A to carry out
+   build and run-time optimizations during boot and power management operations.
+   This option defaults to 0 and if it is enabled, then it implies
+   ``WARMBOOT_ENABLE_DCACHE_EARLY`` is also enabled.
+
+   If this flag is disabled while the platform which TF-A is compiled for
+   includes cores that manage coherency in hardware, then a compilation error is
+   generated. This is based on the fact that a system cannot have, at the same
+   time, cores that manage coherency in hardware and cores that don't. In other
+   words, a platform cannot have, at the same time, cores that require
+   ``HW_ASSISTED_COHERENCY=1`` and cores that require
+   ``HW_ASSISTED_COHERENCY=0``.
 
    Note that, when ``HW_ASSISTED_COHERENCY`` is enabled, version 2 of
    translation library (xlat tables v2) must be used; version 1 of translation

diff --git a/lib/cpus/aarch64/cortex_a55.S b/lib/cpus/aarch64/cortex_a55.S
index b9a3f3653ebcaed489bbb8a274800b6567707e94..0ef373a0a80f4306207c6545e73589b473f2c446 100644 (file)
--- a/lib/cpus/aarch64/cortex_a55.S
+++ b/lib/cpus/aarch64/cortex_a55.S
@@ -11,6 +11,11 @@
 #include <cpu_macros.S>
 #include <plat_macros.S>
 
+/* Hardware handled coherency */
+#if HW_ASSISTED_COHERENCY == 0
+#error "Cortex-A55 must be compiled with HW_ASSISTED_COHERENCY enabled"
+#endif
+
        /* --------------------------------------------------
         * Errata Workaround for Cortex A55 Errata #768277.
         * This applies only to revision r0p0 of Cortex A55.

diff --git a/lib/cpus/aarch64/cortex_a75.S b/lib/cpus/aarch64/cortex_a75.S
index fda1aecbecb57b96bee02ddf5d3366187d91772b..657457ee14fb49b1e0185bac6cbd642be0f409b8 100644 (file)
--- a/lib/cpus/aarch64/cortex_a75.S
+++ b/lib/cpus/aarch64/cortex_a75.S
@@ -10,6 +10,11 @@
 #include <cpuamu.h>
 #include <cpu_macros.S>
 
+/* Hardware handled coherency */
+#if HW_ASSISTED_COHERENCY == 0
+#error "Cortex-A75 must be compiled with HW_ASSISTED_COHERENCY enabled"
+#endif
+
        /* --------------------------------------------------
         * Errata Workaround for Cortex A75 Errata #764081.
         * This applies only to revision r0p0 of Cortex A75.

diff --git a/lib/cpus/aarch64/cortex_a76.S b/lib/cpus/aarch64/cortex_a76.S
index 4bf6e77a9cf060895e65b06e1ad2fe4ed8de4119..6fe6afe3db6923aa740e6e8064bdbba1635b221b 100644 (file)
--- a/lib/cpus/aarch64/cortex_a76.S
+++ b/lib/cpus/aarch64/cortex_a76.S
@@ -13,6 +13,11 @@
 #include <plat_macros.S>
 #include <services/arm_arch_svc.h>
 
+/* Hardware handled coherency */
+#if HW_ASSISTED_COHERENCY == 0
+#error "Cortex-A76 must be compiled with HW_ASSISTED_COHERENCY enabled"
+#endif
+
 #define ESR_EL3_A64_SMC0       0x5e000000
 #define ESR_EL3_A32_SMC0       0x4e000000
 

diff --git a/lib/cpus/aarch64/cortex_a76ae.S b/lib/cpus/aarch64/cortex_a76ae.S
index 1ba8e9a7d4481ee8aa96e71f6eb60a752cbd358c..46e9450f29d4f2736114d251c3b193ae3a51d2b8 100644 (file)
--- a/lib/cpus/aarch64/cortex_a76ae.S
+++ b/lib/cpus/aarch64/cortex_a76ae.S
@@ -8,6 +8,11 @@
 #include <cortex_a76ae.h>
 #include <cpu_macros.S>
 
+/* Hardware handled coherency */
+#if HW_ASSISTED_COHERENCY == 0
+#error "Cortex-A76AE must be compiled with HW_ASSISTED_COHERENCY enabled"
+#endif
+
        /* ---------------------------------------------
         * HW will do the cache maintenance while powering down
         * ---------------------------------------------

diff --git a/lib/cpus/aarch64/cortex_deimos.S b/lib/cpus/aarch64/cortex_deimos.S
index 0e72fba5a1aaaccea0c3f38870e50a2e5928aa6e..e73e89f73843c7605170030d4ca23bf684ac3af0 100644 (file)
--- a/lib/cpus/aarch64/cortex_deimos.S
+++ b/lib/cpus/aarch64/cortex_deimos.S
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -11,6 +11,11 @@
 #include <cpu_macros.S>
 #include <plat_macros.S>
 
+/* Hardware handled coherency */
+#if HW_ASSISTED_COHERENCY == 0
+#error "Deimos must be compiled with HW_ASSISTED_COHERENCY enabled"
+#endif
+
        /* ---------------------------------------------
         * HW will do the cache maintenance while powering down
         * ---------------------------------------------

diff --git a/lib/cpus/aarch64/neoverse_e1.S b/lib/cpus/aarch64/neoverse_e1.S
index 8e403062fe3ef9e734cfdbeb8257469d55ec31fc..71e7b5171866abff46b181daac610ab5857b7b3f 100644 (file)
--- a/lib/cpus/aarch64/neoverse_e1.S
+++ b/lib/cpus/aarch64/neoverse_e1.S
@@ -11,6 +11,11 @@
 #include <cpu_macros.S>
 #include <plat_macros.S>
 
+/* Hardware handled coherency */
+#if HW_ASSISTED_COHERENCY == 0
+#error "Neoverse E1 must be compiled with HW_ASSISTED_COHERENCY enabled"
+#endif
+
 func neoverse_e1_cpu_pwr_dwn
        mrs     x0, NEOVERSE_E1_CPUPWRCTLR_EL1
        orr     x0, x0, #NEOVERSE_E1_CPUPWRCTLR_EL1_CORE_PWRDN_BIT

diff --git a/lib/cpus/aarch64/neoverse_n1.S b/lib/cpus/aarch64/neoverse_n1.S
index ce63899a7e50c062855bfa0edcf1b60c5fdd23e7..2038f318be586ec3ce1527308ff2ebb99dec7ce6 100644 (file)
--- a/lib/cpus/aarch64/neoverse_n1.S
+++ b/lib/cpus/aarch64/neoverse_n1.S
@@ -10,6 +10,11 @@
 #include <cpuamu.h>
 #include <cpu_macros.S>
 
+/* Hardware handled coherency */
+#if HW_ASSISTED_COHERENCY == 0
+#error "Neoverse N1 must be compiled with HW_ASSISTED_COHERENCY enabled"
+#endif
+
 /* --------------------------------------------------
  * Errata Workaround for Neoverse N1 Errata
  * This applies to revision r0p0 and r1p0 of Neoverse N1.

diff --git a/lib/cpus/aarch64/neoverse_zeus.S b/lib/cpus/aarch64/neoverse_zeus.S
index 79c8b2fdf4a5d49d2528fb1fbc77bb18dff722cd..c5241afab0529a70ea0d88e0fcc10b100c74affc 100644 (file)
--- a/lib/cpus/aarch64/neoverse_zeus.S
+++ b/lib/cpus/aarch64/neoverse_zeus.S
@@ -11,6 +11,11 @@
 #include <cpu_macros.S>
 #include <plat_macros.S>
 
+/* Hardware handled coherency */
+#if HW_ASSISTED_COHERENCY == 0
+#error "Neoverse Zeus must be compiled with HW_ASSISTED_COHERENCY enabled"
+#endif
+
        /* ---------------------------------------------
         * HW will do the cache maintenance while powering down
         * ---------------------------------------------

diff --git a/plat/arm/board/fvp/platform.mk b/plat/arm/board/fvp/platform.mk
index c11d848ea011b16f48411435eb74e5dde0a2b350..9b128a564174aa28aced81bfa412c66842e7773a 100644 (file)
--- a/plat/arm/board/fvp/platform.mk
+++ b/plat/arm/board/fvp/platform.mk
@@ -95,18 +95,25 @@ PLAT_BL_COMMON_SOURCES      :=      plat/arm/board/fvp/fvp_common.c
 FVP_CPU_LIBS           :=      lib/cpus/${ARCH}/aem_generic.S
 
 ifeq (${ARCH}, aarch64)
-FVP_CPU_LIBS           +=      lib/cpus/aarch64/cortex_a35.S                   \
+
+# select a different set of CPU files, depending on whether we compile with
+# hardware assisted coherency configurations or not
+ifeq (${HW_ASSISTED_COHERENCY}, 0)
+       FVP_CPU_LIBS    +=      lib/cpus/aarch64/cortex_a35.S                   \
                                lib/cpus/aarch64/cortex_a53.S                   \
-                               lib/cpus/aarch64/cortex_a55.S                   \
                                lib/cpus/aarch64/cortex_a57.S                   \
                                lib/cpus/aarch64/cortex_a72.S                   \
-                               lib/cpus/aarch64/cortex_a73.S                   \
+                               lib/cpus/aarch64/cortex_a73.S
+else
+       FVP_CPU_LIBS    +=      lib/cpus/aarch64/cortex_a55.S                   \
                                lib/cpus/aarch64/cortex_a75.S                   \
                                lib/cpus/aarch64/cortex_a76.S                   \
                                lib/cpus/aarch64/cortex_a76ae.S                 \
                                lib/cpus/aarch64/neoverse_n1.S                  \
+                               lib/cpus/aarch64/neoverse_e1.S                  \
                                lib/cpus/aarch64/cortex_deimos.S                \
                                lib/cpus/aarch64/neoverse_zeus.S
+endif
 
 else
 FVP_CPU_LIBS           +=      lib/cpus/aarch32/cortex_a32.S
@@ -217,10 +224,13 @@ ENABLE_PIE                :=      1
 endif
 
 ifeq (${ENABLE_AMU},1)
-BL31_SOURCES           +=      lib/cpus/aarch64/cortex_a75_pubsub.c    \
-                               lib/cpus/aarch64/neoverse_n1_pubsub.c   \
-                               lib/cpus/aarch64/cpuamu.c               \
+BL31_SOURCES           +=      lib/cpus/aarch64/cpuamu.c               \
                                lib/cpus/aarch64/cpuamu_helpers.S
+
+ifeq (${HW_ASSISTED_COHERENCY}, 1)
+BL31_SOURCES           +=      lib/cpus/aarch64/cortex_a75_pubsub.c    \
+                               lib/cpus/aarch64/neoverse_n1_pubsub.c
+endif
 endif
 
 ifeq (${RAS_EXTENSION},1)