drm/nouveau/fifo/gk104: fix chid bit mask

Fix the channel id bit mask in FIFO schedule timeout error handling.

FIFO_ENGINE_STATUS_NEXT_ID is bit 27:16 thus 0x0fff0000.
FIFO_ENGINE_STATUS_ID      is bit 11:0  thus 0x00000fff.

Signed-off-by: Xia Yang <xiay@nvidia.com>
Reviewed-by: Alexandre Courbot <acourbot@nvidia.com>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>

diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk104.c b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk104.c
index 4fcd147d43c83d26132fb454d465bc4f282139b5..d6a88cf67416c46aa7e72332dfc87158edc70e52 100644 (file)
--- a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk104.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk104.c
@@ -198,11 +198,11 @@ gk104_fifo_intr_sched_ctxsw(struct gk104_fifo *fifo)
        for (engn = 0; engn < ARRAY_SIZE(fifo->engine); engn++) {
                u32 stat = nvkm_rd32(device, 0x002640 + (engn * 0x08));
                u32 busy = (stat & 0x80000000);
-               u32 next = (stat & 0x07ff0000) >> 16;
+               u32 next = (stat & 0x0fff0000) >> 16;
                u32 chsw = (stat & 0x00008000);
                u32 save = (stat & 0x00004000);
                u32 load = (stat & 0x00002000);
-               u32 prev = (stat & 0x000007ff);
+               u32 prev = (stat & 0x00000fff);
                u32 chid = load ? next : prev;
                (void)save;