/* CFI Manufacture ID's */
#define SPI_FLASH_CFI_MFR_SPANSION 0x01
#define SPI_FLASH_CFI_MFR_STMICRO 0x20
+#define SPI_FLASH_CFI_MFR_MACRONIX 0xc2
#define SPI_FLASH_CFI_MFR_WINBOND 0xef
/* SECT flags */
/* Common status */
#define STATUS_WIP 0x01
#define STATUS_QEB_WINSPAN (1 << 1)
+#define STATUS_QEB_MXIC (1 << 6)
#define STATUS_PEC 0x80
/* Flash timeout values */
/* Program the status register */
int spi_flash_cmd_write_status(struct spi_flash *flash, u8 sr);
+/* Set quad enbale bit for macronix flashes */
+int spi_flash_set_qeb_mxic(struct spi_flash *flash);
+
/* Set quad enbale bit for winbond and spansion flashes */
int spi_flash_set_qeb_winspan(struct spi_flash *flash);
return 0;
}
+#ifdef CONFIG_SPI_FLASH_MACRONIX
+int spi_flash_set_qeb_mxic(struct spi_flash *flash)
+{
+ u8 qeb_status;
+ u8 cmd;
+ int ret;
+
+ cmd = CMD_READ_STATUS;
+ ret = spi_flash_read_common(flash, &cmd, 1, &qeb_status, 1);
+ if (ret < 0) {
+ debug("SF: fail to read status register\n");
+ return ret;
+ }
+
+ if (qeb_status & STATUS_QEB_MXIC) {
+ debug("SF: Quad enable bit is already set\n");
+ } else {
+ ret = spi_flash_cmd_write_status(flash, STATUS_QEB_MXIC);
+ if (ret < 0)
+ return ret;
+ }
+
+ return ret;
+}
+#endif
+
#if defined(CONFIG_SPI_FLASH_SPANSION) || defined(CONFIG_SPI_FLASH_WINBOND)
static int spi_flash_cmd_write_config(struct spi_flash *flash, u8 cr)
{
static int spi_flash_set_qeb(struct spi_flash *flash, u8 idcode0)
{
switch (idcode0) {
+#ifdef CONFIG_SPI_FLASH_MACRONIX
+ case SPI_FLASH_CFI_MFR_MACRONIX:
+ return spi_flash_set_qeb_mxic(flash);
+#endif
#if defined(CONFIG_SPI_FLASH_SPANSION) || defined(CONFIG_SPI_FLASH_WINBOND)
case SPI_FLASH_CFI_MFR_SPANSION:
case SPI_FLASH_CFI_MFR_WINBOND: