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revert to vlynq bus clock divisor guessing
author
Nicolas Thill
<nico@openwrt.org>
Mon, 1 Oct 2007 10:16:14 +0000
(10:16 +0000)
committer
Nicolas Thill
<nico@openwrt.org>
Mon, 1 Oct 2007 10:16:14 +0000
(10:16 +0000)
SVN-Revision: 9086
target/linux/ar7/files/arch/mips/ar7/vlynq-pci.c
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diff --git
a/target/linux/ar7/files/arch/mips/ar7/vlynq-pci.c
b/target/linux/ar7/files/arch/mips/ar7/vlynq-pci.c
index bffea513553025eacc2ed67a343d1e7ac91df7be..7a640dbef7568014281f5519e76c169b17edf4d0 100644
(file)
--- a/
target/linux/ar7/files/arch/mips/ar7/vlynq-pci.c
+++ b/
target/linux/ar7/files/arch/mips/ar7/vlynq-pci.c
@@
-313,7
+313,7
@@
static int vlynq_pci_probe(struct vlynq_device *dev)
if (result)
return result;
- dev->divisor = vlynq_
ldiv4
;
+ dev->divisor = vlynq_
div_auto
;
result = vlynq_device_enable(dev);
if (result)
return result;