drm/amdgpu: move the VCN DPG mode read and write to VCN

Since this is VCN specific and only used by VCN

Signed-off-by: Leo Liu <leo.liu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h
index a0ad19af90806b814118942ddb39f770d2da1ebf..98bd0982d325ab50bb10105889fd9788da64171b 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h
@@ -45,6 +45,27 @@
 #define VCN_ENC_CMD_REG_WRITE          0x0000000b
 #define VCN_ENC_CMD_REG_WAIT           0x0000000c
 
+#define RREG32_SOC15_DPG_MODE(ip, inst, reg, mask, sram_sel)                           \
+       ({      WREG32_SOC15(ip, inst, mmUVD_DPG_LMA_MASK, mask);                       \
+               WREG32_SOC15(ip, inst, mmUVD_DPG_LMA_CTL,                               \
+                       UVD_DPG_LMA_CTL__MASK_EN_MASK |                                 \
+                       ((adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg)      \
+                       << UVD_DPG_LMA_CTL__READ_WRITE_ADDR__SHIFT) |                   \
+                       (sram_sel << UVD_DPG_LMA_CTL__SRAM_SEL__SHIFT));                \
+               RREG32_SOC15(ip, inst, mmUVD_DPG_LMA_DATA);                             \
+       })
+
+#define WREG32_SOC15_DPG_MODE(ip, inst, reg, value, mask, sram_sel)                    \
+       do {                                                                            \
+               WREG32_SOC15(ip, inst, mmUVD_DPG_LMA_DATA, value);                      \
+               WREG32_SOC15(ip, inst, mmUVD_DPG_LMA_MASK, mask);                       \
+               WREG32_SOC15(ip, inst, mmUVD_DPG_LMA_CTL,                               \
+                       UVD_DPG_LMA_CTL__READ_WRITE_MASK |                              \
+                       ((adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg)      \
+                       << UVD_DPG_LMA_CTL__READ_WRITE_ADDR__SHIFT) |                   \
+                       (sram_sel << UVD_DPG_LMA_CTL__SRAM_SEL__SHIFT));                \
+       } while (0)
+
 enum engine_status_constants {
        UVD_PGFSM_STATUS__UVDM_UVDU_PWR_ON = 0x2AAAA0,
        UVD_PGFSM_CONFIG__UVDM_UVDU_PWR_ON = 0x00000002,

diff --git a/drivers/gpu/drm/amd/amdgpu/soc15_common.h b/drivers/gpu/drm/amd/amdgpu/soc15_common.h
index c634606e64bd5080d5842e7a98e353605011c0a7..47f74dab365dc31193ade9b964e3e703049169c5 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/soc15_common.h
+++ b/drivers/gpu/drm/amd/amdgpu/soc15_common.h
@@ -69,27 +69,6 @@
                }                                               \
        } while (0)
 
-#define RREG32_SOC15_DPG_MODE(ip, inst, reg, mask, sram_sel)   \
-               ({ WREG32_SOC15(ip, inst, mmUVD_DPG_LMA_MASK, mask); \
-                       WREG32_SOC15(ip, inst, mmUVD_DPG_LMA_CTL,       \
-                               UVD_DPG_LMA_CTL__MASK_EN_MASK |                         \
-                               ((adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg) \
-                               << UVD_DPG_LMA_CTL__READ_WRITE_ADDR__SHIFT) | \
-                               (sram_sel << UVD_DPG_LMA_CTL__SRAM_SEL__SHIFT));        \
-                       RREG32_SOC15(ip, inst, mmUVD_DPG_LMA_DATA); })
-
-#define WREG32_SOC15_DPG_MODE(ip, inst, reg, value, mask, sram_sel)    \
-       do {                                                    \
-               WREG32_SOC15(ip, inst, mmUVD_DPG_LMA_DATA, value);      \
-               WREG32_SOC15(ip, inst, mmUVD_DPG_LMA_MASK, mask);               \
-               WREG32_SOC15(ip, inst, mmUVD_DPG_LMA_CTL,       \
-                       UVD_DPG_LMA_CTL__READ_WRITE_MASK |      \
-                       ((adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg) \
-                       << UVD_DPG_LMA_CTL__READ_WRITE_ADDR__SHIFT) |   \
-                       (sram_sel << UVD_DPG_LMA_CTL__SRAM_SEL__SHIFT)); \
-       } while (0)
-
-
 #define WREG32_RLC(reg, value) \
        do {                                                    \
                if (amdgpu_virt_support_rlc_prg_reg(adev)) {    \