iw_cxgb4: Detect Ing. Padding Boundary at run-time
authorHariprasad Shenai <hariprasad@chelsio.com>
Mon, 14 Jul 2014 16:04:51 +0000 (21:34 +0530)
committerDavid S. Miller <davem@davemloft.net>
Tue, 15 Jul 2014 23:25:16 +0000 (16:25 -0700)
Updates iw_cxgb4 to determine the Ingress Padding Boundary from
cxgb4_lld_info, and take subsequent actions.

Signed-off-by: Steve Wise <swise@opengridcomputing.com>
Signed-off-by: Hariprasad Shenai <hariprasad@chelsio.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
drivers/infiniband/hw/cxgb4/cq.c
drivers/infiniband/hw/cxgb4/device.c
drivers/infiniband/hw/cxgb4/iw_cxgb4.h
drivers/infiniband/hw/cxgb4/provider.c
drivers/infiniband/hw/cxgb4/qp.c
drivers/infiniband/hw/cxgb4/t4.h
drivers/net/ethernet/chelsio/cxgb4/cxgb4_main.c
drivers/net/ethernet/chelsio/cxgb4/cxgb4_uld.h

index c04292c950f1750ac5fa2fc35b1ea4fda6a76079..f04a838b65c7151b33c73c695fed0a2a67f544fe 100644 (file)
@@ -895,7 +895,7 @@ struct ib_cq *c4iw_create_cq(struct ib_device *ibdev, int entries,
        /*
         * Make actual HW queue 2x to avoid cdix_inc overflows.
         */
-       hwentries = min(entries * 2, T4_MAX_IQ_SIZE);
+       hwentries = min(entries * 2, rhp->rdev.hw_queue.t4_max_iq_size);
 
        /*
         * Make HW queue at least 64 entries so GTS updates aren't too
@@ -912,7 +912,7 @@ struct ib_cq *c4iw_create_cq(struct ib_device *ibdev, int entries,
        if (ucontext) {
                memsize = roundup(memsize, PAGE_SIZE);
                hwentries = memsize / sizeof *chp->cq.queue;
-               while (hwentries > T4_MAX_IQ_SIZE) {
+               while (hwentries > rhp->rdev.hw_queue.t4_max_iq_size) {
                        memsize -= PAGE_SIZE;
                        hwentries = memsize / sizeof *chp->cq.queue;
                }
index dd93aadc996e1ca15e0739a1d60e9c4930b449b8..88291ef829419b7fafdec997c316fa26f3d0d494 100644 (file)
@@ -768,6 +768,27 @@ static struct c4iw_dev *c4iw_alloc(const struct cxgb4_lld_info *infop)
        }
        devp->rdev.lldi = *infop;
 
+       /* init various hw-queue params based on lld info */
+       PDBG("%s: Ing. padding boundary is %d, egrsstatuspagesize = %d\n",
+            __func__, devp->rdev.lldi.sge_ingpadboundary,
+            devp->rdev.lldi.sge_egrstatuspagesize);
+
+       devp->rdev.hw_queue.t4_eq_status_entries =
+               devp->rdev.lldi.sge_ingpadboundary > 64 ? 2 : 1;
+       devp->rdev.hw_queue.t4_max_eq_size =
+               65520 - devp->rdev.hw_queue.t4_eq_status_entries;
+       devp->rdev.hw_queue.t4_max_iq_size = 65520 - 1;
+       devp->rdev.hw_queue.t4_max_rq_size =
+               8192 - devp->rdev.hw_queue.t4_eq_status_entries;
+       devp->rdev.hw_queue.t4_max_sq_size =
+               devp->rdev.hw_queue.t4_max_eq_size - 1;
+       devp->rdev.hw_queue.t4_max_qp_depth =
+               devp->rdev.hw_queue.t4_max_rq_size - 1;
+       devp->rdev.hw_queue.t4_max_cq_depth =
+               devp->rdev.hw_queue.t4_max_iq_size - 1;
+       devp->rdev.hw_queue.t4_stat_len =
+               devp->rdev.lldi.sge_egrstatuspagesize;
+
        /*
         * For T5 devices, we map all of BAR2 with WC.
         * For T4 devices with onchip qp mem, we map only that part
index 125bc5d1e175ba4b18085fa0323dd304689b504b..9b9754c69ea05a7ebedb897591e15a4cfd28ca33 100644 (file)
@@ -139,6 +139,17 @@ struct c4iw_stats {
        u64  pas_ofld_conn_fails;
 };
 
+struct c4iw_hw_queue {
+       int t4_eq_status_entries;
+       int t4_max_eq_size;
+       int t4_max_iq_size;
+       int t4_max_rq_size;
+       int t4_max_sq_size;
+       int t4_max_qp_depth;
+       int t4_max_cq_depth;
+       int t4_stat_len;
+};
+
 struct c4iw_rdev {
        struct c4iw_resource resource;
        unsigned long qpshift;
@@ -156,6 +167,7 @@ struct c4iw_rdev {
        unsigned long oc_mw_pa;
        void __iomem *oc_mw_kva;
        struct c4iw_stats stats;
+       struct c4iw_hw_queue hw_queue;
        struct t4_dev_status_page *status_page;
 };
 
index b1d305338de6a06477d41ce11eb6f9519b3007c9..1d41b92caaf5df09752a0f912c317a7b3b56323a 100644 (file)
@@ -319,13 +319,13 @@ static int c4iw_query_device(struct ib_device *ibdev,
        props->vendor_part_id = (u32)dev->rdev.lldi.pdev->device;
        props->max_mr_size = T4_MAX_MR_SIZE;
        props->max_qp = T4_MAX_NUM_QP;
-       props->max_qp_wr = T4_MAX_QP_DEPTH;
+       props->max_qp_wr = dev->rdev.hw_queue.t4_max_qp_depth;
        props->max_sge = T4_MAX_RECV_SGE;
        props->max_sge_rd = 1;
        props->max_qp_rd_atom = c4iw_max_read_depth;
        props->max_qp_init_rd_atom = c4iw_max_read_depth;
        props->max_cq = T4_MAX_NUM_CQ;
-       props->max_cqe = T4_MAX_CQ_DEPTH;
+       props->max_cqe = dev->rdev.hw_queue.t4_max_cq_depth;
        props->max_mr = c4iw_num_stags(&dev->rdev);
        props->max_pd = T4_MAX_NUM_PD;
        props->local_ca_ack_delay = 0;
index 086f62f5dc9e2ba5978e81f02e8e392c8e201774..6f74e0e9a02279afe90bba826932e980b659a882 100644 (file)
@@ -258,7 +258,8 @@ static int create_qp(struct c4iw_rdev *rdev, struct t4_wq *wq,
        /*
         * eqsize is the number of 64B entries plus the status page size.
         */
-       eqsize = wq->sq.size * T4_SQ_NUM_SLOTS + T4_EQ_STATUS_ENTRIES;
+       eqsize = wq->sq.size * T4_SQ_NUM_SLOTS +
+               rdev->hw_queue.t4_eq_status_entries;
 
        res->u.sqrq.fetchszm_to_iqid = cpu_to_be32(
                V_FW_RI_RES_WR_HOSTFCMODE(0) |  /* no host cidx updates */
@@ -283,7 +284,8 @@ static int create_qp(struct c4iw_rdev *rdev, struct t4_wq *wq,
        /*
         * eqsize is the number of 64B entries plus the status page size.
         */
-       eqsize = wq->rq.size * T4_RQ_NUM_SLOTS + T4_EQ_STATUS_ENTRIES;
+       eqsize = wq->rq.size * T4_RQ_NUM_SLOTS +
+               rdev->hw_queue.t4_eq_status_entries;
        res->u.sqrq.fetchszm_to_iqid = cpu_to_be32(
                V_FW_RI_RES_WR_HOSTFCMODE(0) |  /* no host cidx updates */
                V_FW_RI_RES_WR_CPRIO(0) |       /* don't keep in chip cache */
@@ -1570,11 +1572,11 @@ struct ib_qp *c4iw_create_qp(struct ib_pd *pd, struct ib_qp_init_attr *attrs,
                return ERR_PTR(-EINVAL);
 
        rqsize = roundup(attrs->cap.max_recv_wr + 1, 16);
-       if (rqsize > T4_MAX_RQ_SIZE)
+       if (rqsize > rhp->rdev.hw_queue.t4_max_rq_size)
                return ERR_PTR(-E2BIG);
 
        sqsize = roundup(attrs->cap.max_send_wr + 1, 16);
-       if (sqsize > T4_MAX_SQ_SIZE)
+       if (sqsize > rhp->rdev.hw_queue.t4_max_sq_size)
                return ERR_PTR(-E2BIG);
 
        ucontext = pd->uobject ? to_c4iw_ucontext(pd->uobject->context) : NULL;
index 68b0a6bf4eb00e23f8b737828ff85e465cc24173..e64fa8b2be066cb2ee3345256546f63a9f34f3be 100644 (file)
 #define T4_MAX_NUM_QP 65536
 #define T4_MAX_NUM_CQ 65536
 #define T4_MAX_NUM_PD 65536
-#define T4_EQ_STATUS_ENTRIES (L1_CACHE_BYTES > 64 ? 2 : 1)
-#define T4_MAX_EQ_SIZE (65520 - T4_EQ_STATUS_ENTRIES)
-#define T4_MAX_IQ_SIZE (65520 - 1)
-#define T4_MAX_RQ_SIZE (8192 - T4_EQ_STATUS_ENTRIES)
-#define T4_MAX_SQ_SIZE (T4_MAX_EQ_SIZE - 1)
-#define T4_MAX_QP_DEPTH (T4_MAX_RQ_SIZE - 1)
-#define T4_MAX_CQ_DEPTH (T4_MAX_IQ_SIZE - 1)
 #define T4_MAX_NUM_STAG (1<<15)
 #define T4_MAX_MR_SIZE (~0ULL)
 #define T4_PAGESIZE_MASK 0xffff000  /* 4KB-128MB */
 #define T4_STAG_UNSET 0xffffffff
 #define T4_FW_MAJ 0
-#define T4_EQ_STATUS_ENTRIES (L1_CACHE_BYTES > 64 ? 2 : 1)
 #define A_PCIE_MA_SYNC 0x30b4
 
 struct t4_status_page {
index 2b438bd68c73bbe2ae023a759c921421c12793f2..a7ce996630edd602d04ab7d9cc3214d702c82f25 100644 (file)
@@ -4109,6 +4109,8 @@ static void uld_attach(struct adapter *adap, unsigned int uld)
        lli.db_reg = adap->regs + MYPF_REG(SGE_PF_KDOORBELL);
        lli.fw_vers = adap->params.fw_vers;
        lli.dbfifo_int_thresh = dbfifo_int_thresh;
+       lli.sge_ingpadboundary = adap->sge.fl_align;
+       lli.sge_egrstatuspagesize = adap->sge.stat_len;
        lli.sge_pktshift = adap->sge.pktshift;
        lli.enable_fw_ofld_conn = adap->flags & FW_OFLD_CONN;
        lli.ulptx_memwrite_dsgl = adap->params.ulptx_memwrite_dsgl;
index 8f60851b75ad47220b09f4a872a3714056bea2a9..962458f5d5b3aeb913607192df6e3464158d662b 100644 (file)
@@ -251,6 +251,8 @@ struct cxgb4_lld_info {
        void __iomem *gts_reg;               /* address of GTS register */
        void __iomem *db_reg;                /* address of kernel doorbell */
        int dbfifo_int_thresh;               /* doorbell fifo int threshold */
+       unsigned int sge_ingpadboundary;     /* SGE ingress padding boundary */
+       unsigned int sge_egrstatuspagesize;  /* SGE egress status page size */
        unsigned int sge_pktshift;           /* Padding between CPL and */
                                             /* packet data */
        unsigned int pf;                     /* Physical Function we're using */