drm/amdgpu: switch to amdgpu_umc structure

create new amdgpu_umc structure to for more umc
settings in future and switch to the new structure

Signed-off-by: Tao Zhou <tao.zhou1@amd.com>
Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Dennis Li <dennis.li@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
index 61bd7be69a3f5954a531dec0e4386f951bdf16c7..2aa06be839742728c2fb94bd9745815df98d7ec2 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
@@ -948,6 +948,9 @@ struct amdgpu_device {
        /* KFD */
        struct amdgpu_kfd_dev           kfd;
 
+       /* UMC */
+       struct amdgpu_umc               umc;
+
        /* display related functionality */
        struct amdgpu_display_manager dm;
 
@@ -973,7 +976,6 @@ struct amdgpu_device {
 
        const struct amdgpu_nbio_funcs  *nbio_funcs;
        const struct amdgpu_df_funcs    *df_funcs;
-       const struct amdgpu_umc_funcs   *umc_funcs;
 
        /* delayed work_func for deferring clockgating during resume */
        struct delayed_work     delayed_init_work;

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
index a6134280b9417f8988beda522cde643b412f2acf..5f428a3929bdb3e520642381bcb4f9173d09e0bd 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
@@ -595,8 +595,8 @@ int amdgpu_ras_error_query(struct amdgpu_device *adev,
 
        switch (info->head.block) {
        case AMDGPU_RAS_BLOCK__UMC:
-               if (adev->umc_funcs->query_ras_error_count)
-                       adev->umc_funcs->query_ras_error_count(adev, &err_data);
+               if (adev->umc.funcs->query_ras_error_count)
+                       adev->umc.funcs->query_ras_error_count(adev, &err_data);
                break;
        default:
                break;

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_umc.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_umc.h
index 1ee1a00e5ac8f30111afdf7edaef47909a1e5753..f5d6def96414287ca86464a1fa0bfc6999a0cd64 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_umc.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_umc.h
@@ -26,4 +26,10 @@ struct amdgpu_umc_funcs {
                                        void *ras_error_status);
 };
 
+struct amdgpu_umc {
+       /* max error count in one ras query call */
+       uint32_t max_ras_err_cnt_per_query;
+       const struct amdgpu_umc_funcs *funcs;
+};
+
 #endif

diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
index 5282c9489c70c72834f60e0a4b08f8e8bcde3e1c..ae685998b2827bee5d885e2f0191d491fdb2f2e6 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
@@ -247,8 +247,8 @@ static int gmc_v9_0_process_ras_data_cb(struct amdgpu_device *adev,
 {
        struct ras_err_data err_data = {0, 0};
        kgd2kfd_set_sram_ecc_flag(adev->kfd.dev);
-       if (adev->umc_funcs->query_ras_error_count)
-               adev->umc_funcs->query_ras_error_count(adev, &err_data);
+       if (adev->umc.funcs->query_ras_error_count)
+               adev->umc.funcs->query_ras_error_count(adev, &err_data);
        amdgpu_ras_reset_gpu(adev, 0);
        return AMDGPU_RAS_UE;
 }
@@ -635,7 +635,9 @@ static void gmc_v9_0_set_umc_funcs(struct amdgpu_device *adev)
 {
        switch (adev->asic_type) {
        case CHIP_VEGA20:
-               adev->umc_funcs = &umc_v6_1_funcs;
+               adev->umc.max_ras_err_cnt_per_query =
+                       UMC_V6_1_UMC_INSTANCE_NUM * UMC_V6_1_CHANNEL_INSTANCE_NUM;
+               adev->umc.funcs = &umc_v6_1_funcs;
                break;
        default:
                break;