dt-bindings: net-next: Add DT bindings documentation for Allwinner dwmac-sun8i
authorLABBE Corentin <clabbe.montjoie@gmail.com>
Wed, 31 May 2017 07:18:34 +0000 (09:18 +0200)
committerDavid S. Miller <davem@davemloft.net>
Thu, 1 Jun 2017 18:53:03 +0000 (14:53 -0400)
This patch adds documentation for Device-Tree bindings for the
Allwinner dwmac-sun8i driver.

Signed-off-by: Corentin Labbe <clabbe.montjoie@gmail.com>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: David S. Miller <davem@davemloft.net>
Documentation/devicetree/bindings/net/dwmac-sun8i.txt [new file with mode: 0644]

diff --git a/Documentation/devicetree/bindings/net/dwmac-sun8i.txt b/Documentation/devicetree/bindings/net/dwmac-sun8i.txt
new file mode 100644 (file)
index 0000000..08e708c
--- /dev/null
@@ -0,0 +1,78 @@
+* Allwinner sun8i GMAC ethernet controller
+
+This device is a platform glue layer for stmmac.
+Please see stmmac.txt for the other unchanged properties.
+
+Required properties:
+- compatible: should be one of the following string:
+               "allwinner,sun8i-a83t-emac"
+               "allwinner,sun8i-h3-emac"
+               "allwinner,sun50i-a64-emac"
+- reg: address and length of the register for the device.
+- interrupts: interrupt for the device
+- interrupt-names: should be "macirq"
+- clocks: A phandle to the reference clock for this device
+- clock-names: should be "stmmaceth"
+- resets: A phandle to the reset control for this device
+- reset-names: should be "stmmaceth"
+- phy-mode: See ethernet.txt
+- phy-handle: See ethernet.txt
+- #address-cells: shall be 1
+- #size-cells: shall be 0
+- syscon: A phandle to the syscon of the SoC with one of the following
+ compatible string:
+  - allwinner,sun8i-h3-system-controller
+  - allwinner,sun50i-a64-system-controller
+  - allwinner,sun8i-a83t-system-controller
+
+Optional properties:
+- allwinner,tx-delay-ps: TX clock delay chain value in ps. Range value is 0-700. Default is 0)
+- allwinner,rx-delay-ps: RX clock delay chain value in ps. Range value is 0-3100. Default is 0)
+Both delay properties need to be a multiple of 100. They control the delay for
+external PHY.
+
+Optional properties for "allwinner,sun8i-h3-emac":
+- allwinner,leds-active-low: EPHY LEDs are active low
+
+Required child node of emac:
+- mdio bus node: should be named mdio
+
+Required properties of the mdio node:
+- #address-cells: shall be 1
+- #size-cells: shall be 0
+
+The device node referenced by "phy" or "phy-handle" should be a child node
+of the mdio node. See phy.txt for the generic PHY bindings.
+
+Required properties of the phy node with "allwinner,sun8i-h3-emac":
+- clocks: a phandle to the reference clock for the EPHY
+- resets: a phandle to the reset control for the EPHY
+
+Example:
+
+emac: ethernet@1c0b000 {
+       compatible = "allwinner,sun8i-h3-emac";
+       syscon = <&syscon>;
+       reg = <0x01c0b000 0x104>;
+       interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
+       interrupt-names = "macirq";
+       resets = <&ccu RST_BUS_EMAC>;
+       reset-names = "stmmaceth";
+       clocks = <&ccu CLK_BUS_EMAC>;
+       clock-names = "stmmaceth";
+       #address-cells = <1>;
+       #size-cells = <0>;
+
+       phy-handle = <&int_mii_phy>;
+       phy-mode = "mii";
+       allwinner,leds-active-low;
+       mdio: mdio {
+               #address-cells = <1>;
+               #size-cells = <0>;
+               int_mii_phy: ethernet-phy@1 {
+                       reg = <1>;
+                       clocks = <&ccu CLK_BUS_EPHY>;
+                       resets = <&ccu RST_BUS_EPHY>;
+               };
+       };
+};