perf/x86: Fix :pp without LBR
authorAndi Kleen <ak@linux.intel.com>
Fri, 8 Aug 2014 00:08:54 +0000 (17:08 -0700)
committerIngo Molnar <mingo@kernel.org>
Wed, 13 Aug 2014 05:51:12 +0000 (07:51 +0200)
This fixes a side effect of Kan's earlier patch to probe the LBRs at boot
time. Normally when the LBRs are disabled cycles:pp is disabled too.
So for example cycles:pp doesn't work.

However this is not needed with PEBSv2 and later (Haswell) because
it does not need LBRs to correct the IP-off-by-one.

So add an extra check for PEBSv2 that also allows :pp

Signed-off-by: Andi Kleen <ak@linux.intel.com>
Signed-off-by: Peter Zijlstra <peterz@infradead.org>
Cc: kan.liang@intel.com
Cc: Arnaldo Carvalho de Melo <acme@kernel.org>
Link: http://lkml.kernel.org/r/1407456534-15747-1-git-send-email-andi@firstfloor.org
Signed-off-by: Ingo Molnar <mingo@kernel.org>
arch/x86/kernel/cpu/perf_event.c

index 2879ecdaac430c62710db3c90b326e6e25f60acf..0646d3b63b9d6f4e8a91a8fefe93b298bd71514c 100644 (file)
@@ -387,7 +387,7 @@ int x86_pmu_hw_config(struct perf_event *event)
                        precise++;
 
                        /* Support for IP fixup */
-                       if (x86_pmu.lbr_nr)
+                       if (x86_pmu.lbr_nr || x86_pmu.intel_cap.pebs_format >= 2)
                                precise++;
                }