ipq40xx: add open-drain support to pinctrl-msm

Submitted upstream. Shouldn't affect existing devices, but enables new
device support.

https://lore.kernel.org/linux-gpio/20200703080646.23233-1-computersforpeace@gmail.com/

Currently queued for-next:
https://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl.git/commit/?h=for-next&id=13355ca35cd16f5024655ac06e228b3c199e52a9

Signed-off-by: Brian Norris <computersforpeace@gmail.com>
[refresh patch]
Signed-off-by: Christian Lamparter <chunkeey@gmail.com>

diff --git a/target/linux/ipq40xx/patches-5.4/090-pinctrl-msm-open-drain.patch b/target/linux/ipq40xx/patches-5.4/090-pinctrl-msm-open-drain.patch
new file mode 100644 (file)
index 0000000..5cd4ccc
--- /dev/null
+++ b/target/linux/ipq40xx/patches-5.4/090-pinctrl-msm-open-drain.patch
@@ -0,0 +1,81 @@
+From 5b08c1d567ee8e6af94696b3e549997cbdb2bb80 Mon Sep 17 00:00:00 2001
+From: Jaiganesh Narayanan <njaigane@codeaurora.org>
+Date: Thu, 1 Sep 2016 10:40:38 +0530
+Subject: [PATCH] pinctrl: qcom: ipq4019: add open drain support
+
+Signed-off-by: Jaiganesh Narayanan <njaigane@codeaurora.org>
+[ Brian: adapted from from the Chromium OS kernel used on IPQ4019-based
+  WiFi APs. ]
+Signed-off-by: Brian Norris <computersforpeace@gmail.com>
+---
+https://lore.kernel.org/linux-gpio/20200703080646.23233-1-computersforpeace@gmail.com/
+
+ drivers/pinctrl/qcom/pinctrl-ipq4019.c |  1 +
+ drivers/pinctrl/qcom/pinctrl-msm.c     | 13 +++++++++++++
+ drivers/pinctrl/qcom/pinctrl-msm.h     |  2 ++
+ 3 files changed, 16 insertions(+)
+
+--- a/drivers/pinctrl/qcom/pinctrl-ipq4019.c
++++ b/drivers/pinctrl/qcom/pinctrl-ipq4019.c
+@@ -254,6 +254,7 @@ DECLARE_QCA_GPIO_PINS(99);
+               .mux_bit = 2,                   \
+               .pull_bit = 0,                  \
+               .drv_bit = 6,                   \
++              .od_bit = 12,                   \
+               .oe_bit = 9,                    \
+               .in_bit = 0,                    \
+               .out_bit = 1,                   \
+--- a/drivers/pinctrl/qcom/pinctrl-msm.c
++++ b/drivers/pinctrl/qcom/pinctrl-msm.c
+@@ -225,6 +225,10 @@ static int msm_config_reg(struct msm_pin
+               *bit = g->pull_bit;
+               *mask = 3;
+               break;
++      case PIN_CONFIG_DRIVE_OPEN_DRAIN:
++              *bit = g->od_bit;
++              *mask = 1;
++              break;
+       case PIN_CONFIG_DRIVE_STRENGTH:
+               *bit = g->drv_bit;
+               *mask = 7;
+@@ -302,6 +306,12 @@ static int msm_config_group_get(struct p
+               if (!arg)
+                       return -EINVAL;
+               break;
++      case PIN_CONFIG_DRIVE_OPEN_DRAIN:
++              /* Pin is not open-drain */
++              if (!arg)
++                      return -EINVAL;
++              arg = 1;
++              break;
+       case PIN_CONFIG_DRIVE_STRENGTH:
+               arg = msm_regval_to_drive(arg);
+               break;
+@@ -374,6 +384,9 @@ static int msm_config_group_set(struct p
+                       else
+                               arg = MSM_PULL_UP;
+                       break;
++              case PIN_CONFIG_DRIVE_OPEN_DRAIN:
++                      arg = 1;
++                      break;
+               case PIN_CONFIG_DRIVE_STRENGTH:
+                       /* Check for invalid values */
+                       if (arg > 16 || arg < 2 || (arg % 2) != 0)
+--- a/drivers/pinctrl/qcom/pinctrl-msm.h
++++ b/drivers/pinctrl/qcom/pinctrl-msm.h
+@@ -38,6 +38,7 @@ struct msm_function {
+  * @mux_bit:              Offset in @ctl_reg for the pinmux function selection.
+  * @pull_bit:             Offset in @ctl_reg for the bias configuration.
+  * @drv_bit:              Offset in @ctl_reg for the drive strength configuration.
++ * @od_bit:               Offset in @ctl_reg for controlling open drain.
+  * @oe_bit:               Offset in @ctl_reg for controlling output enable.
+  * @in_bit:               Offset in @io_reg for the input bit value.
+  * @out_bit:              Offset in @io_reg for the output bit value.
+@@ -75,6 +76,7 @@ struct msm_pingroup {
+       unsigned pull_bit:5;
+       unsigned drv_bit:5;
+ 
++      unsigned od_bit:5;
+       unsigned oe_bit:5;
+       unsigned in_bit:5;
+       unsigned out_bit:5;