ARM: dts: am335x: Fix NAND device nodes
authorRoger Quadros <rogerq@ti.com>
Tue, 23 Feb 2016 16:37:21 +0000 (18:37 +0200)
committerTony Lindgren <tony@atomide.com>
Fri, 26 Feb 2016 18:32:14 +0000 (10:32 -0800)
Add compatible id, GPMC register resource and interrupt
resource to NAND controller nodes.

The GPMC node will provide an interrupt controller for the
NAND IRQs.

Cc: Teresa Remmet <t.remmet@phytec.de>
Cc: Ilya Ledvich <ilya@compulab.co.il>
Cc: Yegor Yefremov <yegorslists@googlemail.com>
Cc: Rostislav Lisovy <lisovy@gmail.com>
Cc: Enric Balletbo i Serra <eballetbo@iseebcn.com>
Signed-off-by: Roger Quadros <rogerq@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
arch/arm/boot/dts/am335x-baltos-ir5221.dts
arch/arm/boot/dts/am335x-chilisom.dtsi
arch/arm/boot/dts/am335x-cm-t335.dts
arch/arm/boot/dts/am335x-evm.dts
arch/arm/boot/dts/am335x-igep0033.dtsi
arch/arm/boot/dts/am335x-phycore-som.dtsi
arch/arm/boot/dts/am33xx.dtsi

index ded1eb64ea5216eb993f312fc2d2cbcad2e795cc..7b6bcb05db7fe97efd745c3f319379267054d837 100644 (file)
        status = "okay";
 
        nand@0,0 {
-               reg = <0 0 0>; /* CS0, offset 0 */
+               compatible = "ti,omap2-nand";
+               reg = <0 0 4>; /* CS0, offset 0, IO size 4 */
+               interrupt-parent = <&gpmc>;
+               interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */
+                            <1 IRQ_TYPE_NONE>; /* termcount */
                nand-bus-width = <8>;
                ti,nand-ecc-opt = "bch8";
                ti,nand-xfer-type = "polled";
index fda457b07e15c282887ede12eee576d56c6f3855..e8e7d9d9e26ba9bf025568d764f6f1f872829612 100644 (file)
@@ -7,6 +7,7 @@
  * published by the Free Software Foundation.
  */
 #include "am33xx.dtsi"
+#include <dt-bindings/interrupt-controller/irq.h>
 
 / {
        model = "Grinn AM335x ChiliSOM";
        pinctrl-0 = <&nandflash_pins>;
        ranges = <0 0 0x08000000 0x01000000>; /* CS0 0 @addr 0x08000000, size 0x01000000 */
        nand@0,0 {
+               compatible = "ti,omap2-nand";
                reg = <0 0 4>;  /* CS0, offset 0, IO size 4 */
+               interrupt-parent = <&gpmc>;
+               interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */
+                            <1 IRQ_TYPE_NONE>; /* termcount */
                ti,nand-ecc-opt = "bch8";
                ti,elm-id = <&elm>;
                nand-bus-width = <8>;
index 42e9b665582ab2672f6b112549d4178e5dc63d38..571df14a33a1c6ecfb1bd48cf0be615b0d33f8fc 100644 (file)
@@ -11,6 +11,7 @@
 /dts-v1/;
 
 #include "am33xx.dtsi"
+#include <dt-bindings/interrupt-controller/irq.h>
 
 / {
        model = "CompuLab CM-T335";
@@ -302,7 +303,11 @@ status = "okay";
        pinctrl-0 = <&nandflash_pins>;
        ranges = <0 0 0x08000000 0x10000000>;   /* CS0: NAND */
        nand@0,0 {
-               reg = <0 0 0>; /* CS0, offset 0 */
+               compatible = "ti,omap2-nand";
+               reg = <0 0 4>; /* CS0, offset 0, IO size 4 */
+               interrupt-parent = <&gpmc>;
+               interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */
+                            <1 IRQ_TYPE_NONE>; /* termcount */
                ti,nand-ecc-opt = "bch8";
                ti,elm-id = <&elm>;
                nand-bus-width = <8>;
index 0d6a68ce434a44fa8c9cfc37eacdd72dcab818e5..4e7a53e6a26049b573720da27a56d62d5ca83d4d 100644 (file)
        pinctrl-0 = <&nandflash_pins_s0>;
        ranges = <0 0 0x08000000 0x1000000>;    /* CS0: 16MB for NAND */
        nand@0,0 {
+               compatible = "ti,omap2-nand";
                reg = <0 0 4>; /* CS0, offset 0, IO size 4 */
+               interrupt-parent = <&gpmc>;
+               interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */
+                            <1 IRQ_TYPE_NONE>; /* termcount */
                ti,nand-ecc-opt = "bch8";
                ti,elm-id = <&elm>;
                nand-bus-width = <8>;
index 54f113546ecc0fcd6a520ff8f19b576b14bc80f1..4cfe0419a5353d3f592c169448edfde1198fc539 100644 (file)
@@ -11,6 +11,7 @@
 /dts-v1/;
 
 #include "am33xx.dtsi"
+#include <dt-bindings/interrupt-controller/irq.h>
 
 / {
        cpus {
        ranges = <0 0 0x08000000 0x1000000>;    /* CS0: 16MB for NAND */
 
        nand@0,0 {
+               compatible = "ti,omap2-nand";
                reg = <0 0 4>; /* CS0, offset 0, IO size 4 */
+               interrupt-parent = <&gpmc>;
+               interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */
+                            <1 IRQ_TYPE_NONE>; /* termcount */
                nand-bus-width = <8>;
                ti,nand-ecc-opt = "bch8";
                gpmc,device-width = <1>;
index c20ae6c6f6c7cf01ce54ac04d28e20ab40fdac20..80a56873a055e24a0c1d7f0bad1f79cdff2e87c3 100644 (file)
@@ -8,6 +8,7 @@
  */
 
 #include "am33xx.dtsi"
+#include <dt-bindings/interrupt-controller/irq.h>
 
 / {
        model = "Phytec AM335x phyCORE";
        pinctrl-0 = <&nandflash_pins>;
        ranges = <0 0 0x08000000 0x1000000>;   /* CS0: NAND */
        nandflash: nand@0,0 {
+               compatible = "ti,omap2-nand";
                reg = <0 0 4>; /* CS0, offset 0, IO size 4 */
+               interrupt-parent = <&gpmc>;
+               interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */
+                            <1 IRQ_TYPE_NONE>; /* termcount */
                nand-bus-width = <8>;
                ti,nand-ecc-opt = "bch8";
                gpmc,device-nand = "true";
index 04885f9f959e21fcffb388940d64be0b6eb32869..b8ca5b456a4b90d007bc49a656095fd4f181e1db 100644 (file)
                        gpmc,num-waitpins = <2>;
                        #address-cells = <2>;
                        #size-cells = <1>;
+                       interrupt-controller;
+                       #interrupt-cells = <2>;
                        status = "disabled";
                };