drm/msm/hdmi: add 74.176MHz and 154.0MHz pix clks

Signed-off-by: Rob Clark <robdclark@gmail.com>

diff --git a/drivers/gpu/drm/msm/hdmi/hdmi_phy_8960.c b/drivers/gpu/drm/msm/hdmi/hdmi_phy_8960.c
index eeed006eed1337a6c07c62e0cc62d944b95fce83..6997ec636c6d473413227f0701e3f1c72b94988c 100644 (file)
--- a/drivers/gpu/drm/msm/hdmi/hdmi_phy_8960.c
+++ b/drivers/gpu/drm/msm/hdmi/hdmi_phy_8960.c
@@ -53,6 +53,23 @@ struct pll_rate {
 
 /* NOTE: keep sorted highest freq to lowest: */
 static const struct pll_rate freqtbl[] = {
+       { 154000000, {
+               { 0x08, REG_HDMI_8960_PHY_PLL_REFCLK_CFG    },
+               { 0x20, REG_HDMI_8960_PHY_PLL_LOOP_FLT_CFG0 },
+               { 0xf9, REG_HDMI_8960_PHY_PLL_LOOP_FLT_CFG1 },
+               { 0x02, REG_HDMI_8960_PHY_PLL_VCOCAL_CFG0   },
+               { 0x03, REG_HDMI_8960_PHY_PLL_VCOCAL_CFG1   },
+               { 0x3b, REG_HDMI_8960_PHY_PLL_VCOCAL_CFG2   },
+               { 0x00, REG_HDMI_8960_PHY_PLL_VCOCAL_CFG3   },
+               { 0x86, REG_HDMI_8960_PHY_PLL_VCOCAL_CFG4   },
+               { 0x00, REG_HDMI_8960_PHY_PLL_VCOCAL_CFG5   },
+               { 0x0d, REG_HDMI_8960_PHY_PLL_SDM_CFG0      },
+               { 0x4d, REG_HDMI_8960_PHY_PLL_SDM_CFG1      },
+               { 0x5e, REG_HDMI_8960_PHY_PLL_SDM_CFG2      },
+               { 0x42, REG_HDMI_8960_PHY_PLL_SDM_CFG3      },
+               { 0x00, REG_HDMI_8960_PHY_PLL_SDM_CFG4      },
+               { 0, 0 } }
+       },
        /* 1080p60/1080p50 case */
        { 148500000, {
                { 0x02, REG_HDMI_8960_PHY_PLL_REFCLK_CFG    },
@@ -112,6 +129,23 @@ static const struct pll_rate freqtbl[] = {
                { 0x3b, REG_HDMI_8960_PHY_PLL_VCOCAL_CFG2   },
                { 0, 0 } }
        },
+       { 74176000, {
+               { 0x18, REG_HDMI_8960_PHY_PLL_REFCLK_CFG    },
+               { 0x20, REG_HDMI_8960_PHY_PLL_LOOP_FLT_CFG0 },
+               { 0xf9, REG_HDMI_8960_PHY_PLL_LOOP_FLT_CFG1 },
+               { 0xe5, REG_HDMI_8960_PHY_PLL_VCOCAL_CFG0   },
+               { 0x02, REG_HDMI_8960_PHY_PLL_VCOCAL_CFG1   },
+               { 0x3b, REG_HDMI_8960_PHY_PLL_VCOCAL_CFG2   },
+               { 0x00, REG_HDMI_8960_PHY_PLL_VCOCAL_CFG3   },
+               { 0x86, REG_HDMI_8960_PHY_PLL_VCOCAL_CFG4   },
+               { 0x00, REG_HDMI_8960_PHY_PLL_VCOCAL_CFG5   },
+               { 0x0c, REG_HDMI_8960_PHY_PLL_SDM_CFG0      },
+               { 0x4c, REG_HDMI_8960_PHY_PLL_SDM_CFG1      },
+               { 0x7d, REG_HDMI_8960_PHY_PLL_SDM_CFG2      },
+               { 0xbc, REG_HDMI_8960_PHY_PLL_SDM_CFG3      },
+               { 0x00, REG_HDMI_8960_PHY_PLL_SDM_CFG4      },
+               { 0, 0 } }
+       },
        { 65000000, {
                { 0x18, REG_HDMI_8960_PHY_PLL_REFCLK_CFG    },
                { 0x20, REG_HDMI_8960_PHY_PLL_LOOP_FLT_CFG0 },