--- /dev/null
+CONFIG_ALIGNMENT_TRAP=y
+CONFIG_ARCH_BINFMT_ELF_RANDOMIZE_PIE=y
+CONFIG_ARCH_HAS_ATOMIC64_DEC_IF_POSITIVE=y
+CONFIG_ARCH_HAVE_CUSTOM_GPIO_H=y
+CONFIG_ARCH_KIRKWOOD=y
+CONFIG_ARCH_KIRKWOOD_DT=y
+# CONFIG_ARCH_NEEDS_CPU_IDLE_COUPLED is not set
+CONFIG_ARCH_NR_GPIO=0
+CONFIG_ARCH_REQUIRE_GPIOLIB=y
+# CONFIG_ARCH_SELECT_MEMORY_MODEL is not set
+# CONFIG_ARCH_SPARSEMEM_DEFAULT is not set
+CONFIG_ARCH_WANT_IPC_PARSE_VERSION=y
+CONFIG_ARM=y
+CONFIG_ARM_APPENDED_DTB=y
+CONFIG_ARM_ATAG_DTB_COMPAT=y
+# CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEND is not set
+CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER=y
+# CONFIG_ARM_CPU_SUSPEND is not set
+CONFIG_ARM_L1_CACHE_SHIFT=5
+CONFIG_ARM_NR_BANKS=8
+CONFIG_ARM_PATCH_PHYS_VIRT=y
+# CONFIG_ARM_THUMB is not set
+# CONFIG_ARPD is not set
+CONFIG_ATAGS=y
+CONFIG_BLK_DEV_SD=y
+CONFIG_CACHE_FEROCEON_L2=y
+# CONFIG_CACHE_FEROCEON_L2_WRITETHROUGH is not set
+# CONFIG_CACHE_L2X0 is not set
+# CONFIG_CHARGER_MANAGER is not set
+CONFIG_CLKDEV_LOOKUP=y
+CONFIG_CLKSRC_MMIO=y
+CONFIG_CLONE_BACKWARDS=y
+CONFIG_CMDLINE="rootdelay=1 root=/dev/mmcblk0p1 noinitrd console=ttyS0,115200"
+CONFIG_CMDLINE_FROM_BOOTLOADER=y
+CONFIG_COMMON_CLK=y
+CONFIG_CPU_32v5=y
+CONFIG_CPU_ABRT_EV5T=y
+CONFIG_CPU_CACHE_VIVT=y
+CONFIG_CPU_COPY_FEROCEON=y
+CONFIG_CPU_CP15=y
+CONFIG_CPU_CP15_MMU=y
+CONFIG_CPU_FEROCEON=y
+# CONFIG_CPU_FEROCEON_OLD_ID is not set
+# CONFIG_CPU_ICACHE_DISABLE is not set
+CONFIG_CPU_IDLE=y
+CONFIG_CPU_IDLE_GOV_LADDER=y
+CONFIG_CPU_PABRT_LEGACY=y
+CONFIG_CPU_PM=y
+CONFIG_CPU_TLB_FEROCEON=y
+CONFIG_CPU_USE_DOMAINS=y
+CONFIG_CRC16=y
+CONFIG_DEBUG_LL_INCLUDE="mach/debug-macro.S"
+# CONFIG_DEBUG_PINCTRL is not set
+# CONFIG_DEBUG_USER is not set
+# CONFIG_DLCI is not set
+CONFIG_DNOTIFY=y
+CONFIG_DTC=y
+CONFIG_FRAME_POINTER=y
+CONFIG_GENERIC_ATOMIC64=y
+CONFIG_GENERIC_BUG=y
+CONFIG_GENERIC_CLOCKEVENTS=y
+CONFIG_GENERIC_CLOCKEVENTS_BUILD=y
+CONFIG_GENERIC_IDLE_POLL_SETUP=y
+CONFIG_GENERIC_IO=y
+CONFIG_GENERIC_IRQ_CHIP=y
+CONFIG_GENERIC_IRQ_SHOW=y
+CONFIG_GENERIC_PCI_IOMAP=y
+CONFIG_GENERIC_SMP_IDLE_THREAD=y
+CONFIG_GENERIC_STRNCPY_FROM_USER=y
+CONFIG_GENERIC_STRNLEN_USER=y
+CONFIG_GPIOLIB=y
+CONFIG_GPIO_DEVRES=y
+CONFIG_GPIO_GENERIC=y
+CONFIG_GPIO_MVEBU=y
+CONFIG_GPIO_SYSFS=y
+# CONFIG_HAMRADIO is not set
+CONFIG_HARDIRQS_SW_RESEND=y
+CONFIG_HAS_DMA=y
+CONFIG_HAS_IOMEM=y
+CONFIG_HAS_IOPORT=y
+# CONFIG_HAVE_64BIT_ALIGNED_ACCESS is not set
+CONFIG_HAVE_AOUT=y
+CONFIG_HAVE_ARCH_JUMP_LABEL=y
+CONFIG_HAVE_ARCH_KGDB=y
+CONFIG_HAVE_ARCH_PFN_VALID=y
+CONFIG_HAVE_ARCH_SECCOMP_FILTER=y
+CONFIG_HAVE_ARCH_TRACEHOOK=y
+# CONFIG_HAVE_BOOTMEM_INFO_NODE is not set
+CONFIG_HAVE_BPF_JIT=y
+CONFIG_HAVE_CLK=y
+CONFIG_HAVE_CLK_PREPARE=y
+CONFIG_HAVE_CONTEXT_TRACKING=y
+CONFIG_HAVE_C_RECORDMCOUNT=y
+CONFIG_HAVE_DEBUG_KMEMLEAK=y
+CONFIG_HAVE_DMA_API_DEBUG=y
+CONFIG_HAVE_DMA_ATTRS=y
+CONFIG_HAVE_DMA_CONTIGUOUS=y
+CONFIG_HAVE_DYNAMIC_FTRACE=y
+CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y
+CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y
+CONFIG_HAVE_FUNCTION_TRACER=y
+CONFIG_HAVE_GENERIC_DMA_COHERENT=y
+CONFIG_HAVE_GENERIC_HARDIRQS=y
+CONFIG_HAVE_IDE=y
+CONFIG_HAVE_IRQ_TIME_ACCOUNTING=y
+CONFIG_HAVE_KERNEL_GZIP=y
+CONFIG_HAVE_KERNEL_LZMA=y
+CONFIG_HAVE_KERNEL_LZO=y
+CONFIG_HAVE_KERNEL_XZ=y
+CONFIG_HAVE_LATENCYTOP_SUPPORT=y
+CONFIG_HAVE_MEMBLOCK=y
+CONFIG_HAVE_NET_DSA=y
+CONFIG_HAVE_OPROFILE=y
+CONFIG_HAVE_PERF_EVENTS=y
+CONFIG_HAVE_PROC_CPU=y
+CONFIG_HAVE_REGS_AND_STACK_ACCESS_API=y
+CONFIG_HAVE_SYSCALL_TRACEPOINTS=y
+CONFIG_HAVE_UID16=y
+CONFIG_HW_RANDOM=y
+CONFIG_HZ_PERIODIC=y
+CONFIG_I2C=y
+CONFIG_I2C_BOARDINFO=y
+CONFIG_INET_LRO=y
+CONFIG_INITRAMFS_SOURCE=""
+# CONFIG_IP_ADVANCED_ROUTER is not set
+CONFIG_IP_PIMSM_V1=y
+CONFIG_IP_PIMSM_V2=y
+CONFIG_IRQCHIP=y
+CONFIG_IRQ_DOMAIN=y
+CONFIG_IRQ_WORK=y
+CONFIG_KTIME_SCALAR=y
+CONFIG_LEDS_GPIO=y
+# CONFIG_LEDS_REGULATOR is not set
+CONFIG_LEGACY_PTYS=y
+CONFIG_LEGACY_PTY_COUNT=256
+CONFIG_M25PXX_USE_FAST_READ=y
+# CONFIG_MACH_D2NET_V2 is not set
+# CONFIG_MACH_DLINK_KIRKWOOD_DT is not set
+# CONFIG_MACH_DOCKSTAR is not set
+CONFIG_MACH_ESATA_SHEEVAPLUG=y
+# CONFIG_MACH_GURUPLUG is not set
+# CONFIG_MACH_INETSPACE_V2 is not set
+# CONFIG_MACH_MV88F6281GTW_GE is not set
+# CONFIG_MACH_NET2BIG_V2 is not set
+# CONFIG_MACH_NET5BIG_V2 is not set
+# CONFIG_MACH_NETSPACE_MAX_V2 is not set
+# CONFIG_MACH_NETSPACE_V2 is not set
+CONFIG_MACH_OPENRD=y
+CONFIG_MACH_OPENRD_BASE=y
+CONFIG_MACH_OPENRD_CLIENT=y
+# CONFIG_MACH_OPENRD_ULTIMATE is not set
+# CONFIG_MACH_RD88F6192_NAS is not set
+# CONFIG_MACH_RD88F6281 is not set
+CONFIG_MACH_SHEEVAPLUG=y
+# CONFIG_MACH_T5325 is not set
+# CONFIG_MACH_TS219 is not set
+# CONFIG_MACH_TS219_DT is not set
+# CONFIG_MACH_TS41X is not set
+CONFIG_MDIO_BOARDINFO=y
+CONFIG_MMC=y
+CONFIG_MMC_BLOCK=y
+CONFIG_MMC_MVSDIO=y
+# CONFIG_MMC_TIFM_SD is not set
+CONFIG_MODULES_USE_ELF_REL=y
+# CONFIG_MTD_CFI is not set
+CONFIG_MTD_CMDLINE_PARTS=y
+CONFIG_MTD_M25P80=y
+CONFIG_MTD_NAND=y
+CONFIG_MTD_NAND_ECC=y
+CONFIG_MTD_NAND_ORION=y
+CONFIG_MTD_OF_PARTS=y
+# CONFIG_MTD_SM_COMMON is not set
+CONFIG_MTD_UIMAGE_SPLIT=y
+CONFIG_MV643XX_ETH=y
+CONFIG_MVEBU_CLK_CORE=y
+CONFIG_MVEBU_CLK_GATING=y
+CONFIG_MVEBU_MBUS=y
+CONFIG_MVMDIO=y
+CONFIG_NEED_DMA_MAP_STATE=y
+CONFIG_NEED_PER_CPU_KM=y
+CONFIG_NET_DSA=y
+CONFIG_NET_DSA_MV88E6123_61_65=y
+CONFIG_NET_DSA_MV88E6131=y
+CONFIG_NET_DSA_MV88E6XXX=y
+CONFIG_NET_DSA_MV88E6XXX_NEED_PPU=y
+CONFIG_NET_DSA_TAG_DSA=y
+CONFIG_NET_DSA_TAG_EDSA=y
+# CONFIG_NET_IP_TUNNEL is not set
+CONFIG_NLS=y
+CONFIG_OF=y
+CONFIG_OF_ADDRESS=y
+CONFIG_OF_DEVICE=y
+CONFIG_OF_EARLY_FLATTREE=y
+CONFIG_OF_FLATTREE=y
+CONFIG_OF_GPIO=y
+CONFIG_OF_I2C=y
+CONFIG_OF_IRQ=y
+CONFIG_OF_MDIO=y
+CONFIG_OF_MTD=y
+CONFIG_OF_NET=y
+CONFIG_OF_PCI=y
+CONFIG_OF_PCI_IRQ=y
+CONFIG_OLD_SIGACTION=y
+CONFIG_OLD_SIGSUSPEND3=y
+CONFIG_OUTER_CACHE=y
+CONFIG_PAGEFLAGS_EXTENDED=y
+CONFIG_PAGE_OFFSET=0xC0000000
+CONFIG_PCI=y
+CONFIG_PCI_MVEBU=y
+# CONFIG_PDA_POWER is not set
+CONFIG_PERF_USE_VMALLOC=y
+CONFIG_PHYLIB=y
+CONFIG_PINCONF=y
+CONFIG_PINCTRL=y
+CONFIG_PINCTRL_KIRKWOOD=y
+CONFIG_PINCTRL_MVEBU=y
+# CONFIG_PINCTRL_SINGLE is not set
+CONFIG_PINMUX=y
+CONFIG_PLAT_ORION=y
+CONFIG_PLAT_ORION_LEGACY=y
+CONFIG_POWER_RESET=y
+CONFIG_POWER_RESET_GPIO=y
+# CONFIG_POWER_RESET_QNAP is not set
+CONFIG_POWER_SUPPLY=y
+# CONFIG_PREEMPT_RCU is not set
+CONFIG_PROC_DEVICETREE=y
+# CONFIG_RCU_STALL_COMMON is not set
+CONFIG_REGULATOR=y
+# CONFIG_REGULATOR_DEBUG is not set
+# CONFIG_REGULATOR_DUMMY is not set
+CONFIG_REGULATOR_FIXED_VOLTAGE=y
+# CONFIG_REGULATOR_USERSPACE_CONSUMER is not set
+# CONFIG_RFKILL_REGULATOR is not set
+CONFIG_RTC_CLASS=y
+# CONFIG_RTC_DRV_MV is not set
+CONFIG_SCHED_HRTICK=y
+CONFIG_SCSI=y
+# CONFIG_SCSI_MULTI_LUN is not set
+CONFIG_SERIAL_8250_DEPRECATED_OPTIONS=y
+CONFIG_SERIAL_OF_PLATFORM=y
+CONFIG_SPI=y
+CONFIG_SPI_MASTER=y
+CONFIG_SPI_ORION=y
+CONFIG_SPLIT_PTLOCK_CPUS=999999
+CONFIG_SYS_SUPPORTS_APM_EMULATION=y
+CONFIG_TICK_CPU_ACCOUNTING=y
+CONFIG_UID16=y
+CONFIG_UIDGID_CONVERTED=y
+CONFIG_UNCOMPRESS_INCLUDE="mach/uncompress.h"
+CONFIG_USB=y
+CONFIG_USB_ARCH_HAS_XHCI=y
+CONFIG_USB_COMMON=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_EHCI_HCD_ORION=y
+# CONFIG_USB_EHCI_HCD_PLATFORM is not set
+CONFIG_USB_EHCI_PCI=y
+CONFIG_USB_STORAGE=y
+CONFIG_USB_SUPPORT=y
+# CONFIG_USB_UHCI_HCD is not set
+CONFIG_USE_OF=y
+CONFIG_VECTORS_BASE=0xffff0000
+# CONFIG_VFP is not set
+CONFIG_VM_EVENT_COUNTERS=y
+CONFIG_WAN=y
+CONFIG_XZ_DEC_ARM=y
+CONFIG_XZ_DEC_BCJ=y
+CONFIG_ZBOOT_ROM_BSS=0x0
+CONFIG_ZBOOT_ROM_TEXT=0x0
+CONFIG_ZONE_DMA_FLAG=0
--- /dev/null
+From 6b5917890ada1dc078ee64af2500cd6289fcf9bc Mon Sep 17 00:00:00 2001
+From: Andrew Murray <Andrew.Murray@arm.com>
+Date: Tue, 7 May 2013 16:31:12 +0100
+Subject: [PATCH 01/29] of/pci: Provide support for parsing PCI DT ranges
+ property
+
+This patch factors out common implementation patterns to reduce overall kernel
+code and provide a means for host bridge drivers to directly obtain struct
+resources from the DT's ranges property without relying on architecture specific
+DT handling. This will make it easier to write archiecture independent host bridge
+drivers and mitigate against further duplication of DT parsing code.
+
+This patch can be used in the following way:
+
+ struct of_pci_range_parser parser;
+ struct of_pci_range range;
+
+ if (of_pci_range_parser_init(&parser, np))
+ ; //no ranges property
+
+ for_each_of_pci_range(&parser, &range) {
+
+ /*
+ directly access properties of the address range, e.g.:
+ range.pci_space, range.pci_addr, range.cpu_addr,
+ range.size, range.flags
+
+ alternatively obtain a struct resource, e.g.:
+ struct resource res;
+ of_pci_range_to_resource(&range, np, &res);
+ */
+ }
+
+Additionally the implementation takes care of adjacent ranges and merges them
+into a single range (as was the case with powerpc and microblaze).
+
+Signed-off-by: Andrew Murray <Andrew.Murray@arm.com>
+Signed-off-by: Liviu Dudau <Liviu.Dudau@arm.com>
+Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
+Reviewed-by: Rob Herring <rob.herring@calxeda.com>
+Tested-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
+Tested-by: Linus Walleij <linus.walleij@linaro.org>
+Tested-by: Jingoo Han <jg1.han@samsung.com>
+Acked-by: Grant Likely <grant.likely@secretlab.ca>
+---
+ drivers/of/address.c | 67 ++++++++++++++++++++++++++++++++++++++++++++++
+ include/linux/of_address.h | 48 +++++++++++++++++++++++++++++++++
+ 2 files changed, 115 insertions(+)
+
+diff --git a/drivers/of/address.c b/drivers/of/address.c
+index 7c8221d..b55c218 100644
+--- a/drivers/of/address.c
++++ b/drivers/of/address.c
+@@ -231,6 +231,73 @@ int of_pci_address_to_resource(struct device_node *dev, int bar,
+ return __of_address_to_resource(dev, addrp, size, flags, NULL, r);
+ }
+ EXPORT_SYMBOL_GPL(of_pci_address_to_resource);
++
++int of_pci_range_parser_init(struct of_pci_range_parser *parser,
++ struct device_node *node)
++{
++ const int na = 3, ns = 2;
++ int rlen;
++
++ parser->node = node;
++ parser->pna = of_n_addr_cells(node);
++ parser->np = parser->pna + na + ns;
++
++ parser->range = of_get_property(node, "ranges", &rlen);
++ if (parser->range == NULL)
++ return -ENOENT;
++
++ parser->end = parser->range + rlen / sizeof(__be32);
++
++ return 0;
++}
++EXPORT_SYMBOL_GPL(of_pci_range_parser_init);
++
++struct of_pci_range *of_pci_range_parser_one(struct of_pci_range_parser *parser,
++ struct of_pci_range *range)
++{
++ const int na = 3, ns = 2;
++
++ if (!range)
++ return NULL;
++
++ if (!parser->range || parser->range + parser->np > parser->end)
++ return NULL;
++
++ range->pci_space = parser->range[0];
++ range->flags = of_bus_pci_get_flags(parser->range);
++ range->pci_addr = of_read_number(parser->range + 1, ns);
++ range->cpu_addr = of_translate_address(parser->node,
++ parser->range + na);
++ range->size = of_read_number(parser->range + parser->pna + na, ns);
++
++ parser->range += parser->np;
++
++ /* Now consume following elements while they are contiguous */
++ while (parser->range + parser->np <= parser->end) {
++ u32 flags, pci_space;
++ u64 pci_addr, cpu_addr, size;
++
++ pci_space = be32_to_cpup(parser->range);
++ flags = of_bus_pci_get_flags(parser->range);
++ pci_addr = of_read_number(parser->range + 1, ns);
++ cpu_addr = of_translate_address(parser->node,
++ parser->range + na);
++ size = of_read_number(parser->range + parser->pna + na, ns);
++
++ if (flags != range->flags)
++ break;
++ if (pci_addr != range->pci_addr + range->size ||
++ cpu_addr != range->cpu_addr + range->size)
++ break;
++
++ range->size += size;
++ parser->range += parser->np;
++ }
++
++ return range;
++}
++EXPORT_SYMBOL_GPL(of_pci_range_parser_one);
++
+ #endif /* CONFIG_PCI */
+
+ /*
+diff --git a/include/linux/of_address.h b/include/linux/of_address.h
+index 0506eb5..4c2e6f2 100644
+--- a/include/linux/of_address.h
++++ b/include/linux/of_address.h
+@@ -4,6 +4,36 @@
+ #include <linux/errno.h>
+ #include <linux/of.h>
+
++struct of_pci_range_parser {
++ struct device_node *node;
++ const __be32 *range;
++ const __be32 *end;
++ int np;
++ int pna;
++};
++
++struct of_pci_range {
++ u32 pci_space;
++ u64 pci_addr;
++ u64 cpu_addr;
++ u64 size;
++ u32 flags;
++};
++
++#define for_each_of_pci_range(parser, range) \
++ for (; of_pci_range_parser_one(parser, range);)
++
++static inline void of_pci_range_to_resource(struct of_pci_range *range,
++ struct device_node *np,
++ struct resource *res)
++{
++ res->flags = range->flags;
++ res->start = range->cpu_addr;
++ res->end = range->cpu_addr + range->size - 1;
++ res->parent = res->child = res->sibling = NULL;
++ res->name = np->full_name;
++}
++
+ #ifdef CONFIG_OF_ADDRESS
+ extern u64 of_translate_address(struct device_node *np, const __be32 *addr);
+ extern bool of_can_translate_address(struct device_node *dev);
+@@ -27,6 +57,11 @@ static inline unsigned long pci_address_to_pio(phys_addr_t addr) { return -1; }
+ #define pci_address_to_pio pci_address_to_pio
+ #endif
+
++extern int of_pci_range_parser_init(struct of_pci_range_parser *parser,
++ struct device_node *node);
++extern struct of_pci_range *of_pci_range_parser_one(
++ struct of_pci_range_parser *parser,
++ struct of_pci_range *range);
+ #else /* CONFIG_OF_ADDRESS */
+ #ifndef of_address_to_resource
+ static inline int of_address_to_resource(struct device_node *dev, int index,
+@@ -53,6 +88,19 @@ static inline const __be32 *of_get_address(struct device_node *dev, int index,
+ {
+ return NULL;
+ }
++
++static inline int of_pci_range_parser_init(struct of_pci_range_parser *parser,
++ struct device_node *node)
++{
++ return -1;
++}
++
++static inline struct of_pci_range *of_pci_range_parser_one(
++ struct of_pci_range_parser *parser,
++ struct of_pci_range *range)
++{
++ return NULL;
++}
+ #endif /* CONFIG_OF_ADDRESS */
+
+
+--
+1.8.4.rc1
+
--- /dev/null
+From 6275a8e0bacac9702350b6a003470a9ce67c9139 Mon Sep 17 00:00:00 2001
+From: Thierry Reding <thierry.reding@avionic-design.de>
+Date: Mon, 11 Feb 2013 09:22:20 +0100
+Subject: [PATCH 03/29] of/pci: Add of_pci_parse_bus_range() function
+
+This function can be used to parse a bus-range property as specified by
+device nodes representing PCI bridges.
+
+Signed-off-by: Thierry Reding <thierry.reding@avionic-design.de>
+---
+ drivers/of/of_pci.c | 25 +++++++++++++++++++++++++
+ include/linux/of_pci.h | 1 +
+ 2 files changed, 26 insertions(+)
+
+diff --git a/drivers/of/of_pci.c b/drivers/of/of_pci.c
+index 4dd7b9b..42c687a 100644
+--- a/drivers/of/of_pci.c
++++ b/drivers/of/of_pci.c
+@@ -64,3 +64,28 @@ int of_pci_get_devfn(struct device_node *np)
+ return (be32_to_cpup(reg) >> 8) & 0xff;
+ }
+ EXPORT_SYMBOL_GPL(of_pci_get_devfn);
++
++/**
++ * of_pci_parse_bus_range() - parse the bus-range property of a PCI device
++ * @node: device node
++ * @res: address to a struct resource to return the bus-range
++ *
++ * Returns 0 on success or a negative error-code on failure.
++ */
++int of_pci_parse_bus_range(struct device_node *node, struct resource *res)
++{
++ const __be32 *values;
++ int len;
++
++ values = of_get_property(node, "bus-range", &len);
++ if (!values || len < sizeof(*values) * 2)
++ return -EINVAL;
++
++ res->name = node->name;
++ res->start = be32_to_cpup(values++);
++ res->end = be32_to_cpup(values);
++ res->flags = IORESOURCE_BUS;
++
++ return 0;
++}
++EXPORT_SYMBOL_GPL(of_pci_parse_bus_range);
+diff --git a/include/linux/of_pci.h b/include/linux/of_pci.h
+index 91ec484..7a04826 100644
+--- a/include/linux/of_pci.h
++++ b/include/linux/of_pci.h
+@@ -11,5 +11,6 @@ struct device_node;
+ struct device_node *of_pci_find_child_device(struct device_node *parent,
+ unsigned int devfn);
+ int of_pci_get_devfn(struct device_node *np);
++int of_pci_parse_bus_range(struct device_node *node, struct resource *res);
+
+ #endif
+--
+1.8.4.rc1
+
--- /dev/null
+From adebeab033de18cabf880f98d2167095520243f2 Mon Sep 17 00:00:00 2001
+From: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
+Date: Fri, 7 Dec 2012 20:35:20 +0100
+Subject: [PATCH 04/29] clk: mvebu: create parent-child relation for PCIe
+ clocks on Armada 370
+
+The Armada 370 has two gatable clocks for each PCIe interface, and we
+want both of them to be enabled. We therefore make one of the two
+clocks a child of the other, as we did for the sataX and sataXlnk
+clocks on Armada XP.
+
+Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
+Cc: Mike Turquette <mturquette@linaro.org>
+---
+ drivers/clk/mvebu/clk-gating-ctrl.c | 4 ++--
+ 1 file changed, 2 insertions(+), 2 deletions(-)
+
+diff --git a/drivers/clk/mvebu/clk-gating-ctrl.c b/drivers/clk/mvebu/clk-gating-ctrl.c
+index ebf141d..b35785a 100644
+--- a/drivers/clk/mvebu/clk-gating-ctrl.c
++++ b/drivers/clk/mvebu/clk-gating-ctrl.c
+@@ -119,8 +119,8 @@ static const struct mvebu_soc_descr __initconst armada_370_gating_descr[] = {
+ { "pex1_en", NULL, 2 },
+ { "ge1", NULL, 3 },
+ { "ge0", NULL, 4 },
+- { "pex0", NULL, 5 },
+- { "pex1", NULL, 9 },
++ { "pex0", "pex0_en", 5 },
++ { "pex1", "pex1_en", 9 },
+ { "sata0", NULL, 15 },
+ { "sdio", NULL, 17 },
+ { "tdm", NULL, 25 },
+--
+1.8.4.rc1
+
--- /dev/null
+From 7bda5e7704872a2f01a6c980bb7616d689520ea5 Mon Sep 17 00:00:00 2001
+From: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
+Date: Fri, 18 Jan 2013 16:42:01 +0100
+Subject: [PATCH 05/29] clk: mvebu: add more PCIe clocks for Armada XP
+
+The current revision of the datasheet only mentions the gatable clocks
+for the PCIe 0.0, 0.1, 0.2 and 0.3 interfaces, and forgot to mention
+the ones for the PCIe 1.0, 1.1, 1.2, 1.3, 2.0 and 3.0
+interfaces. After confirmation with Marvell engineers, this patch adds
+the missing gatable clocks for those PCIe interfaces.
+
+It also changes the name of the previously existing PCIe gatable
+clocks, in order to match the naming using the datasheets.
+
+Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
+Cc: Mike Turquette <mturquette@linaro.org>
+---
+ drivers/clk/mvebu/clk-gating-ctrl.c | 14 ++++++++++----
+ 1 file changed, 10 insertions(+), 4 deletions(-)
+
+diff --git a/drivers/clk/mvebu/clk-gating-ctrl.c b/drivers/clk/mvebu/clk-gating-ctrl.c
+index b35785a..2f03723 100644
+--- a/drivers/clk/mvebu/clk-gating-ctrl.c
++++ b/drivers/clk/mvebu/clk-gating-ctrl.c
+@@ -137,10 +137,14 @@ static const struct mvebu_soc_descr __initconst armada_xp_gating_descr[] = {
+ { "ge2", NULL, 2 },
+ { "ge1", NULL, 3 },
+ { "ge0", NULL, 4 },
+- { "pex0", NULL, 5 },
+- { "pex1", NULL, 6 },
+- { "pex2", NULL, 7 },
+- { "pex3", NULL, 8 },
++ { "pex00", NULL, 5 },
++ { "pex01", NULL, 6 },
++ { "pex02", NULL, 7 },
++ { "pex03", NULL, 8 },
++ { "pex10", NULL, 9 },
++ { "pex11", NULL, 10 },
++ { "pex12", NULL, 11 },
++ { "pex13", NULL, 12 },
+ { "bp", NULL, 13 },
+ { "sata0lnk", NULL, 14 },
+ { "sata0", "sata0lnk", 15 },
+@@ -152,6 +156,8 @@ static const struct mvebu_soc_descr __initconst armada_xp_gating_descr[] = {
+ { "xor0", NULL, 22 },
+ { "crypto", NULL, 23 },
+ { "tdm", NULL, 25 },
++ { "pex20", NULL, 26 },
++ { "pex30", NULL, 27 },
+ { "xor1", NULL, 28 },
+ { "sata1lnk", NULL, 29 },
+ { "sata1", "sata1lnk", 30 },
+--
+1.8.4.rc1
+
--- /dev/null
+From b18ed8465d6c2e3b7057d5bb2fc3da5cb15e3fb1 Mon Sep 17 00:00:00 2001
+From: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
+Date: Fri, 18 Jan 2013 17:42:58 +0100
+Subject: [PATCH 06/29] pci: PCIe driver for Marvell Armada 370/XP systems
+
+This driver implements the support for the PCIe interfaces on the
+Marvell Armada 370/XP ARM SoCs. In the future, it might be extended to
+cover earlier families of Marvell SoCs, such as Dove, Orion and
+Kirkwood.
+
+The driver implements the hw_pci operations needed by the core ARM PCI
+code to setup PCI devices and get their corresponding IRQs, and the
+pci_ops operations that are used by the PCI core to read/write the
+configuration space of PCI devices.
+
+Since the PCIe interfaces of Marvell SoCs are completely separate and
+not linked together in a bus, this driver sets up an emulated PCI host
+bridge, with one PCI-to-PCI bridge as child for each hardware PCIe
+interface.
+
+In addition, this driver enumerates the different PCIe slots, and for
+those having a device plugged in, it sets up the necessary address
+decoding windows, using the mvebu-mbus driver.
+
+Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
+Acked-by: Bjorn Helgaas <bhelgaas@google.com>
+---
+ .../devicetree/bindings/pci/mvebu-pci.txt | 220 ++++++
+ drivers/pci/Kconfig | 2 +
+ drivers/pci/Makefile | 3 +
+ drivers/pci/host/Kconfig | 8 +
+ drivers/pci/host/Makefile | 1 +
+ drivers/pci/host/pci-mvebu.c | 879 +++++++++++++++++++++
+ 6 files changed, 1113 insertions(+)
+ create mode 100644 Documentation/devicetree/bindings/pci/mvebu-pci.txt
+ create mode 100644 drivers/pci/host/Kconfig
+ create mode 100644 drivers/pci/host/Makefile
+ create mode 100644 drivers/pci/host/pci-mvebu.c
+
+diff --git a/Documentation/devicetree/bindings/pci/mvebu-pci.txt b/Documentation/devicetree/bindings/pci/mvebu-pci.txt
+new file mode 100644
+index 0000000..eb69d92
+--- /dev/null
++++ b/Documentation/devicetree/bindings/pci/mvebu-pci.txt
+@@ -0,0 +1,220 @@
++* Marvell EBU PCIe interfaces
++
++Mandatory properties:
++- compatible: one of the following values:
++ marvell,armada-370-pcie
++ marvell,armada-xp-pcie
++- #address-cells, set to <3>
++- #size-cells, set to <2>
++- #interrupt-cells, set to <1>
++- bus-range: PCI bus numbers covered
++- device_type, set to "pci"
++- ranges: ranges for the PCI memory and I/O regions, as well as the
++ MMIO registers to control the PCIe interfaces.
++
++In addition, the Device Tree node must have sub-nodes describing each
++PCIe interface, having the following mandatory properties:
++- reg: used only for interrupt mapping, so only the first four bytes
++ are used to refer to the correct bus number and device number.
++- assigned-addresses: reference to the MMIO registers used to control
++ this PCIe interface.
++- clocks: the clock associated to this PCIe interface
++- marvell,pcie-port: the physical PCIe port number
++- status: either "disabled" or "okay"
++- device_type, set to "pci"
++- #address-cells, set to <3>
++- #size-cells, set to <2>
++- #interrupt-cells, set to <1>
++- ranges, empty property.
++- interrupt-map-mask and interrupt-map, standard PCI properties to
++ define the mapping of the PCIe interface to interrupt numbers.
++
++and the following optional properties:
++- marvell,pcie-lane: the physical PCIe lane number, for ports having
++ multiple lanes. If this property is not found, we assume that the
++ value is 0.
++
++Example:
++
++pcie-controller {
++ compatible = "marvell,armada-xp-pcie";
++ status = "disabled";
++ device_type = "pci";
++
++ #address-cells = <3>;
++ #size-cells = <2>;
++
++ bus-range = <0x00 0xff>;
++
++ ranges = <0x82000000 0 0xd0040000 0xd0040000 0 0x00002000 /* Port 0.0 registers */
++ 0x82000000 0 0xd0042000 0xd0042000 0 0x00002000 /* Port 2.0 registers */
++ 0x82000000 0 0xd0044000 0xd0044000 0 0x00002000 /* Port 0.1 registers */
++ 0x82000000 0 0xd0048000 0xd0048000 0 0x00002000 /* Port 0.2 registers */
++ 0x82000000 0 0xd004c000 0xd004c000 0 0x00002000 /* Port 0.3 registers */
++ 0x82000000 0 0xd0080000 0xd0080000 0 0x00002000 /* Port 1.0 registers */
++ 0x82000000 0 0xd0082000 0xd0082000 0 0x00002000 /* Port 3.0 registers */
++ 0x82000000 0 0xd0084000 0xd0084000 0 0x00002000 /* Port 1.1 registers */
++ 0x82000000 0 0xd0088000 0xd0088000 0 0x00002000 /* Port 1.2 registers */
++ 0x82000000 0 0xd008c000 0xd008c000 0 0x00002000 /* Port 1.3 registers */
++ 0x82000000 0 0xe0000000 0xe0000000 0 0x08000000 /* non-prefetchable memory */
++ 0x81000000 0 0 0xe8000000 0 0x00100000>; /* downstream I/O */
++
++ pcie@1,0 {
++ device_type = "pci";
++ assigned-addresses = <0x82000800 0 0xd0040000 0 0x2000>;
++ reg = <0x0800 0 0 0 0>;
++ #address-cells = <3>;
++ #size-cells = <2>;
++ #interrupt-cells = <1>;
++ ranges;
++ interrupt-map-mask = <0 0 0 0>;
++ interrupt-map = <0 0 0 0 &mpic 58>;
++ marvell,pcie-port = <0>;
++ marvell,pcie-lane = <0>;
++ clocks = <&gateclk 5>;
++ status = "disabled";
++ };
++
++ pcie@2,0 {
++ device_type = "pci";
++ assigned-addresses = <0x82001000 0 0xd0044000 0 0x2000>;
++ reg = <0x1000 0 0 0 0>;
++ #address-cells = <3>;
++ #size-cells = <2>;
++ #interrupt-cells = <1>;
++ ranges;
++ interrupt-map-mask = <0 0 0 0>;
++ interrupt-map = <0 0 0 0 &mpic 59>;
++ marvell,pcie-port = <0>;
++ marvell,pcie-lane = <1>;
++ clocks = <&gateclk 6>;
++ status = "disabled";
++ };
++
++ pcie@3,0 {
++ device_type = "pci";
++ assigned-addresses = <0x82001800 0 0xd0048000 0 0x2000>;
++ reg = <0x1800 0 0 0 0>;
++ #address-cells = <3>;
++ #size-cells = <2>;
++ #interrupt-cells = <1>;
++ ranges;
++ interrupt-map-mask = <0 0 0 0>;
++ interrupt-map = <0 0 0 0 &mpic 60>;
++ marvell,pcie-port = <0>;
++ marvell,pcie-lane = <2>;
++ clocks = <&gateclk 7>;
++ status = "disabled";
++ };
++
++ pcie@4,0 {
++ device_type = "pci";
++ assigned-addresses = <0x82002000 0 0xd004c000 0 0x2000>;
++ reg = <0x2000 0 0 0 0>;
++ #address-cells = <3>;
++ #size-cells = <2>;
++ #interrupt-cells = <1>;
++ ranges;
++ interrupt-map-mask = <0 0 0 0>;
++ interrupt-map = <0 0 0 0 &mpic 61>;
++ marvell,pcie-port = <0>;
++ marvell,pcie-lane = <3>;
++ clocks = <&gateclk 8>;
++ status = "disabled";
++ };
++
++ pcie@5,0 {
++ device_type = "pci";
++ assigned-addresses = <0x82002800 0 0xd0080000 0 0x2000>;
++ reg = <0x2800 0 0 0 0>;
++ #address-cells = <3>;
++ #size-cells = <2>;
++ #interrupt-cells = <1>;
++ ranges;
++ interrupt-map-mask = <0 0 0 0>;
++ interrupt-map = <0 0 0 0 &mpic 62>;
++ marvell,pcie-port = <1>;
++ marvell,pcie-lane = <0>;
++ clocks = <&gateclk 9>;
++ status = "disabled";
++ };
++
++ pcie@6,0 {
++ device_type = "pci";
++ assigned-addresses = <0x82003000 0 0xd0084000 0 0x2000>;
++ reg = <0x3000 0 0 0 0>;
++ #address-cells = <3>;
++ #size-cells = <2>;
++ #interrupt-cells = <1>;
++ ranges;
++ interrupt-map-mask = <0 0 0 0>;
++ interrupt-map = <0 0 0 0 &mpic 63>;
++ marvell,pcie-port = <1>;
++ marvell,pcie-lane = <1>;
++ clocks = <&gateclk 10>;
++ status = "disabled";
++ };
++
++ pcie@7,0 {
++ device_type = "pci";
++ assigned-addresses = <0x82003800 0 0xd0088000 0 0x2000>;
++ reg = <0x3800 0 0 0 0>;
++ #address-cells = <3>;
++ #size-cells = <2>;
++ #interrupt-cells = <1>;
++ ranges;
++ interrupt-map-mask = <0 0 0 0>;
++ interrupt-map = <0 0 0 0 &mpic 64>;
++ marvell,pcie-port = <1>;
++ marvell,pcie-lane = <2>;
++ clocks = <&gateclk 11>;
++ status = "disabled";
++ };
++
++ pcie@8,0 {
++ device_type = "pci";
++ assigned-addresses = <0x82004000 0 0xd008c000 0 0x2000>;
++ reg = <0x4000 0 0 0 0>;
++ #address-cells = <3>;
++ #size-cells = <2>;
++ #interrupt-cells = <1>;
++ ranges;
++ interrupt-map-mask = <0 0 0 0>;
++ interrupt-map = <0 0 0 0 &mpic 65>;
++ marvell,pcie-port = <1>;
++ marvell,pcie-lane = <3>;
++ clocks = <&gateclk 12>;
++ status = "disabled";
++ };
++ pcie@9,0 {
++ device_type = "pci";
++ assigned-addresses = <0x82004800 0 0xd0042000 0 0x2000>;
++ reg = <0x4800 0 0 0 0>;
++ #address-cells = <3>;
++ #size-cells = <2>;
++ #interrupt-cells = <1>;
++ ranges;
++ interrupt-map-mask = <0 0 0 0>;
++ interrupt-map = <0 0 0 0 &mpic 99>;
++ marvell,pcie-port = <2>;
++ marvell,pcie-lane = <0>;
++ clocks = <&gateclk 26>;
++ status = "disabled";
++ };
++
++ pcie@10,0 {
++ device_type = "pci";
++ assigned-addresses = <0x82005000 0 0xd0082000 0 0x2000>;
++ reg = <0x5000 0 0 0 0>;
++ #address-cells = <3>;
++ #size-cells = <2>;
++ #interrupt-cells = <1>;
++ ranges;
++ interrupt-map-mask = <0 0 0 0>;
++ interrupt-map = <0 0 0 0 &mpic 103>;
++ marvell,pcie-port = <3>;
++ marvell,pcie-lane = <0>;
++ clocks = <&gateclk 27>;
++ status = "disabled";
++ };
++};
+diff --git a/drivers/pci/Kconfig b/drivers/pci/Kconfig
+index 6d51aa6..ac45398 100644
+--- a/drivers/pci/Kconfig
++++ b/drivers/pci/Kconfig
+@@ -119,3 +119,5 @@ config PCI_IOAPIC
+ config PCI_LABEL
+ def_bool y if (DMI || ACPI)
+ select NLS
++
++source "drivers/pci/host/Kconfig"
+diff --git a/drivers/pci/Makefile b/drivers/pci/Makefile
+index 0c3efcf..6ebf5bf 100644
+--- a/drivers/pci/Makefile
++++ b/drivers/pci/Makefile
+@@ -67,3 +67,6 @@ obj-$(CONFIG_XEN_PCIDEV_FRONTEND) += xen-pcifront.o
+ obj-$(CONFIG_OF) += of.o
+
+ ccflags-$(CONFIG_PCI_DEBUG) := -DDEBUG
++
++# PCI host controller drivers
++obj-y += host/
+diff --git a/drivers/pci/host/Kconfig b/drivers/pci/host/Kconfig
+new file mode 100644
+index 0000000..6918fbc
+--- /dev/null
++++ b/drivers/pci/host/Kconfig
+@@ -0,0 +1,8 @@
++menu "PCI host controller drivers"
++ depends on PCI
++
++config PCI_MVEBU
++ bool "Marvell EBU PCIe controller"
++ depends on ARCH_MVEBU
++
++endmenu
+diff --git a/drivers/pci/host/Makefile b/drivers/pci/host/Makefile
+new file mode 100644
+index 0000000..5ea2d8b
+--- /dev/null
++++ b/drivers/pci/host/Makefile
+@@ -0,0 +1 @@
++obj-$(CONFIG_PCI_MVEBU) += pci-mvebu.o
+diff --git a/drivers/pci/host/pci-mvebu.c b/drivers/pci/host/pci-mvebu.c
+new file mode 100644
+index 0000000..b0ee63b
+--- /dev/null
++++ b/drivers/pci/host/pci-mvebu.c
+@@ -0,0 +1,879 @@
++/*
++ * PCIe driver for Marvell Armada 370 and Armada XP SoCs
++ *
++ * This file is licensed under the terms of the GNU General Public
++ * License version 2. This program is licensed "as is" without any
++ * warranty of any kind, whether express or implied.
++ */
++
++#include <linux/kernel.h>
++#include <linux/pci.h>
++#include <linux/clk.h>
++#include <linux/module.h>
++#include <linux/mbus.h>
++#include <linux/slab.h>
++#include <linux/platform_device.h>
++#include <linux/of_address.h>
++#include <linux/of_pci.h>
++#include <linux/of_irq.h>
++#include <linux/of_platform.h>
++
++/*
++ * PCIe unit register offsets.
++ */
++#define PCIE_DEV_ID_OFF 0x0000
++#define PCIE_CMD_OFF 0x0004
++#define PCIE_DEV_REV_OFF 0x0008
++#define PCIE_BAR_LO_OFF(n) (0x0010 + ((n) << 3))
++#define PCIE_BAR_HI_OFF(n) (0x0014 + ((n) << 3))
++#define PCIE_HEADER_LOG_4_OFF 0x0128
++#define PCIE_BAR_CTRL_OFF(n) (0x1804 + (((n) - 1) * 4))
++#define PCIE_WIN04_CTRL_OFF(n) (0x1820 + ((n) << 4))
++#define PCIE_WIN04_BASE_OFF(n) (0x1824 + ((n) << 4))
++#define PCIE_WIN04_REMAP_OFF(n) (0x182c + ((n) << 4))
++#define PCIE_WIN5_CTRL_OFF 0x1880
++#define PCIE_WIN5_BASE_OFF 0x1884
++#define PCIE_WIN5_REMAP_OFF 0x188c
++#define PCIE_CONF_ADDR_OFF 0x18f8
++#define PCIE_CONF_ADDR_EN 0x80000000
++#define PCIE_CONF_REG(r) ((((r) & 0xf00) << 16) | ((r) & 0xfc))
++#define PCIE_CONF_BUS(b) (((b) & 0xff) << 16)
++#define PCIE_CONF_DEV(d) (((d) & 0x1f) << 11)
++#define PCIE_CONF_FUNC(f) (((f) & 0x7) << 8)
++#define PCIE_CONF_ADDR(bus, devfn, where) \
++ (PCIE_CONF_BUS(bus) | PCIE_CONF_DEV(PCI_SLOT(devfn)) | \
++ PCIE_CONF_FUNC(PCI_FUNC(devfn)) | PCIE_CONF_REG(where) | \
++ PCIE_CONF_ADDR_EN)
++#define PCIE_CONF_DATA_OFF 0x18fc
++#define PCIE_MASK_OFF 0x1910
++#define PCIE_MASK_ENABLE_INTS 0x0f000000
++#define PCIE_CTRL_OFF 0x1a00
++#define PCIE_CTRL_X1_MODE 0x0001
++#define PCIE_STAT_OFF 0x1a04
++#define PCIE_STAT_BUS 0xff00
++#define PCIE_STAT_LINK_DOWN BIT(0)
++#define PCIE_DEBUG_CTRL 0x1a60
++#define PCIE_DEBUG_SOFT_RESET BIT(20)
++
++/*
++ * This product ID is registered by Marvell, and used when the Marvell
++ * SoC is not the root complex, but an endpoint on the PCIe bus. It is
++ * therefore safe to re-use this PCI ID for our emulated PCI-to-PCI
++ * bridge.
++ */
++#define MARVELL_EMULATED_PCI_PCI_BRIDGE_ID 0x7846
++
++/* PCI configuration space of a PCI-to-PCI bridge */
++struct mvebu_sw_pci_bridge {
++ u16 vendor;
++ u16 device;
++ u16 command;
++ u16 status;
++ u16 class;
++ u8 interface;
++ u8 revision;
++ u8 bist;
++ u8 header_type;
++ u8 latency_timer;
++ u8 cache_line_size;
++ u32 bar[2];
++ u8 primary_bus;
++ u8 secondary_bus;
++ u8 subordinate_bus;
++ u8 secondary_latency_timer;
++ u8 iobase;
++ u8 iolimit;
++ u16 secondary_status;
++ u16 membase;
++ u16 memlimit;
++ u16 prefmembase;
++ u16 prefmemlimit;
++ u32 prefbaseupper;
++ u32 preflimitupper;
++ u16 iobaseupper;
++ u16 iolimitupper;
++ u8 cappointer;
++ u8 reserved1;
++ u16 reserved2;
++ u32 romaddr;
++ u8 intline;
++ u8 intpin;
++ u16 bridgectrl;
++};
++
++struct mvebu_pcie_port;
++
++/* Structure representing all PCIe interfaces */
++struct mvebu_pcie {
++ struct platform_device *pdev;
++ struct mvebu_pcie_port *ports;
++ struct resource io;
++ struct resource realio;
++ struct resource mem;
++ struct resource busn;
++ int nports;
++};
++
++/* Structure representing one PCIe interface */
++struct mvebu_pcie_port {
++ char *name;
++ void __iomem *base;
++ spinlock_t conf_lock;
++ int haslink;
++ u32 port;
++ u32 lane;
++ int devfn;
++ struct clk *clk;
++ struct mvebu_sw_pci_bridge bridge;
++ struct device_node *dn;
++ struct mvebu_pcie *pcie;
++ phys_addr_t memwin_base;
++ size_t memwin_size;
++ phys_addr_t iowin_base;
++ size_t iowin_size;
++};
++
++static bool mvebu_pcie_link_up(struct mvebu_pcie_port *port)
++{
++ return !(readl(port->base + PCIE_STAT_OFF) & PCIE_STAT_LINK_DOWN);
++}
++
++static void mvebu_pcie_set_local_bus_nr(struct mvebu_pcie_port *port, int nr)
++{
++ u32 stat;
++
++ stat = readl(port->base + PCIE_STAT_OFF);
++ stat &= ~PCIE_STAT_BUS;
++ stat |= nr << 8;
++ writel(stat, port->base + PCIE_STAT_OFF);
++}
++
++/*
++ * Setup PCIE BARs and Address Decode Wins:
++ * BAR[0,2] -> disabled, BAR[1] -> covers all DRAM banks
++ * WIN[0-3] -> DRAM bank[0-3]
++ */
++static void __init mvebu_pcie_setup_wins(struct mvebu_pcie_port *port)
++{
++ const struct mbus_dram_target_info *dram;
++ u32 size;
++ int i;
++
++ dram = mv_mbus_dram_info();
++
++ /* First, disable and clear BARs and windows. */
++ for (i = 1; i < 3; i++) {
++ writel(0, port->base + PCIE_BAR_CTRL_OFF(i));
++ writel(0, port->base + PCIE_BAR_LO_OFF(i));
++ writel(0, port->base + PCIE_BAR_HI_OFF(i));
++ }
++
++ for (i = 0; i < 5; i++) {
++ writel(0, port->base + PCIE_WIN04_CTRL_OFF(i));
++ writel(0, port->base + PCIE_WIN04_BASE_OFF(i));
++ writel(0, port->base + PCIE_WIN04_REMAP_OFF(i));
++ }
++
++ writel(0, port->base + PCIE_WIN5_CTRL_OFF);
++ writel(0, port->base + PCIE_WIN5_BASE_OFF);
++ writel(0, port->base + PCIE_WIN5_REMAP_OFF);
++
++ /* Setup windows for DDR banks. Count total DDR size on the fly. */
++ size = 0;
++ for (i = 0; i < dram->num_cs; i++) {
++ const struct mbus_dram_window *cs = dram->cs + i;
++
++ writel(cs->base & 0xffff0000,
++ port->base + PCIE_WIN04_BASE_OFF(i));
++ writel(0, port->base + PCIE_WIN04_REMAP_OFF(i));
++ writel(((cs->size - 1) & 0xffff0000) |
++ (cs->mbus_attr << 8) |
++ (dram->mbus_dram_target_id << 4) | 1,
++ port->base + PCIE_WIN04_CTRL_OFF(i));
++
++ size += cs->size;
++ }
++
++ /* Round up 'size' to the nearest power of two. */
++ if ((size & (size - 1)) != 0)
++ size = 1 << fls(size);
++
++ /* Setup BAR[1] to all DRAM banks. */
++ writel(dram->cs[0].base, port->base + PCIE_BAR_LO_OFF(1));
++ writel(0, port->base + PCIE_BAR_HI_OFF(1));
++ writel(((size - 1) & 0xffff0000) | 1,
++ port->base + PCIE_BAR_CTRL_OFF(1));
++}
++
++static void __init mvebu_pcie_setup_hw(struct mvebu_pcie_port *port)
++{
++ u16 cmd;
++ u32 mask;
++
++ /* Point PCIe unit MBUS decode windows to DRAM space. */
++ mvebu_pcie_setup_wins(port);
++
++ /* Master + slave enable. */
++ cmd = readw(port->base + PCIE_CMD_OFF);
++ cmd |= PCI_COMMAND_IO;
++ cmd |= PCI_COMMAND_MEMORY;
++ cmd |= PCI_COMMAND_MASTER;
++ writew(cmd, port->base + PCIE_CMD_OFF);
++
++ /* Enable interrupt lines A-D. */
++ mask = readl(port->base + PCIE_MASK_OFF);
++ mask |= PCIE_MASK_ENABLE_INTS;
++ writel(mask, port->base + PCIE_MASK_OFF);
++}
++
++static int mvebu_pcie_hw_rd_conf(struct mvebu_pcie_port *port,
++ struct pci_bus *bus,
++ u32 devfn, int where, int size, u32 *val)
++{
++ writel(PCIE_CONF_ADDR(bus->number, devfn, where),
++ port->base + PCIE_CONF_ADDR_OFF);
++
++ *val = readl(port->base + PCIE_CONF_DATA_OFF);
++
++ if (size == 1)
++ *val = (*val >> (8 * (where & 3))) & 0xff;
++ else if (size == 2)
++ *val = (*val >> (8 * (where & 3))) & 0xffff;
++
++ return PCIBIOS_SUCCESSFUL;
++}
++
++static int mvebu_pcie_hw_wr_conf(struct mvebu_pcie_port *port,
++ struct pci_bus *bus,
++ u32 devfn, int where, int size, u32 val)
++{
++ int ret = PCIBIOS_SUCCESSFUL;
++
++ writel(PCIE_CONF_ADDR(bus->number, devfn, where),
++ port->base + PCIE_CONF_ADDR_OFF);
++
++ if (size == 4)
++ writel(val, port->base + PCIE_CONF_DATA_OFF);
++ else if (size == 2)
++ writew(val, port->base + PCIE_CONF_DATA_OFF + (where & 3));
++ else if (size == 1)
++ writeb(val, port->base + PCIE_CONF_DATA_OFF + (where & 3));
++ else
++ ret = PCIBIOS_BAD_REGISTER_NUMBER;
++
++ return ret;
++}
++
++static void mvebu_pcie_handle_iobase_change(struct mvebu_pcie_port *port)
++{
++ phys_addr_t iobase;
++
++ /* Are the new iobase/iolimit values invalid? */
++ if (port->bridge.iolimit < port->bridge.iobase ||
++ port->bridge.iolimitupper < port->bridge.iobaseupper) {
++
++ /* If a window was configured, remove it */
++ if (port->iowin_base) {
++ mvebu_mbus_del_window(port->iowin_base,
++ port->iowin_size);
++ port->iowin_base = 0;
++ port->iowin_size = 0;
++ }
++
++ return;
++ }
++
++ /*
++ * We read the PCI-to-PCI bridge emulated registers, and
++ * calculate the base address and size of the address decoding
++ * window to setup, according to the PCI-to-PCI bridge
++ * specifications. iobase is the bus address, port->iowin_base
++ * is the CPU address.
++ */
++ iobase = ((port->bridge.iobase & 0xF0) << 8) |
++ (port->bridge.iobaseupper << 16);
++ port->iowin_base = port->pcie->io.start + iobase;
++ port->iowin_size = ((0xFFF | ((port->bridge.iolimit & 0xF0) << 8) |
++ (port->bridge.iolimitupper << 16)) -
++ iobase);
++
++ mvebu_mbus_add_window_remap_flags(port->name, port->iowin_base,
++ port->iowin_size,
++ iobase,
++ MVEBU_MBUS_PCI_IO);
++
++ pci_ioremap_io(iobase, port->iowin_base);
++}
++
++static void mvebu_pcie_handle_membase_change(struct mvebu_pcie_port *port)
++{
++ /* Are the new membase/memlimit values invalid? */
++ if (port->bridge.memlimit < port->bridge.membase) {
++
++ /* If a window was configured, remove it */
++ if (port->memwin_base) {
++ mvebu_mbus_del_window(port->memwin_base,
++ port->memwin_size);
++ port->memwin_base = 0;
++ port->memwin_size = 0;
++ }
++
++ return;
++ }
++
++ /*
++ * We read the PCI-to-PCI bridge emulated registers, and
++ * calculate the base address and size of the address decoding
++ * window to setup, according to the PCI-to-PCI bridge
++ * specifications.
++ */
++ port->memwin_base = ((port->bridge.membase & 0xFFF0) << 16);
++ port->memwin_size =
++ (((port->bridge.memlimit & 0xFFF0) << 16) | 0xFFFFF) -
++ port->memwin_base;
++
++ mvebu_mbus_add_window_remap_flags(port->name, port->memwin_base,
++ port->memwin_size,
++ MVEBU_MBUS_NO_REMAP,
++ MVEBU_MBUS_PCI_MEM);
++}
++
++/*
++ * Initialize the configuration space of the PCI-to-PCI bridge
++ * associated with the given PCIe interface.
++ */
++static void mvebu_sw_pci_bridge_init(struct mvebu_pcie_port *port)
++{
++ struct mvebu_sw_pci_bridge *bridge = &port->bridge;
++
++ memset(bridge, 0, sizeof(struct mvebu_sw_pci_bridge));
++
++ bridge->status = PCI_STATUS_CAP_LIST;
++ bridge->class = PCI_CLASS_BRIDGE_PCI;
++ bridge->vendor = PCI_VENDOR_ID_MARVELL;
++ bridge->device = MARVELL_EMULATED_PCI_PCI_BRIDGE_ID;
++ bridge->header_type = PCI_HEADER_TYPE_BRIDGE;
++ bridge->cache_line_size = 0x10;
++
++ /* We support 32 bits I/O addressing */
++ bridge->iobase = PCI_IO_RANGE_TYPE_32;
++ bridge->iolimit = PCI_IO_RANGE_TYPE_32;
++}
++
++/*
++ * Read the configuration space of the PCI-to-PCI bridge associated to
++ * the given PCIe interface.
++ */
++static int mvebu_sw_pci_bridge_read(struct mvebu_pcie_port *port,
++ unsigned int where, int size, u32 *value)
++{
++ struct mvebu_sw_pci_bridge *bridge = &port->bridge;
++
++ switch (where & ~3) {
++ case PCI_VENDOR_ID:
++ *value = bridge->device << 16 | bridge->vendor;
++ break;
++
++ case PCI_COMMAND:
++ *value = bridge->status << 16 | bridge->command;
++ break;
++
++ case PCI_CLASS_REVISION:
++ *value = bridge->class << 16 | bridge->interface << 8 |
++ bridge->revision;
++ break;
++
++ case PCI_CACHE_LINE_SIZE:
++ *value = bridge->bist << 24 | bridge->header_type << 16 |
++ bridge->latency_timer << 8 | bridge->cache_line_size;
++ break;
++
++ case PCI_BASE_ADDRESS_0 ... PCI_BASE_ADDRESS_1:
++ *value = bridge->bar[((where & ~3) - PCI_BASE_ADDRESS_0) / 4];
++ break;
++
++ case PCI_PRIMARY_BUS:
++ *value = (bridge->secondary_latency_timer << 24 |
++ bridge->subordinate_bus << 16 |
++ bridge->secondary_bus << 8 |
++ bridge->primary_bus);
++ break;
++
++ case PCI_IO_BASE:
++ *value = (bridge->secondary_status << 16 |
++ bridge->iolimit << 8 |
++ bridge->iobase);
++ break;
++
++ case PCI_MEMORY_BASE:
++ *value = (bridge->memlimit << 16 | bridge->membase);
++ break;
++
++ case PCI_PREF_MEMORY_BASE:
++ *value = (bridge->prefmemlimit << 16 | bridge->prefmembase);
++ break;
++
++ case PCI_PREF_BASE_UPPER32:
++ *value = bridge->prefbaseupper;
++ break;
++
++ case PCI_PREF_LIMIT_UPPER32:
++ *value = bridge->preflimitupper;
++ break;
++
++ case PCI_IO_BASE_UPPER16:
++ *value = (bridge->iolimitupper << 16 | bridge->iobaseupper);
++ break;
++
++ case PCI_ROM_ADDRESS1:
++ *value = 0;
++ break;
++
++ default:
++ *value = 0xffffffff;
++ return PCIBIOS_BAD_REGISTER_NUMBER;
++ }
++
++ if (size == 2)
++ *value = (*value >> (8 * (where & 3))) & 0xffff;
++ else if (size == 1)
++ *value = (*value >> (8 * (where & 3))) & 0xff;
++
++ return PCIBIOS_SUCCESSFUL;
++}
++
++/* Write to the PCI-to-PCI bridge configuration space */
++static int mvebu_sw_pci_bridge_write(struct mvebu_pcie_port *port,
++ unsigned int where, int size, u32 value)
++{
++ struct mvebu_sw_pci_bridge *bridge = &port->bridge;
++ u32 mask, reg;
++ int err;
++
++ if (size == 4)
++ mask = 0x0;
++ else if (size == 2)
++ mask = ~(0xffff << ((where & 3) * 8));
++ else if (size == 1)
++ mask = ~(0xff << ((where & 3) * 8));
++ else
++ return PCIBIOS_BAD_REGISTER_NUMBER;
++
++ err = mvebu_sw_pci_bridge_read(port, where & ~3, 4, ®);
++ if (err)
++ return err;
++
++ value = (reg & mask) | value << ((where & 3) * 8);
++
++ switch (where & ~3) {
++ case PCI_COMMAND:
++ bridge->command = value & 0xffff;
++ bridge->status = value >> 16;
++ break;
++
++ case PCI_BASE_ADDRESS_0 ... PCI_BASE_ADDRESS_1:
++ bridge->bar[((where & ~3) - PCI_BASE_ADDRESS_0) / 4] = value;
++ break;
++
++ case PCI_IO_BASE:
++ /*
++ * We also keep bit 1 set, it is a read-only bit that
++ * indicates we support 32 bits addressing for the
++ * I/O
++ */
++ bridge->iobase = (value & 0xff) | PCI_IO_RANGE_TYPE_32;
++ bridge->iolimit = ((value >> 8) & 0xff) | PCI_IO_RANGE_TYPE_32;
++ bridge->secondary_status = value >> 16;
++ mvebu_pcie_handle_iobase_change(port);
++ break;
++
++ case PCI_MEMORY_BASE:
++ bridge->membase = value & 0xffff;
++ bridge->memlimit = value >> 16;
++ mvebu_pcie_handle_membase_change(port);
++ break;
++
++ case PCI_PREF_MEMORY_BASE:
++ bridge->prefmembase = value & 0xffff;
++ bridge->prefmemlimit = value >> 16;
++ break;
++
++ case PCI_PREF_BASE_UPPER32:
++ bridge->prefbaseupper = value;
++ break;
++
++ case PCI_PREF_LIMIT_UPPER32:
++ bridge->preflimitupper = value;
++ break;
++
++ case PCI_IO_BASE_UPPER16:
++ bridge->iobaseupper = value & 0xffff;
++ bridge->iolimitupper = value >> 16;
++ mvebu_pcie_handle_iobase_change(port);
++ break;
++
++ case PCI_PRIMARY_BUS:
++ bridge->primary_bus = value & 0xff;
++ bridge->secondary_bus = (value >> 8) & 0xff;
++ bridge->subordinate_bus = (value >> 16) & 0xff;
++ bridge->secondary_latency_timer = (value >> 24) & 0xff;
++ mvebu_pcie_set_local_bus_nr(port, bridge->secondary_bus);
++ break;
++
++ default:
++ break;
++ }
++
++ return PCIBIOS_SUCCESSFUL;
++}
++
++static inline struct mvebu_pcie *sys_to_pcie(struct pci_sys_data *sys)
++{
++ return sys->private_data;
++}
++
++static struct mvebu_pcie_port *
++mvebu_pcie_find_port(struct mvebu_pcie *pcie, struct pci_bus *bus,
++ int devfn)
++{
++ int i;
++
++ for (i = 0; i < pcie->nports; i++) {
++ struct mvebu_pcie_port *port = &pcie->ports[i];
++ if (bus->number == 0 && port->devfn == devfn)
++ return port;
++ if (bus->number != 0 &&
++ port->bridge.secondary_bus == bus->number)
++ return port;
++ }
++
++ return NULL;
++}
++
++/* PCI configuration space write function */
++static int mvebu_pcie_wr_conf(struct pci_bus *bus, u32 devfn,
++ int where, int size, u32 val)
++{
++ struct mvebu_pcie *pcie = sys_to_pcie(bus->sysdata);
++ struct mvebu_pcie_port *port;
++ unsigned long flags;
++ int ret;
++
++ port = mvebu_pcie_find_port(pcie, bus, devfn);
++ if (!port)
++ return PCIBIOS_DEVICE_NOT_FOUND;
++
++ /* Access the emulated PCI-to-PCI bridge */
++ if (bus->number == 0)
++ return mvebu_sw_pci_bridge_write(port, where, size, val);
++
++ if (!port->haslink || PCI_SLOT(devfn) != 0)
++ return PCIBIOS_DEVICE_NOT_FOUND;
++
++ /* Access the real PCIe interface */
++ spin_lock_irqsave(&port->conf_lock, flags);
++ ret = mvebu_pcie_hw_wr_conf(port, bus,
++ PCI_DEVFN(1, PCI_FUNC(devfn)),
++ where, size, val);
++ spin_unlock_irqrestore(&port->conf_lock, flags);
++
++ return ret;
++}
++
++/* PCI configuration space read function */
++static int mvebu_pcie_rd_conf(struct pci_bus *bus, u32 devfn, int where,
++ int size, u32 *val)
++{
++ struct mvebu_pcie *pcie = sys_to_pcie(bus->sysdata);
++ struct mvebu_pcie_port *port;
++ unsigned long flags;
++ int ret;
++
++ port = mvebu_pcie_find_port(pcie, bus, devfn);
++ if (!port) {
++ *val = 0xffffffff;
++ return PCIBIOS_DEVICE_NOT_FOUND;
++ }
++
++ /* Access the emulated PCI-to-PCI bridge */
++ if (bus->number == 0)
++ return mvebu_sw_pci_bridge_read(port, where, size, val);
++
++ if (!port->haslink || PCI_SLOT(devfn) != 0) {
++ *val = 0xffffffff;
++ return PCIBIOS_DEVICE_NOT_FOUND;
++ }
++
++ /* Access the real PCIe interface */
++ spin_lock_irqsave(&port->conf_lock, flags);
++ ret = mvebu_pcie_hw_rd_conf(port, bus,
++ PCI_DEVFN(1, PCI_FUNC(devfn)),
++ where, size, val);
++ spin_unlock_irqrestore(&port->conf_lock, flags);
++
++ return ret;
++}
++
++static struct pci_ops mvebu_pcie_ops = {
++ .read = mvebu_pcie_rd_conf,
++ .write = mvebu_pcie_wr_conf,
++};
++
++static int __init mvebu_pcie_setup(int nr, struct pci_sys_data *sys)
++{
++ struct mvebu_pcie *pcie = sys_to_pcie(sys);
++ int i;
++
++ pci_add_resource_offset(&sys->resources, &pcie->realio, sys->io_offset);
++ pci_add_resource_offset(&sys->resources, &pcie->mem, sys->mem_offset);
++ pci_add_resource(&sys->resources, &pcie->busn);
++
++ for (i = 0; i < pcie->nports; i++) {
++ struct mvebu_pcie_port *port = &pcie->ports[i];
++ mvebu_pcie_setup_hw(port);
++ }
++
++ return 1;
++}
++
++static int __init mvebu_pcie_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
++{
++ struct of_irq oirq;
++ int ret;
++
++ ret = of_irq_map_pci(dev, &oirq);
++ if (ret)
++ return ret;
++
++ return irq_create_of_mapping(oirq.controller, oirq.specifier,
++ oirq.size);
++}
++
++static struct pci_bus *mvebu_pcie_scan_bus(int nr, struct pci_sys_data *sys)
++{
++ struct mvebu_pcie *pcie = sys_to_pcie(sys);
++ struct pci_bus *bus;
++
++ bus = pci_create_root_bus(&pcie->pdev->dev, sys->busnr,
++ &mvebu_pcie_ops, sys, &sys->resources);
++ if (!bus)
++ return NULL;
++
++ pci_scan_child_bus(bus);
++
++ return bus;
++}
++
++resource_size_t mvebu_pcie_align_resource(struct pci_dev *dev,
++ const struct resource *res,
++ resource_size_t start,
++ resource_size_t size,
++ resource_size_t align)
++{
++ if (dev->bus->number != 0)
++ return start;
++
++ /*
++ * On the PCI-to-PCI bridge side, the I/O windows must have at
++ * least a 64 KB size and be aligned on their size, and the
++ * memory windows must have at least a 1 MB size and be
++ * aligned on their size
++ */
++ if (res->flags & IORESOURCE_IO)
++ return round_up(start, max((resource_size_t)SZ_64K, size));
++ else if (res->flags & IORESOURCE_MEM)
++ return round_up(start, max((resource_size_t)SZ_1M, size));
++ else
++ return start;
++}
++
++static void mvebu_pcie_enable(struct mvebu_pcie *pcie)
++{
++ struct hw_pci hw;
++
++ memset(&hw, 0, sizeof(hw));
++
++ hw.nr_controllers = 1;
++ hw.private_data = (void **)&pcie;
++ hw.setup = mvebu_pcie_setup;
++ hw.scan = mvebu_pcie_scan_bus;
++ hw.map_irq = mvebu_pcie_map_irq;
++ hw.ops = &mvebu_pcie_ops;
++ hw.align_resource = mvebu_pcie_align_resource;
++
++ pci_common_init(&hw);
++}
++
++/*
++ * Looks up the list of register addresses encoded into the reg =
++ * <...> property for one that matches the given port/lane. Once
++ * found, maps it.
++ */
++static void __iomem *mvebu_pcie_map_registers(struct platform_device *pdev,
++ struct device_node *np,
++ struct mvebu_pcie_port *port)
++{
++ struct resource regs;
++ int ret = 0;
++
++ ret = of_address_to_resource(np, 0, ®s);
++ if (ret)
++ return NULL;
++
++ return devm_request_and_ioremap(&pdev->dev, ®s);
++}
++
++static int __init mvebu_pcie_probe(struct platform_device *pdev)
++{
++ struct mvebu_pcie *pcie;
++ struct device_node *np = pdev->dev.of_node;
++ struct of_pci_range range;
++ struct of_pci_range_parser parser;
++ struct device_node *child;
++ int i, ret;
++
++ pcie = devm_kzalloc(&pdev->dev, sizeof(struct mvebu_pcie),
++ GFP_KERNEL);
++ if (!pcie)
++ return -ENOMEM;
++
++ pcie->pdev = pdev;
++
++ if (of_pci_range_parser_init(&parser, np))
++ return -EINVAL;
++
++ /* Get the I/O and memory ranges from DT */
++ for_each_of_pci_range(&parser, &range) {
++ unsigned long restype = range.flags & IORESOURCE_TYPE_BITS;
++ if (restype == IORESOURCE_IO) {
++ of_pci_range_to_resource(&range, np, &pcie->io);
++ of_pci_range_to_resource(&range, np, &pcie->realio);
++ pcie->io.name = "I/O";
++ pcie->realio.start = max_t(resource_size_t,
++ PCIBIOS_MIN_IO,
++ range.pci_addr);
++ pcie->realio.end = min_t(resource_size_t,
++ IO_SPACE_LIMIT,
++ range.pci_addr + range.size);
++ }
++ if (restype == IORESOURCE_MEM) {
++ of_pci_range_to_resource(&range, np, &pcie->mem);
++ pcie->mem.name = "MEM";
++ }
++ }
++
++ /* Get the bus range */
++ ret = of_pci_parse_bus_range(np, &pcie->busn);
++ if (ret) {
++ dev_err(&pdev->dev, "failed to parse bus-range property: %d\n",
++ ret);
++ return ret;
++ }
++
++ for_each_child_of_node(pdev->dev.of_node, child) {
++ if (!of_device_is_available(child))
++ continue;
++ pcie->nports++;
++ }
++
++ pcie->ports = devm_kzalloc(&pdev->dev, pcie->nports *
++ sizeof(struct mvebu_pcie_port),
++ GFP_KERNEL);
++ if (!pcie->ports)
++ return -ENOMEM;
++
++ i = 0;
++ for_each_child_of_node(pdev->dev.of_node, child) {
++ struct mvebu_pcie_port *port = &pcie->ports[i];
++
++ if (!of_device_is_available(child))
++ continue;
++
++ port->pcie = pcie;
++
++ if (of_property_read_u32(child, "marvell,pcie-port",
++ &port->port)) {
++ dev_warn(&pdev->dev,
++ "ignoring PCIe DT node, missing pcie-port property\n");
++ continue;
++ }
++
++ if (of_property_read_u32(child, "marvell,pcie-lane",
++ &port->lane))
++ port->lane = 0;
++
++ port->name = kasprintf(GFP_KERNEL, "pcie%d.%d",
++ port->port, port->lane);
++
++ port->devfn = of_pci_get_devfn(child);
++ if (port->devfn < 0)
++ continue;
++
++ port->base = mvebu_pcie_map_registers(pdev, child, port);
++ if (!port->base) {
++ dev_err(&pdev->dev, "PCIe%d.%d: cannot map registers\n",
++ port->port, port->lane);
++ continue;
++ }
++
++ if (mvebu_pcie_link_up(port)) {
++ port->haslink = 1;
++ dev_info(&pdev->dev, "PCIe%d.%d: link up\n",
++ port->port, port->lane);
++ } else {
++ port->haslink = 0;
++ dev_info(&pdev->dev, "PCIe%d.%d: link down\n",
++ port->port, port->lane);
++ }
++
++ port->clk = of_clk_get_by_name(child, NULL);
++ if (!port->clk) {
++ dev_err(&pdev->dev, "PCIe%d.%d: cannot get clock\n",
++ port->port, port->lane);
++ iounmap(port->base);
++ port->haslink = 0;
++ continue;
++ }
++
++ port->dn = child;
++
++ clk_prepare_enable(port->clk);
++ spin_lock_init(&port->conf_lock);
++
++ mvebu_sw_pci_bridge_init(port);
++
++ i++;
++ }
++
++ mvebu_pcie_enable(pcie);
++
++ return 0;
++}
++
++static const struct of_device_id mvebu_pcie_of_match_table[] = {
++ { .compatible = "marvell,armada-xp-pcie", },
++ { .compatible = "marvell,armada-370-pcie", },
++ {},
++};
++MODULE_DEVICE_TABLE(of, mvebu_pcie_of_match_table);
++
++static struct platform_driver mvebu_pcie_driver = {
++ .driver = {
++ .owner = THIS_MODULE,
++ .name = "mvebu-pcie",
++ .of_match_table =
++ of_match_ptr(mvebu_pcie_of_match_table),
++ },
++};
++
++static int mvebu_pcie_init(void)
++{
++ return platform_driver_probe(&mvebu_pcie_driver,
++ mvebu_pcie_probe);
++}
++
++subsys_initcall(mvebu_pcie_init);
++
++MODULE_AUTHOR("Thomas Petazzoni <thomas.petazzoni@free-electrons.com>");
++MODULE_DESCRIPTION("Marvell EBU PCIe driver");
++MODULE_LICENSE("GPLv2");
+--
+1.8.4.rc1
+
--- /dev/null
+From d8bb1510b06f29bb6b63ebafe23656faae60d87f Mon Sep 17 00:00:00 2001
+From: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
+Date: Fri, 7 Dec 2012 20:56:52 +0100
+Subject: [PATCH 07/29] arm: mvebu: PCIe support is now available on mvebu
+
+Now that the PCIe driver for mvebu has been integrated and all its
+relevant dependencies, we can mark the ARCH_MVEBU platform has
+MIGHT_HAVE_PCI, which allows to select the PCI bus support if needed.
+
+Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
+---
+ arch/arm/mach-mvebu/Kconfig | 2 ++
+ 1 file changed, 2 insertions(+)
+
+diff --git a/arch/arm/mach-mvebu/Kconfig b/arch/arm/mach-mvebu/Kconfig
+index 80a8bca..fb827ac 100644
+--- a/arch/arm/mach-mvebu/Kconfig
++++ b/arch/arm/mach-mvebu/Kconfig
+@@ -16,6 +16,8 @@ config ARCH_MVEBU
+ select MVEBU_MBUS
+ select ZONE_DMA if ARM_LPAE
+ select ARCH_REQUIRE_GPIOLIB
++ select MIGHT_HAVE_PCI
++ select PCI_QUIRKS if PCI
+
+ if ARCH_MVEBU
+
+--
+1.8.4.rc1
+
--- /dev/null
+From 3339170f8adf10c32ad8ba4069f94f1bcd40f46d Mon Sep 17 00:00:00 2001
+From: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
+Date: Fri, 7 Dec 2012 22:49:57 +0100
+Subject: [PATCH 08/29] arm: mvebu: update defconfig with PCI and USB support
+
+Now that we have the necessary drivers and Device Tree informations to
+support PCIe on Armada 370 and Armada XP, enable the CONFIG_PCI
+option.
+
+Also, since the Armada 370 Mirabox has a built-in USB XHCI controller
+connected on the PCIe bus, enable the corresponding options as well.
+
+Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
+---
+ arch/arm/configs/mvebu_defconfig | 3 +++
+ 1 file changed, 3 insertions(+)
+
+diff --git a/arch/arm/configs/mvebu_defconfig b/arch/arm/configs/mvebu_defconfig
+index f3e8ae0..966281e 100644
+--- a/arch/arm/configs/mvebu_defconfig
++++ b/arch/arm/configs/mvebu_defconfig
+@@ -13,6 +13,8 @@ CONFIG_MACH_ARMADA_370=y
+ CONFIG_MACH_ARMADA_XP=y
+ # CONFIG_CACHE_L2X0 is not set
+ # CONFIG_SWP_EMULATE is not set
++CONFIG_PCI=y
++CONFIG_PCI_MVEBU=y
+ CONFIG_SMP=y
+ CONFIG_AEABI=y
+ CONFIG_HIGHMEM=y
+@@ -60,6 +62,7 @@ CONFIG_USB_SUPPORT=y
+ CONFIG_USB=y
+ CONFIG_USB_EHCI_HCD=y
+ CONFIG_USB_EHCI_ROOT_HUB_TT=y
++CONFIG_USB_XHCI_HCD=y
+ CONFIG_MMC=y
+ CONFIG_MMC_MVSDIO=y
+ CONFIG_NEW_LEDS=y
+--
+1.8.4.rc1
+
--- /dev/null
+From 3b93e75d1b66353b8f8ad7d965e17aad68982c55 Mon Sep 17 00:00:00 2001
+From: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
+Date: Wed, 27 Mar 2013 18:48:13 +0100
+Subject: [PATCH 09/29] pci: mvebu: enable driver usage on Kirkwood
+
+We allow the pci-mvebu driver to be compiled on the Kirkwood platform,
+and add the 'marvell,kirkwood-pcie' as a compatible string supported
+by the driver.
+
+Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
+Tested-by: Andrew Lunn <andrew@lunn.ch>
+---
+ Documentation/devicetree/bindings/pci/mvebu-pci.txt | 1 +
+ drivers/pci/host/Kconfig | 2 +-
+ drivers/pci/host/pci-mvebu.c | 1 +
+ 3 files changed, 3 insertions(+), 1 deletion(-)
+
+diff --git a/Documentation/devicetree/bindings/pci/mvebu-pci.txt b/Documentation/devicetree/bindings/pci/mvebu-pci.txt
+index eb69d92..f8d4058 100644
+--- a/Documentation/devicetree/bindings/pci/mvebu-pci.txt
++++ b/Documentation/devicetree/bindings/pci/mvebu-pci.txt
+@@ -4,6 +4,7 @@ Mandatory properties:
+ - compatible: one of the following values:
+ marvell,armada-370-pcie
+ marvell,armada-xp-pcie
++ marvell,kirkwood-pcie
+ - #address-cells, set to <3>
+ - #size-cells, set to <2>
+ - #interrupt-cells, set to <1>
+diff --git a/drivers/pci/host/Kconfig b/drivers/pci/host/Kconfig
+index 6918fbc..1f1d67f 100644
+--- a/drivers/pci/host/Kconfig
++++ b/drivers/pci/host/Kconfig
+@@ -3,6 +3,6 @@ menu "PCI host controller drivers"
+
+ config PCI_MVEBU
+ bool "Marvell EBU PCIe controller"
+- depends on ARCH_MVEBU
++ depends on ARCH_MVEBU || ARCH_KIRKWOOD
+
+ endmenu
+diff --git a/drivers/pci/host/pci-mvebu.c b/drivers/pci/host/pci-mvebu.c
+index b0ee63b..6fe8b90 100644
+--- a/drivers/pci/host/pci-mvebu.c
++++ b/drivers/pci/host/pci-mvebu.c
+@@ -853,6 +853,7 @@ static int __init mvebu_pcie_probe(struct platform_device *pdev)
+ static const struct of_device_id mvebu_pcie_of_match_table[] = {
+ { .compatible = "marvell,armada-xp-pcie", },
+ { .compatible = "marvell,armada-370-pcie", },
++ { .compatible = "marvell,kirkwood-pcie", },
+ {},
+ };
+ MODULE_DEVICE_TABLE(of, mvebu_pcie_of_match_table);
+--
+1.8.4.rc1
+
--- /dev/null
+From 080dc44291ff143d84b63e5ff9fda963d46a7dce Mon Sep 17 00:00:00 2001
+From: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
+Date: Wed, 27 Mar 2013 18:51:25 +0100
+Subject: [PATCH 10/29] arm: kirkwood: move PCIe window init to legacy driver
+
+Since we are going to enable the usage of the mvebu PCIe driver on
+Kirkwood, we don't want the PCIe windows to be unconditionally created
+by kirkwood_setup_wins(). Therefore, we move the PCIe window
+initialization into the legacy PCIe driver
+(arch/arm/mach-kirkwood/pcie.c).
+
+The platforms using the legacy driver will see their windows
+statically allocated by
+arch/arm/mach-kirkwood/pcie.c:kirkwood_pcie_init(). The platforms
+using the new driver in drivers/pci/ will see their windows
+dynamically allocated directly by the driver.
+
+Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
+Tested-by: Andrew Lunn <andrew@lunn.ch>
+---
+ arch/arm/mach-kirkwood/common.c | 24 ------------------------
+ arch/arm/mach-kirkwood/pcie.c | 22 ++++++++++++++++++++++
+ 2 files changed, 22 insertions(+), 24 deletions(-)
+
+diff --git a/arch/arm/mach-kirkwood/common.c b/arch/arm/mach-kirkwood/common.c
+index f389228..41ea98d 100644
+--- a/arch/arm/mach-kirkwood/common.c
++++ b/arch/arm/mach-kirkwood/common.c
+@@ -648,30 +648,6 @@ char * __init kirkwood_id(void)
+
+ void __init kirkwood_setup_wins(void)
+ {
+- /*
+- * The PCIe windows will no longer be statically allocated
+- * here once Kirkwood is migrated to the pci-mvebu driver.
+- */
+- mvebu_mbus_add_window_remap_flags("pcie0.0",
+- KIRKWOOD_PCIE_IO_PHYS_BASE,
+- KIRKWOOD_PCIE_IO_SIZE,
+- KIRKWOOD_PCIE_IO_BUS_BASE,
+- MVEBU_MBUS_PCI_IO);
+- mvebu_mbus_add_window_remap_flags("pcie0.0",
+- KIRKWOOD_PCIE_MEM_PHYS_BASE,
+- KIRKWOOD_PCIE_MEM_SIZE,
+- MVEBU_MBUS_NO_REMAP,
+- MVEBU_MBUS_PCI_MEM);
+- mvebu_mbus_add_window_remap_flags("pcie1.0",
+- KIRKWOOD_PCIE1_IO_PHYS_BASE,
+- KIRKWOOD_PCIE1_IO_SIZE,
+- KIRKWOOD_PCIE1_IO_BUS_BASE,
+- MVEBU_MBUS_PCI_IO);
+- mvebu_mbus_add_window_remap_flags("pcie1.0",
+- KIRKWOOD_PCIE1_MEM_PHYS_BASE,
+- KIRKWOOD_PCIE1_MEM_SIZE,
+- MVEBU_MBUS_NO_REMAP,
+- MVEBU_MBUS_PCI_MEM);
+ mvebu_mbus_add_window("nand", KIRKWOOD_NAND_MEM_PHYS_BASE,
+ KIRKWOOD_NAND_MEM_SIZE);
+ mvebu_mbus_add_window("sram", KIRKWOOD_SRAM_PHYS_BASE,
+diff --git a/arch/arm/mach-kirkwood/pcie.c b/arch/arm/mach-kirkwood/pcie.c
+index 7f43e6c..ddcb09f 100644
+--- a/arch/arm/mach-kirkwood/pcie.c
++++ b/arch/arm/mach-kirkwood/pcie.c
+@@ -12,6 +12,7 @@
+ #include <linux/pci.h>
+ #include <linux/slab.h>
+ #include <linux/clk.h>
++#include <linux/mbus.h>
+ #include <video/vga.h>
+ #include <asm/irq.h>
+ #include <asm/mach/pci.h>
+@@ -253,6 +254,27 @@ static void __init add_pcie_port(int index, void __iomem *base)
+
+ void __init kirkwood_pcie_init(unsigned int portmask)
+ {
++ mvebu_mbus_add_window_remap_flags("pcie0.0",
++ KIRKWOOD_PCIE_IO_PHYS_BASE,
++ KIRKWOOD_PCIE_IO_SIZE,
++ KIRKWOOD_PCIE_IO_BUS_BASE,
++ MVEBU_MBUS_PCI_IO);
++ mvebu_mbus_add_window_remap_flags("pcie0.0",
++ KIRKWOOD_PCIE_MEM_PHYS_BASE,
++ KIRKWOOD_PCIE_MEM_SIZE,
++ MVEBU_MBUS_NO_REMAP,
++ MVEBU_MBUS_PCI_MEM);
++ mvebu_mbus_add_window_remap_flags("pcie1.0",
++ KIRKWOOD_PCIE1_IO_PHYS_BASE,
++ KIRKWOOD_PCIE1_IO_SIZE,
++ KIRKWOOD_PCIE1_IO_BUS_BASE,
++ MVEBU_MBUS_PCI_IO);
++ mvebu_mbus_add_window_remap_flags("pcie1.0",
++ KIRKWOOD_PCIE1_MEM_PHYS_BASE,
++ KIRKWOOD_PCIE1_MEM_SIZE,
++ MVEBU_MBUS_NO_REMAP,
++ MVEBU_MBUS_PCI_MEM);
++
+ vga_base = KIRKWOOD_PCIE_MEM_PHYS_BASE;
+
+ if (portmask & KW_PCIE0)
+--
+1.8.4.rc1
+
--- /dev/null
+From 8725a4f93dcb242466990261dc2bd78599b0306a Mon Sep 17 00:00:00 2001
+From: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
+Date: Wed, 27 Mar 2013 18:55:20 +0100
+Subject: [PATCH 11/29] arm: kirkwood: add SoC-level Device Tree data for PCIe
+ interfaces
+
+This commit adds Device Tree details to enable the PCIe interfaces on
+Kirkwood. The 6281 has one PCIe interface, the 6282 has two PCIe
+interfaces.
+
+Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
+Tested-by: Andrew Lunn <andrew@lunn.ch>
+---
+ arch/arm/boot/dts/kirkwood-6281.dtsi | 31 +++++++++++++++++++++++
+ arch/arm/boot/dts/kirkwood-6282.dtsi | 48 ++++++++++++++++++++++++++++++++++++
+ arch/arm/boot/dts/kirkwood.dtsi | 1 +
+ 3 files changed, 80 insertions(+)
+
+diff --git a/arch/arm/boot/dts/kirkwood-6281.dtsi b/arch/arm/boot/dts/kirkwood-6281.dtsi
+index d6c9d65..5137668 100644
+--- a/arch/arm/boot/dts/kirkwood-6281.dtsi
++++ b/arch/arm/boot/dts/kirkwood-6281.dtsi
+@@ -40,5 +40,36 @@
+ marvell,function = "sdio";
+ };
+ };
++
++ pcie-controller {
++ compatible = "marvell,kirkwood-pcie";
++ status = "disabled";
++ device_type = "pci";
++
++ #address-cells = <3>;
++ #size-cells = <2>;
++
++ bus-range = <0x00 0xff>;
++
++ ranges = <0x82000000 0 0x00040000 0x00040000 0 0x00002000 /* Port 0.0 registers */
++ 0x82000000 0 0xe0000000 0xe0000000 0 0x08000000 /* non-prefetchable memory */
++ 0x81000000 0 0 0xe8000000 0 0x00100000>; /* downstream I/O */
++
++ pcie@1,0 {
++ device_type = "pci";
++ assigned-addresses = <0x82000800 0 0x00040000 0 0x2000>;
++ reg = <0x0800 0 0 0 0>;
++ #address-cells = <3>;
++ #size-cells = <2>;
++ #interrupt-cells = <1>;
++ ranges;
++ interrupt-map-mask = <0 0 0 0>;
++ interrupt-map = <0 0 0 0 &intc 9>;
++ marvell,pcie-port = <0>;
++ marvell,pcie-lane = <0>;
++ clocks = <&gate_clk 2>;
++ status = "disabled";
++ };
++ };
+ };
+ };
+diff --git a/arch/arm/boot/dts/kirkwood-6282.dtsi b/arch/arm/boot/dts/kirkwood-6282.dtsi
+index 23991e4..66a751a 100644
+--- a/arch/arm/boot/dts/kirkwood-6282.dtsi
++++ b/arch/arm/boot/dts/kirkwood-6282.dtsi
+@@ -65,5 +65,53 @@
+ clocks = <&gate_clk 7>;
+ status = "disabled";
+ };
++
++ pcie-controller {
++ compatible = "marvell,kirkwood-pcie";
++ status = "disabled";
++ device_type = "pci";
++
++ #address-cells = <3>;
++ #size-cells = <2>;
++
++ bus-range = <0x00 0xff>;
++
++ ranges = <0x82000000 0 0x00040000 0x00040000 0 0x00002000 /* Port 0.0 registers */
++ 0x82000000 0 0x00044000 0x00044000 0 0x00002000 /* Port 1.0 registers */
++ 0x82000000 0 0xe0000000 0xe0000000 0 0x08000000 /* non-prefetchable memory */
++ 0x81000000 0 0 0xe8000000 0 0x00100000>; /* downstream I/O */
++
++ pcie@1,0 {
++ device_type = "pci";
++ assigned-addresses = <0x82000800 0 0x00040000 0 0x2000>;
++ reg = <0x0800 0 0 0 0>;
++ #address-cells = <3>;
++ #size-cells = <2>;
++ #interrupt-cells = <1>;
++ ranges;
++ interrupt-map-mask = <0 0 0 0>;
++ interrupt-map = <0 0 0 0 &intc 9>;
++ marvell,pcie-port = <0>;
++ marvell,pcie-lane = <0>;
++ clocks = <&gate_clk 2>;
++ status = "disabled";
++ };
++
++ pcie@2,0 {
++ device_type = "pci";
++ assigned-addresses = <0x82001000 0 0x00044000 0 0x2000>;
++ reg = <0x1000 0 0 0 0>;
++ #address-cells = <3>;
++ #size-cells = <2>;
++ #interrupt-cells = <1>;
++ ranges;
++ interrupt-map-mask = <0 0 0 0>;
++ interrupt-map = <0 0 0 0 &intc 10>;
++ marvell,pcie-port = <1>;
++ marvell,pcie-lane = <0>;
++ clocks = <&gate_clk 18>;
++ status = "disabled";
++ };
++ };
+ };
+ };
+diff --git a/arch/arm/boot/dts/kirkwood.dtsi b/arch/arm/boot/dts/kirkwood.dtsi
+index fada7e6..7eef88f 100644
+--- a/arch/arm/boot/dts/kirkwood.dtsi
++++ b/arch/arm/boot/dts/kirkwood.dtsi
+@@ -19,6 +19,7 @@
+ ocp@f1000000 {
+ compatible = "simple-bus";
+ ranges = <0x00000000 0xf1000000 0x4000000
++ 0xe0000000 0xe0000000 0x8100000 /* PCIE */
+ 0xf5000000 0xf5000000 0x0000400>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+--
+1.8.4.rc1
+
--- /dev/null
+From b7031bd802336c77a6b330f79b275ccbb55fdc96 Mon Sep 17 00:00:00 2001
+From: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
+Date: Wed, 10 Apr 2013 21:22:13 +0200
+Subject: [PATCH 12/29] arm: kirkwood: convert Iomega Iconnect to use DT for
+ the PCIe interface
+
+Now that the PCIe mvebu driver is usable on Kirkwood, use it instead
+of the legacy PCIe code, since it allows to describe the PCIe
+interfaces in the Device Tree.
+
+Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
+---
+ arch/arm/boot/dts/kirkwood-iconnect.dts | 8 ++++++++
+ arch/arm/mach-kirkwood/board-iconnect.c | 8 --------
+ 2 files changed, 8 insertions(+), 8 deletions(-)
+
+diff --git a/arch/arm/boot/dts/kirkwood-iconnect.dts b/arch/arm/boot/dts/kirkwood-iconnect.dts
+index 12ccf74..e591d5d 100644
+--- a/arch/arm/boot/dts/kirkwood-iconnect.dts
++++ b/arch/arm/boot/dts/kirkwood-iconnect.dts
+@@ -109,6 +109,14 @@
+ reg = <0x980000 0x1f400000>;
+ };
+ };
++
++ pcie-controller {
++ status = "okay";
++
++ pcie@1,0 {
++ status = "okay";
++ };
++ };
+ };
+
+ gpio-leds {
+diff --git a/arch/arm/mach-kirkwood/board-iconnect.c b/arch/arm/mach-kirkwood/board-iconnect.c
+index c8ebde4..98b5ad1 100644
+--- a/arch/arm/mach-kirkwood/board-iconnect.c
++++ b/arch/arm/mach-kirkwood/board-iconnect.c
+@@ -22,11 +22,3 @@ void __init iconnect_init(void)
+ {
+ kirkwood_ge00_init(&iconnect_ge00_data);
+ }
+-
+-static int __init iconnect_pci_init(void)
+-{
+- if (of_machine_is_compatible("iom,iconnect"))
+- kirkwood_pcie_init(KW_PCIE0);
+- return 0;
+-}
+-subsys_initcall(iconnect_pci_init);
+--
+1.8.4.rc1
+
--- /dev/null
+From b3e3851d461779cd94a2efe4484f01175fcb460e Mon Sep 17 00:00:00 2001
+From: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
+Date: Wed, 10 Apr 2013 23:05:32 +0200
+Subject: [PATCH 13/29] arm: kirkwood: convert MPL CEC4 to use DT for the PCIe
+ interface
+
+Now that the PCIe mvebu driver is usable on Kirkwood, use it instead
+of the legacy PCIe code, since it allows to describe the PCIe
+interfaces in the Device Tree.
+
+Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
+---
+ arch/arm/boot/dts/kirkwood-mplcec4.dts | 8 ++++++++
+ arch/arm/mach-kirkwood/board-mplcec4.c | 1 -
+ 2 files changed, 8 insertions(+), 1 deletion(-)
+
+diff --git a/arch/arm/boot/dts/kirkwood-mplcec4.dts b/arch/arm/boot/dts/kirkwood-mplcec4.dts
+index 7588241..90501cf 100644
+--- a/arch/arm/boot/dts/kirkwood-mplcec4.dts
++++ b/arch/arm/boot/dts/kirkwood-mplcec4.dts
+@@ -139,6 +139,14 @@
+ cd-gpios = <&gpio1 15 0>;
+ /* No WP GPIO */
+ };
++
++ pcie-controller {
++ status = "okay";
++
++ pcie@1,0 {
++ status = "okay";
++ };
++ };
+ };
+
+ gpio-leds {
+diff --git a/arch/arm/mach-kirkwood/board-mplcec4.c b/arch/arm/mach-kirkwood/board-mplcec4.c
+index 7d6dc66..938712e 100644
+--- a/arch/arm/mach-kirkwood/board-mplcec4.c
++++ b/arch/arm/mach-kirkwood/board-mplcec4.c
+@@ -29,7 +29,6 @@ void __init mplcec4_init(void)
+ */
+ kirkwood_ge00_init(&mplcec4_ge00_data);
+ kirkwood_ge01_init(&mplcec4_ge01_data);
+- kirkwood_pcie_init(KW_PCIE0);
+ }
+
+
+--
+1.8.4.rc1
+
--- /dev/null
+From 86310ed36ec224b248b5169371f44250ce8c2275 Mon Sep 17 00:00:00 2001
+From: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
+Date: Wed, 10 Apr 2013 23:07:27 +0200
+Subject: [PATCH 14/29] arm: kirkwood: convert ZyXEL NSA310 to use DT for the
+ PCIe interface
+
+Now that the PCIe mvebu driver is usable on Kirkwood, use it instead
+of the legacy PCIe code, since it allows to describe the PCIe
+interfaces in the Device Tree.
+
+Since it was the only device left that prevented this platform to use
+the Device Tree only, we remove the board-nsa310.c file and the
+related Kconfig/Makefile bits.
+
+Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
+---
+ arch/arm/boot/dts/kirkwood-nsa310.dts | 8 ++++++++
+ arch/arm/mach-kirkwood/Kconfig | 8 --------
+ arch/arm/mach-kirkwood/Makefile | 1 -
+ arch/arm/mach-kirkwood/board-nsa310.c | 25 -------------------------
+ 4 files changed, 8 insertions(+), 34 deletions(-)
+ delete mode 100644 arch/arm/mach-kirkwood/board-nsa310.c
+
+diff --git a/arch/arm/boot/dts/kirkwood-nsa310.dts b/arch/arm/boot/dts/kirkwood-nsa310.dts
+index a7412b9..9ddf218 100644
+--- a/arch/arm/boot/dts/kirkwood-nsa310.dts
++++ b/arch/arm/boot/dts/kirkwood-nsa310.dts
+@@ -176,6 +176,14 @@
+ reg = <0x5040000 0x2fc0000>;
+ };
+ };
++
++ pcie-controller {
++ status = "okay";
++
++ pcie@1,0 {
++ status = "okay";
++ };
++ };
+ };
+
+ gpio_keys {
+diff --git a/arch/arm/mach-kirkwood/Kconfig b/arch/arm/mach-kirkwood/Kconfig
+index 7509a89..267ca95 100644
+--- a/arch/arm/mach-kirkwood/Kconfig
++++ b/arch/arm/mach-kirkwood/Kconfig
+@@ -272,14 +272,6 @@ config MACH_NETSPACE_V2_DT
+ Say 'Y' here if you want your kernel to support the LaCie
+ Network Space v2 NAS, using Flattened Device Tree.
+
+-config MACH_NSA310_DT
+- bool "ZyXEL NSA-310 (Flattened Device Tree)"
+- select ARCH_KIRKWOOD_DT
+- select ARM_ATAG_DTB_COMPAT
+- help
+- Say 'Y' here if you want your kernel to support the
+- ZyXEL NSA-310 board (Flattened Device Tree).
+-
+ config MACH_OPENBLOCKS_A6_DT
+ bool "Plat'Home OpenBlocks A6 (Flattened Device Tree)"
+ select ARCH_KIRKWOOD_DT
+diff --git a/arch/arm/mach-kirkwood/Makefile b/arch/arm/mach-kirkwood/Makefile
+index e1f3735..794366e 100644
+--- a/arch/arm/mach-kirkwood/Makefile
++++ b/arch/arm/mach-kirkwood/Makefile
+@@ -37,7 +37,6 @@ obj-$(CONFIG_MACH_NETSPACE_LITE_V2_DT) += board-ns2.o
+ obj-$(CONFIG_MACH_NETSPACE_MAX_V2_DT) += board-ns2.o
+ obj-$(CONFIG_MACH_NETSPACE_MINI_V2_DT) += board-ns2.o
+ obj-$(CONFIG_MACH_NETSPACE_V2_DT) += board-ns2.o
+-obj-$(CONFIG_MACH_NSA310_DT) += board-nsa310.o
+ obj-$(CONFIG_MACH_OPENBLOCKS_A6_DT) += board-openblocks_a6.o
+ obj-$(CONFIG_MACH_READYNAS_DT) += board-readynas.o
+ obj-$(CONFIG_MACH_TOPKICK_DT) += board-usi_topkick.o
+diff --git a/arch/arm/mach-kirkwood/board-nsa310.c b/arch/arm/mach-kirkwood/board-nsa310.c
+deleted file mode 100644
+index 55ade93..0000000
+--- a/arch/arm/mach-kirkwood/board-nsa310.c
++++ /dev/null
+@@ -1,25 +0,0 @@
+-/*
+- * arch/arm/mach-kirkwood/nsa-310-setup.c
+- *
+- * ZyXEL NSA-310 Setup
+- *
+- * This file is licensed under the terms of the GNU General Public
+- * License version 2. This program is licensed "as is" without any
+- * warranty of any kind, whether express or implied.
+- */
+-
+-#include <linux/kernel.h>
+-#include <linux/init.h>
+-#include <mach/kirkwood.h>
+-#include <linux/of.h>
+-#include "common.h"
+-
+-static int __init nsa310_pci_init(void)
+-{
+- if (of_machine_is_compatible("zyxel,nsa310"))
+- kirkwood_pcie_init(KW_PCIE0);
+-
+- return 0;
+-}
+-
+-subsys_initcall(nsa310_pci_init);
+--
+1.8.4.rc1
+
--- /dev/null
+From 0f75608615894c9707e40c0dd3383193fb6c09f6 Mon Sep 17 00:00:00 2001
+From: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
+Date: Sat, 13 Apr 2013 13:03:56 +0200
+Subject: [PATCH 15/29] arm: kirkwood: convert QNAP TS219 to use DT for the
+ PCIe interface
+
+Now that the PCIe mvebu driver is usable on Kirkwood, use it instead
+of the legacy PCIe code, since it allows to describe the PCIe
+interfaces in the Device Tree.
+
+Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
+Signed-off-by: Andrew Lunn <andrew@lunn.ch>
+---
+ arch/arm/boot/dts/kirkwood-ts219-6281.dts | 3 ++-
+ arch/arm/boot/dts/kirkwood-ts219-6282.dts | 3 ++-
+ arch/arm/boot/dts/kirkwood-ts219.dtsi | 9 +++++++--
+ 3 files changed, 11 insertions(+), 4 deletions(-)
+
+diff --git a/arch/arm/boot/dts/kirkwood-ts219-6281.dts b/arch/arm/boot/dts/kirkwood-ts219-6281.dts
+index 8295c83..42648ab 100644
+--- a/arch/arm/boot/dts/kirkwood-ts219-6281.dts
++++ b/arch/arm/boot/dts/kirkwood-ts219-6281.dts
+@@ -1,7 +1,8 @@
+ /dts-v1/;
+
+-/include/ "kirkwood-ts219.dtsi"
++/include/ "kirkwood.dtsi"
+ /include/ "kirkwood-6281.dtsi"
++/include/ "kirkwood-ts219.dtsi"
+
+ / {
+ ocp@f1000000 {
+diff --git a/arch/arm/boot/dts/kirkwood-ts219-6282.dts b/arch/arm/boot/dts/kirkwood-ts219-6282.dts
+index df3f95d..95ceeb9 100644
+--- a/arch/arm/boot/dts/kirkwood-ts219-6282.dts
++++ b/arch/arm/boot/dts/kirkwood-ts219-6282.dts
+@@ -1,7 +1,8 @@
+ /dts-v1/;
+
+-/include/ "kirkwood-ts219.dtsi"
++/include/ "kirkwood.dtsi"
+ /include/ "kirkwood-6282.dtsi"
++/include/ "kirkwood-ts219.dtsi"
+
+ / {
+ ocp@f1000000 {
+diff --git a/arch/arm/boot/dts/kirkwood-ts219.dtsi b/arch/arm/boot/dts/kirkwood-ts219.dtsi
+index 64ea27c..7c022fd 100644
+--- a/arch/arm/boot/dts/kirkwood-ts219.dtsi
++++ b/arch/arm/boot/dts/kirkwood-ts219.dtsi
+@@ -1,5 +1,3 @@
+-/include/ "kirkwood.dtsi"
+-
+ / {
+ model = "QNAP TS219 family";
+ compatible = "qnap,ts219", "marvell,kirkwood";
+@@ -74,5 +72,12 @@
+ status = "okay";
+ nr-ports = <2>;
+ };
++ pcie-controller {
++ status = "okay";
++
++ pcie@1,0 {
++ status = "okay";
++ };
++ };
+ };
+ };
+--
+1.8.4.rc1
+
--- /dev/null
+From 32f9dd19f7c859205440a8734cb6ab1295c78015 Mon Sep 17 00:00:00 2001
+From: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
+Date: Wed, 27 Mar 2013 18:56:40 +0100
+Subject: [PATCH 16/29] arm: kirkwood: convert db-88f6281/db-88f6282 to the
+ Device Tree
+
+This commit converts the Marvell DB-88F6281/DB-88F6282 board to the
+Device Tree. In fact, the code was supporting two different boards:
+one with the 6281 SoC variant, and one with the 6282 SoC variant. The
+difference between the two being that the 6281 has one PCIe interface,
+and the 6282 has two PCIe interfaces.
+
+In order to handle that with the Device Tree, we create a
+'kirkwood-db.dtsi' file that contains the definitions common to both
+boards, and 'kirkwood-db-88f6281.dts' and 'kirkwood-db-88f6282.dts'
+for the definitions specific to each board. This is similar to what is
+done for the QNAP TS219 Kirkwood platform.
+
+We have kept one single Kconfig option, just like it was before.
+
+Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
+---
+ arch/arm/boot/dts/Makefile | 2 +
+ arch/arm/boot/dts/kirkwood-db-88f6281.dts | 30 ++++++++
+ arch/arm/boot/dts/kirkwood-db-88f6282.dts | 34 +++++++++
+ arch/arm/boot/dts/kirkwood-db.dtsi | 89 +++++++++++++++++++++++
+ arch/arm/mach-kirkwood/Kconfig | 13 ++--
+ arch/arm/mach-kirkwood/Makefile | 2 +-
+ arch/arm/mach-kirkwood/board-db88f628x-bp.c | 24 +++++++
+ arch/arm/mach-kirkwood/board-dt.c | 6 ++
+ arch/arm/mach-kirkwood/common.h | 6 ++
+ arch/arm/mach-kirkwood/db88f6281-bp-setup.c | 108 ----------------------------
+ 10 files changed, 199 insertions(+), 115 deletions(-)
+ create mode 100644 arch/arm/boot/dts/kirkwood-db-88f6281.dts
+ create mode 100644 arch/arm/boot/dts/kirkwood-db-88f6282.dts
+ create mode 100644 arch/arm/boot/dts/kirkwood-db.dtsi
+ create mode 100644 arch/arm/mach-kirkwood/board-db88f628x-bp.c
+ delete mode 100644 arch/arm/mach-kirkwood/db88f6281-bp-setup.c
+
+diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
+index f0895c5..3844ef2 100644
+--- a/arch/arm/boot/dts/Makefile
++++ b/arch/arm/boot/dts/Makefile
+@@ -64,6 +64,8 @@ dtb-$(CONFIG_ARCH_INTEGRATOR) += integratorap.dtb \
+ integratorcp.dtb
+ dtb-$(CONFIG_ARCH_LPC32XX) += ea3250.dtb phy3250.dtb
+ dtb-$(CONFIG_ARCH_KIRKWOOD) += kirkwood-cloudbox.dtb \
++ kirkwood-db-88f6281.dtb \
++ kirkwood-db-88f6282.dtb \
+ kirkwood-dns320.dtb \
+ kirkwood-dns325.dtb \
+ kirkwood-dockstar.dtb \
+diff --git a/arch/arm/boot/dts/kirkwood-db-88f6281.dts b/arch/arm/boot/dts/kirkwood-db-88f6281.dts
+new file mode 100644
+index 0000000..9d777ed
+--- /dev/null
++++ b/arch/arm/boot/dts/kirkwood-db-88f6281.dts
+@@ -0,0 +1,30 @@
++/*
++ * Marvell DB-88F6281-BP Development Board Setup
++ *
++ * Saeed Bishara <saeed@marvell.com>
++ * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
++ *
++ * This file is licensed under the terms of the GNU General Public
++ * License version 2. This program is licensed "as is" without any
++ * warranty of any kind, whether express or implied.
++ */
++
++/dts-v1/;
++
++/include/ "kirkwood-db.dtsi"
++/include/ "kirkwood-6281.dtsi"
++
++/ {
++ model = "Marvell DB-88F6281-BP Development Board";
++ compatible = "marvell,db-88f6281-bp", "marvell,kirkwood-88f6281", "marvell,kirkwood";
++
++ ocp@f1000000 {
++ pcie-controller {
++ status = "okay";
++
++ pcie@1,0 {
++ status = "okay";
++ };
++ };
++ };
++};
+diff --git a/arch/arm/boot/dts/kirkwood-db-88f6282.dts b/arch/arm/boot/dts/kirkwood-db-88f6282.dts
+new file mode 100644
+index 0000000..f4c8528
+--- /dev/null
++++ b/arch/arm/boot/dts/kirkwood-db-88f6282.dts
+@@ -0,0 +1,34 @@
++/*
++ * Marvell DB-88F6282-BP Development Board Setup
++ *
++ * Saeed Bishara <saeed@marvell.com>
++ * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
++ *
++ * This file is licensed under the terms of the GNU General Public
++ * License version 2. This program is licensed "as is" without any
++ * warranty of any kind, whether express or implied.
++ */
++
++/dts-v1/;
++
++/include/ "kirkwood-db.dtsi"
++/include/ "kirkwood-6282.dtsi"
++
++/ {
++ model = "Marvell DB-88F6282-BP Development Board";
++ compatible = "marvell,db-88f6282-bp", "marvell,kirkwood-88f6282", "marvell,kirkwood";
++
++ ocp@f1000000 {
++ pcie-controller {
++ status = "okay";
++
++ pcie@1,0 {
++ status = "okay";
++ };
++
++ pcie@2,0 {
++ status = "okay";
++ };
++ };
++ };
++};
+diff --git a/arch/arm/boot/dts/kirkwood-db.dtsi b/arch/arm/boot/dts/kirkwood-db.dtsi
+new file mode 100644
+index 0000000..c87cfb8
+--- /dev/null
++++ b/arch/arm/boot/dts/kirkwood-db.dtsi
+@@ -0,0 +1,89 @@
++/*
++ * Marvell DB-{88F6281,88F6282}-BP Development Board Setup
++ *
++ * Saeed Bishara <saeed@marvell.com>
++ * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
++ *
++ * This file is licensed under the terms of the GNU General Public
++ * License version 2. This program is licensed "as is" without any
++ * warranty of any kind, whether express or implied.
++ *
++ * This file contains the definitions that are common between the 6281
++ * and 6282 variants of the Marvell Kirkwood Development Board.
++ */
++
++/include/ "kirkwood.dtsi"
++
++/ {
++ memory {
++ device_type = "memory";
++ reg = <0x00000000 0x20000000>; /* 512 MB */
++ };
++
++ chosen {
++ bootargs = "console=ttyS0,115200n8 earlyprintk";
++ };
++
++ ocp@f1000000 {
++ pinctrl@10000 {
++ pmx_sdio_gpios: pmx-sdio-gpios {
++ marvell,pins = "mpp37", "mpp38";
++ marvell,function = "gpio";
++ };
++ };
++
++ serial@12000 {
++ pinctrl-0 = <&pmx_uart0>;
++ pinctrl-names = "default";
++ clock-frequency = <200000000>;
++ status = "ok";
++ };
++
++ nand@3000000 {
++ pinctrl-0 = <&pmx_nand>;
++ pinctrl-names = "default";
++ chip-delay = <25>;
++ status = "okay";
++
++ partition@0 {
++ label = "uboot";
++ reg = <0x0 0x100000>;
++ };
++
++ partition@100000 {
++ label = "uImage";
++ reg = <0x100000 0x400000>;
++ };
++
++ partition@500000 {
++ label = "root";
++ reg = <0x500000 0x1fb00000>;
++ };
++ };
++
++ sata@80000 {
++ nr-ports = <2>;
++ status = "okay";
++ };
++
++ ehci@50000 {
++ status = "okay";
++ };
++
++ mvsdio@90000 {
++ pinctrl-0 = <&pmx_sdio_gpios>;
++ pinctrl-names = "default";
++ wp-gpios = <&gpio1 5 0>;
++ cd-gpios = <&gpio1 6 0>;
++ status = "okay";
++ };
++
++ pcie-controller {
++ status = "okay";
++
++ pcie@1,0 {
++ status = "okay";
++ };
++ };
++ };
++};
+diff --git a/arch/arm/mach-kirkwood/Kconfig b/arch/arm/mach-kirkwood/Kconfig
+index 267ca95..b56bd3d 100644
+--- a/arch/arm/mach-kirkwood/Kconfig
++++ b/arch/arm/mach-kirkwood/Kconfig
+@@ -8,12 +8,6 @@ config MACH_D2NET_V2
+ Say 'Y' here if you want your kernel to support the
+ LaCie d2 Network v2 NAS.
+
+-config MACH_DB88F6281_BP
+- bool "Marvell DB-88F6281-BP Development Board"
+- help
+- Say 'Y' here if you want your kernel to support the
+- Marvell DB-88F6281-BP Development Board.
+-
+ config MACH_DOCKSTAR
+ bool "Seagate FreeAgent DockStar"
+ help
+@@ -153,6 +147,13 @@ config MACH_CLOUDBOX_DT
+ Say 'Y' here if you want your kernel to support the LaCie
+ CloudBox NAS, using Flattened Device Tree.
+
++config MACH_DB88F628X_BP_DT
++ bool "Marvell DB-88F628x-BP Development Board (Flattened Device Tree)"
++ help
++ Say 'Y' here if you want your kernel to support the Marvell
++ DB-88F6281-BP and DB-88F6282-BP Development Board (Flattened
++ Device Tree).
++
+ config MACH_DLINK_KIRKWOOD_DT
+ bool "D-Link Kirkwood-based NAS (Flattened Device Tree)"
+ select ARCH_KIRKWOOD_DT
+diff --git a/arch/arm/mach-kirkwood/Makefile b/arch/arm/mach-kirkwood/Makefile
+index 794366e..2fdc3a7 100644
+--- a/arch/arm/mach-kirkwood/Makefile
++++ b/arch/arm/mach-kirkwood/Makefile
+@@ -1,7 +1,6 @@
+ obj-y += common.o irq.o pcie.o mpp.o
+
+ obj-$(CONFIG_MACH_D2NET_V2) += d2net_v2-setup.o lacie_v2-common.o
+-obj-$(CONFIG_MACH_DB88F6281_BP) += db88f6281-bp-setup.o
+ obj-$(CONFIG_MACH_DOCKSTAR) += dockstar-setup.o
+ obj-$(CONFIG_MACH_ESATA_SHEEVAPLUG) += sheevaplug-setup.o
+ obj-$(CONFIG_MACH_GURUPLUG) += guruplug-setup.o
+@@ -21,6 +20,7 @@ obj-$(CONFIG_MACH_TS41X) += ts41x-setup.o tsx1x-common.o
+
+ obj-$(CONFIG_ARCH_KIRKWOOD_DT) += board-dt.o
+ obj-$(CONFIG_MACH_CLOUDBOX_DT) += board-ns2.o
++obj-$(CONFIG_MACH_DB88F628X_BP_DT) += board-db88f628x-bp.o
+ obj-$(CONFIG_MACH_DLINK_KIRKWOOD_DT) += board-dnskw.o
+ obj-$(CONFIG_MACH_DOCKSTAR_DT) += board-dockstar.o
+ obj-$(CONFIG_MACH_DREAMPLUG_DT) += board-dreamplug.o
+diff --git a/arch/arm/mach-kirkwood/board-db88f628x-bp.c b/arch/arm/mach-kirkwood/board-db88f628x-bp.c
+new file mode 100644
+index 0000000..2f574bc
+--- /dev/null
++++ b/arch/arm/mach-kirkwood/board-db88f628x-bp.c
+@@ -0,0 +1,24 @@
++/*
++ * Saeed Bishara <saeed@marvell.com>
++ *
++ * Marvell DB-88F628{1,2}-BP Development Board Setup
++ *
++ * This file is licensed under the terms of the GNU General Public
++ * License version 2. This program is licensed "as is" without any
++ * warranty of any kind, whether express or implied.
++ */
++
++#include <linux/kernel.h>
++#include <linux/init.h>
++#include <linux/of.h>
++#include <linux/mv643xx_eth.h>
++#include "common.h"
++
++static struct mv643xx_eth_platform_data db88f628x_ge00_data = {
++ .phy_addr = MV643XX_ETH_PHY_ADDR(8),
++};
++
++void __init db88f628x_init(void)
++{
++ kirkwood_ge00_init(&db88f628x_ge00_data);
++}
+diff --git a/arch/arm/mach-kirkwood/board-dt.c b/arch/arm/mach-kirkwood/board-dt.c
+index e9647b8..f5aed1f 100644
+--- a/arch/arm/mach-kirkwood/board-dt.c
++++ b/arch/arm/mach-kirkwood/board-dt.c
+@@ -147,6 +147,10 @@ static void __init kirkwood_dt_init(void)
+ of_machine_is_compatible("lacie,netspace_v2"))
+ ns2_init();
+
++ if (of_machine_is_compatible("marvell,db-88f6281-bp") ||
++ of_machine_is_compatible("marvell,db-88f6282-bp"))
++ db88f628x_init();
++
+ if (of_machine_is_compatible("mpl,cec4"))
+ mplcec4_init();
+
+@@ -181,6 +185,8 @@ static const char * const kirkwood_dt_board_compat[] = {
+ "lacie,netspace_max_v2",
+ "lacie,netspace_mini_v2",
+ "lacie,netspace_v2",
++ "marvell,db-88f6281-bp",
++ "marvell,db-88f6282-bp",
+ "mpl,cec4",
+ "netgear,readynas-duo-v2",
+ "plathome,openblocks-a6",
+diff --git a/arch/arm/mach-kirkwood/common.h b/arch/arm/mach-kirkwood/common.h
+index 21da3b1..cbbc0b8 100644
+--- a/arch/arm/mach-kirkwood/common.h
++++ b/arch/arm/mach-kirkwood/common.h
+@@ -119,6 +119,12 @@ void km_kirkwood_init(void);
+ static inline void km_kirkwood_init(void) {};
+ #endif
+
++#ifdef CONFIG_MACH_DB88F628X_BP_DT
++void db88f628x_init(void);
++#else
++static inline void db88f628x_init(void) {};
++#endif
++
+ #ifdef CONFIG_MACH_MPLCEC4_DT
+ void mplcec4_init(void);
+ #else
+diff --git a/arch/arm/mach-kirkwood/db88f6281-bp-setup.c b/arch/arm/mach-kirkwood/db88f6281-bp-setup.c
+deleted file mode 100644
+index 5a369fe..0000000
+--- a/arch/arm/mach-kirkwood/db88f6281-bp-setup.c
++++ /dev/null
+@@ -1,108 +0,0 @@
+-/*
+- * arch/arm/mach-kirkwood/db88f6281-bp-setup.c
+- *
+- * Marvell DB-88F6281-BP Development Board Setup
+- *
+- * This file is licensed under the terms of the GNU General Public
+- * License version 2. This program is licensed "as is" without any
+- * warranty of any kind, whether express or implied.
+- */
+-
+-#include <linux/kernel.h>
+-#include <linux/init.h>
+-#include <linux/sizes.h>
+-#include <linux/platform_device.h>
+-#include <linux/mtd/partitions.h>
+-#include <linux/ata_platform.h>
+-#include <linux/mv643xx_eth.h>
+-#include <asm/mach-types.h>
+-#include <asm/mach/arch.h>
+-#include <mach/kirkwood.h>
+-#include <linux/platform_data/mmc-mvsdio.h>
+-#include "common.h"
+-#include "mpp.h"
+-
+-static struct mtd_partition db88f6281_nand_parts[] = {
+- {
+- .name = "u-boot",
+- .offset = 0,
+- .size = SZ_1M
+- }, {
+- .name = "uImage",
+- .offset = MTDPART_OFS_NXTBLK,
+- .size = SZ_4M
+- }, {
+- .name = "root",
+- .offset = MTDPART_OFS_NXTBLK,
+- .size = MTDPART_SIZ_FULL
+- },
+-};
+-
+-static struct mv643xx_eth_platform_data db88f6281_ge00_data = {
+- .phy_addr = MV643XX_ETH_PHY_ADDR(8),
+-};
+-
+-static struct mv_sata_platform_data db88f6281_sata_data = {
+- .n_ports = 2,
+-};
+-
+-static struct mvsdio_platform_data db88f6281_mvsdio_data = {
+- .gpio_write_protect = 37,
+- .gpio_card_detect = 38,
+-};
+-
+-static unsigned int db88f6281_mpp_config[] __initdata = {
+- MPP0_NF_IO2,
+- MPP1_NF_IO3,
+- MPP2_NF_IO4,
+- MPP3_NF_IO5,
+- MPP4_NF_IO6,
+- MPP5_NF_IO7,
+- MPP18_NF_IO0,
+- MPP19_NF_IO1,
+- MPP37_GPIO,
+- MPP38_GPIO,
+- 0
+-};
+-
+-static void __init db88f6281_init(void)
+-{
+- /*
+- * Basic setup. Needs to be called early.
+- */
+- kirkwood_init();
+- kirkwood_mpp_conf(db88f6281_mpp_config);
+-
+- kirkwood_nand_init(ARRAY_AND_SIZE(db88f6281_nand_parts), 25);
+- kirkwood_ehci_init();
+- kirkwood_ge00_init(&db88f6281_ge00_data);
+- kirkwood_sata_init(&db88f6281_sata_data);
+- kirkwood_uart0_init();
+- kirkwood_sdio_init(&db88f6281_mvsdio_data);
+-}
+-
+-static int __init db88f6281_pci_init(void)
+-{
+- if (machine_is_db88f6281_bp()) {
+- u32 dev, rev;
+-
+- kirkwood_pcie_id(&dev, &rev);
+- if (dev == MV88F6282_DEV_ID)
+- kirkwood_pcie_init(KW_PCIE1 | KW_PCIE0);
+- else
+- kirkwood_pcie_init(KW_PCIE0);
+- }
+- return 0;
+-}
+-subsys_initcall(db88f6281_pci_init);
+-
+-MACHINE_START(DB88F6281_BP, "Marvell DB-88F6281-BP Development Board")
+- /* Maintainer: Saeed Bishara <saeed@marvell.com> */
+- .atag_offset = 0x100,
+- .init_machine = db88f6281_init,
+- .map_io = kirkwood_map_io,
+- .init_early = kirkwood_init_early,
+- .init_irq = kirkwood_init_irq,
+- .init_time = kirkwood_timer_init,
+- .restart = kirkwood_restart,
+-MACHINE_END
+--
+1.8.4.rc1
+
--- /dev/null
+From f53bb70209838ffea1824ba7c4c7935cf200233f Mon Sep 17 00:00:00 2001
+From: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
+Date: Thu, 11 Apr 2013 00:18:29 +0200
+Subject: [PATCH 17/29] arm: kirkwood: update defconfig with PCIe driver and
+ board updates
+
+This commit enables the mvebu PCIe driver in kirkwood_defconfig and
+updates various options related to Kirkwood boards.
+
+Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
+---
+ arch/arm/configs/kirkwood_defconfig | 2 ++
+ 1 file changed, 2 insertions(+)
+
+diff --git a/arch/arm/configs/kirkwood_defconfig b/arch/arm/configs/kirkwood_defconfig
+index a1d8252..452adec 100644
+--- a/arch/arm/configs/kirkwood_defconfig
++++ b/arch/arm/configs/kirkwood_defconfig
+@@ -31,6 +31,7 @@ CONFIG_MACH_T5325=y
+ CONFIG_MACH_TS219=y
+ CONFIG_MACH_TS41X=y
+ CONFIG_MACH_CLOUDBOX_DT=y
++CONFIG_MACH_DB88F628X_BP_DT=y
+ CONFIG_MACH_DLINK_KIRKWOOD_DT=y
+ CONFIG_MACH_DOCKSTAR_DT=y
+ CONFIG_MACH_DREAMPLUG_DT=y
+@@ -53,6 +54,7 @@ CONFIG_MACH_READYNAS_DT=y
+ CONFIG_MACH_TOPKICK_DT=y
+ CONFIG_MACH_TS219_DT=y
+ # CONFIG_CPU_FEROCEON_OLD_ID is not set
++CONFIG_PCI_MVEBU=y
+ CONFIG_PREEMPT=y
+ CONFIG_AEABI=y
+ # CONFIG_OABI_COMPAT is not set
+--
+1.8.4.rc1
+
--- /dev/null
+From 40a635881d8fedff7242598cd3bf892e4733f7dc Mon Sep 17 00:00:00 2001
+From: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
+Date: Wed, 29 May 2013 21:32:43 +0200
+Subject: [PATCH 18/29] net: mv643xx_eth: use phy_disconnect instead of
+ phy_detach
+
+Using a separated mdio bus driver with mvmdio, phy_detach on network device
+removal will not stop the phy and finally lead to NULL pointer dereference
+in mvmdio due to non-existent network device. Use phy_disconnect instead
+to properly stop phy device from accessing network device prior removal of
+the network device.
+
+Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
+---
+ drivers/net/ethernet/marvell/mv643xx_eth.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/drivers/net/ethernet/marvell/mv643xx_eth.c b/drivers/net/ethernet/marvell/mv643xx_eth.c
+index d1cbfb1..748dcd3 100644
+--- a/drivers/net/ethernet/marvell/mv643xx_eth.c
++++ b/drivers/net/ethernet/marvell/mv643xx_eth.c
+@@ -2805,7 +2805,7 @@ static int mv643xx_eth_remove(struct platform_device *pdev)
+
+ unregister_netdev(mp->dev);
+ if (mp->phy != NULL)
+- phy_detach(mp->phy);
++ phy_disconnect(mp->phy);
+ cancel_work_sync(&mp->tx_timeout_task);
+
+ if (!IS_ERR(mp->clk))
+--
+1.8.4.rc1
+
--- /dev/null
+From ba7ccfb6824e89ea6175abcf854e7808597a2c40 Mon Sep 17 00:00:00 2001
+From: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
+Date: Wed, 29 May 2013 21:32:44 +0200
+Subject: [PATCH 19/29] net: mv643xx_eth: use managed devm_ioremap for port
+ registers
+
+Make use of managed devm_ioremap and remove corresponding iounmap.
+
+Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
+---
+ drivers/net/ethernet/marvell/mv643xx_eth.c | 3 +--
+ 1 file changed, 1 insertion(+), 2 deletions(-)
+
+diff --git a/drivers/net/ethernet/marvell/mv643xx_eth.c b/drivers/net/ethernet/marvell/mv643xx_eth.c
+index 748dcd3..0a8c064 100644
+--- a/drivers/net/ethernet/marvell/mv643xx_eth.c
++++ b/drivers/net/ethernet/marvell/mv643xx_eth.c
+@@ -2470,7 +2470,7 @@ static int mv643xx_eth_shared_probe(struct platform_device *pdev)
+ if (msp == NULL)
+ return -ENOMEM;
+
+- msp->base = ioremap(res->start, resource_size(res));
++ msp->base = devm_ioremap(&pdev->dev, res->start, resource_size(res));
+ if (msp->base == NULL)
+ return -ENOMEM;
+
+@@ -2498,7 +2498,6 @@ static int mv643xx_eth_shared_remove(struct platform_device *pdev)
+ {
+ struct mv643xx_eth_shared_private *msp = platform_get_drvdata(pdev);
+
+- iounmap(msp->base);
+ if (!IS_ERR(msp->clk))
+ clk_disable_unprepare(msp->clk);
+
+--
+1.8.4.rc1
+
--- /dev/null
+From 76a09d3052c7c1c5d4a3fcdfee3a12cfc998d58f Mon Sep 17 00:00:00 2001
+From: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
+Date: Wed, 29 May 2013 21:32:45 +0200
+Subject: [PATCH 20/29] net: mv643xx_eth: add phy_node to platform_data struct
+
+This adds a struct device_node pointer for a phy passed by phandle
+to mv643xx_eth node.
+
+Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
+---
+ include/linux/mv643xx_eth.h | 2 ++
+ 1 file changed, 2 insertions(+)
+
+diff --git a/include/linux/mv643xx_eth.h b/include/linux/mv643xx_eth.h
+index 141d395..6e8215b 100644
+--- a/include/linux/mv643xx_eth.h
++++ b/include/linux/mv643xx_eth.h
+@@ -30,6 +30,7 @@ struct mv643xx_eth_shared_platform_data {
+ #define MV643XX_ETH_PHY_ADDR(x) (0x80 | (x))
+ #define MV643XX_ETH_PHY_NONE 0xff
+
++struct device_node;
+ struct mv643xx_eth_platform_data {
+ /*
+ * Pointer back to our parent instance, and our port number.
+@@ -41,6 +42,7 @@ struct mv643xx_eth_platform_data {
+ * Whether a PHY is present, and if yes, at which address.
+ */
+ int phy_addr;
++ struct device_node *phy_node;
+
+ /*
+ * Use this MAC address if it is valid, overriding the
+--
+1.8.4.rc1
+
--- /dev/null
+From 04417da7ac6d1a2a38d4406d899ab92bf6e488e1 Mon Sep 17 00:00:00 2001
+From: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
+Date: Wed, 29 May 2013 21:32:46 +0200
+Subject: [PATCH 21/29] net: mv643xx_eth: use of_phy_connect if phy_node
+ present
+
+This connects to a phy node passed to the port device instead of probing
+the phy by phy_addr.
+
+Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
+---
+ drivers/net/ethernet/marvell/mv643xx_eth.c | 25 ++++++++++++++++++-------
+ 1 file changed, 18 insertions(+), 7 deletions(-)
+
+diff --git a/drivers/net/ethernet/marvell/mv643xx_eth.c b/drivers/net/ethernet/marvell/mv643xx_eth.c
+index 0a8c064..946033b 100644
+--- a/drivers/net/ethernet/marvell/mv643xx_eth.c
++++ b/drivers/net/ethernet/marvell/mv643xx_eth.c
+@@ -60,6 +60,7 @@
+ #include <linux/types.h>
+ #include <linux/slab.h>
+ #include <linux/clk.h>
++#include <linux/of_mdio.h>
+
+ static char mv643xx_eth_driver_name[] = "mv643xx_eth";
+ static char mv643xx_eth_driver_version[] = "1.4";
+@@ -2715,17 +2716,27 @@ static int mv643xx_eth_probe(struct platform_device *pdev)
+ netif_set_real_num_tx_queues(dev, mp->txq_count);
+ netif_set_real_num_rx_queues(dev, mp->rxq_count);
+
+- if (pd->phy_addr != MV643XX_ETH_PHY_NONE) {
++ err = 0;
++ if (pd->phy_node) {
++ mp->phy = of_phy_connect(mp->dev, pd->phy_node,
++ mv643xx_eth_adjust_link, 0,
++ PHY_INTERFACE_MODE_GMII);
++ if (!mp->phy)
++ err = -ENODEV;
++ } else if (pd->phy_addr != MV643XX_ETH_PHY_NONE) {
+ mp->phy = phy_scan(mp, pd->phy_addr);
+
+- if (IS_ERR(mp->phy)) {
++ if (IS_ERR(mp->phy))
+ err = PTR_ERR(mp->phy);
+- if (err == -ENODEV)
+- err = -EPROBE_DEFER;
+- goto out;
+- }
+- phy_init(mp, pd->speed, pd->duplex);
++ else
++ phy_init(mp, pd->speed, pd->duplex);
+ }
++ if (err == -ENODEV) {
++ err = -EPROBE_DEFER;
++ goto out;
++ }
++ if (err)
++ goto out;
+
+ SET_ETHTOOL_OPS(dev, &mv643xx_eth_ethtool_ops);
+
+--
+1.8.4.rc1
+
--- /dev/null
+From 3b0f26629fef1b55a71031b4ef4db27d0a66a0be Mon Sep 17 00:00:00 2001
+From: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
+Date: Wed, 29 May 2013 21:32:47 +0200
+Subject: [PATCH 22/29] net: mv643xx_eth: proper initialization for Kirkwood
+ SoCs
+
+Ethernet controllers found on Kirkwood SoCs not only suffer from loosing
+MAC address register contents on clock gating but also some important
+registers are reset to values that would break ethernet. This patch
+clears the CLK125_BYPASS_EN bit for DT enabled Kirkwood only by using
+of_device_is_compatible() instead of #ifdefs. Non-DT Kirkwood is not
+affected as it installs a clock gating workaround because of the MAC
+address issue above. Other Orion SoCs do not suffer from register reset,
+do not have the bit in question, or do not have the register at all.
+Moreover, system controllers on PPC using this driver should also be
+protected from clearing that bit.
+
+Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
+---
+ drivers/net/ethernet/marvell/mv643xx_eth.c | 11 +++++++++++
+ 1 file changed, 11 insertions(+)
+
+diff --git a/drivers/net/ethernet/marvell/mv643xx_eth.c b/drivers/net/ethernet/marvell/mv643xx_eth.c
+index 946033b..af6bdcc 100644
+--- a/drivers/net/ethernet/marvell/mv643xx_eth.c
++++ b/drivers/net/ethernet/marvell/mv643xx_eth.c
+@@ -116,6 +116,8 @@ static char mv643xx_eth_driver_version[] = "1.4";
+ #define LINK_UP 0x00000002
+ #define TXQ_COMMAND 0x0048
+ #define TXQ_FIX_PRIO_CONF 0x004c
++#define PORT_SERIAL_CONTROL1 0x004c
++#define CLK125_BYPASS_EN 0x00000010
+ #define TX_BW_RATE 0x0050
+ #define TX_BW_MTU 0x0058
+ #define TX_BW_BURST 0x005c
+@@ -2701,6 +2703,15 @@ static int mv643xx_eth_probe(struct platform_device *pdev)
+
+ mp->dev = dev;
+
++ /* Kirkwood resets some registers on gated clocks. Especially
++ * CLK125_BYPASS_EN must be cleared but is not available on
++ * all other SoCs/System Controllers using this driver.
++ */
++ if (of_device_is_compatible(pdev->dev.of_node,
++ "marvell,kirkwood-eth-port"))
++ wrlp(mp, PORT_SERIAL_CONTROL1,
++ rdlp(mp, PORT_SERIAL_CONTROL1) & ~CLK125_BYPASS_EN);
++
+ /*
+ * Start with a default rate, and if there is a clock, allow
+ * it to override the default.
+--
+1.8.4.rc1
+
--- /dev/null
+From dd6cae3b60ee88b301f9325db144e70b5e12482e Mon Sep 17 00:00:00 2001
+From: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
+Date: Wed, 29 May 2013 21:32:48 +0200
+Subject: [PATCH 23/29] net: mv643xx_eth: add DT parsing support
+
+This adds device tree parsing support for the shared driver of mv643xx_eth.
+As the bindings are slightly different from current PPC bindings new binding
+documentation is also added. Following PPC-style device setup, the shared
+driver now also adds port platform_devices and sets up port platform_data.
+
+Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
+---
+ .../devicetree/bindings/net/marvell-orion-net.txt | 85 ++++++++++++
+ drivers/net/ethernet/marvell/mv643xx_eth.c | 153 ++++++++++++++++++++-
+ 2 files changed, 234 insertions(+), 4 deletions(-)
+ create mode 100644 Documentation/devicetree/bindings/net/marvell-orion-net.txt
+
+diff --git a/Documentation/devicetree/bindings/net/marvell-orion-net.txt b/Documentation/devicetree/bindings/net/marvell-orion-net.txt
+new file mode 100644
+index 0000000..a73b79f
+--- /dev/null
++++ b/Documentation/devicetree/bindings/net/marvell-orion-net.txt
+@@ -0,0 +1,85 @@
++Marvell Orion/Discovery ethernet controller
++=============================================
++
++The Marvell Discovery ethernet controller can be found on Marvell Orion SoCs
++(Kirkwood, Dove, Orion5x, and Discovery Innovation) and as part of Marvell
++Discovery system controller chips (mv64[345]60).
++
++The Discovery ethernet controller is described with two levels of nodes. The
++first level describes the ethernet controller itself and the second level
++describes up to 3 ethernet port nodes within that controller. The reason for
++the multiple levels is that the port registers are interleaved within a single
++set of controller registers. Each port node describes port-specific properties.
++
++Note: The above separation is only true for Discovery system controllers.
++For Orion SoCs we stick to the separation, although there each controller has
++only one port associated. Multiple ports are implemented as multiple single-port
++controllers. As Kirkwood has some issues with proper initialization after reset,
++an extra compatible string is added for it.
++
++* Ethernet controller node
++
++Required controller properties:
++ - #address-cells: shall be 1.
++ - #size-cells: shall be 0.
++ - compatible: shall be one of "marvell,orion-eth", "marvell,kirkwood-eth".
++ - reg: address and length of the controller registers.
++
++Optional controller properties:
++ - clocks: phandle reference to the controller clock.
++ - marvell,tx-checksum-limit: max tx packet size for hardware checksum.
++
++* Ethernet port node
++
++Required port properties:
++ - device_type: shall be "network".
++ - compatible: shall be one of "marvell,orion-eth-port",
++ "marvell,kirkwood-eth-port".
++ - reg: port number relative to ethernet controller, shall be 0, 1, or 2.
++ - interrupts: port interrupt.
++ - local-mac-address: 6 bytes MAC address.
++
++Optional port properties:
++ - marvell,tx-queue-size: size of the transmit ring buffer.
++ - marvell,tx-sram-addr: address of transmit descriptor buffer located in SRAM.
++ - marvell,tx-sram-size: size of transmit descriptor buffer located in SRAM.
++ - marvell,rx-queue-size: size of the receive ring buffer.
++ - marvell,rx-sram-addr: address of receive descriptor buffer located in SRAM.
++ - marvell,rx-sram-size: size of receive descriptor buffer located in SRAM.
++
++and
++
++ - phy-handle: phandle reference to ethernet PHY.
++
++or
++
++ - speed: port speed if no PHY connected.
++ - duplex: port mode if no PHY connected.
++
++* Node example:
++
++mdio-bus {
++ ...
++ ethphy: ethernet-phy@8 {
++ device_type = "ethernet-phy";
++ ...
++ };
++};
++
++eth: ethernet-controller@72000 {
++ compatible = "marvell,orion-eth";
++ #address-cells = <1>;
++ #size-cells = <0>;
++ reg = <0x72000 0x2000>;
++ clocks = <&gate_clk 2>;
++ marvell,tx-checksum-limit = <1600>;
++
++ ethernet@0 {
++ device_type = "network";
++ compatible = "marvell,orion-eth-port";
++ reg = <0>;
++ interrupts = <29>;
++ phy-handle = <ðphy>;
++ local-mac-address = [00 00 00 00 00 00];
++ };
++};
+diff --git a/drivers/net/ethernet/marvell/mv643xx_eth.c b/drivers/net/ethernet/marvell/mv643xx_eth.c
+index af6bdcc..004a250 100644
+--- a/drivers/net/ethernet/marvell/mv643xx_eth.c
++++ b/drivers/net/ethernet/marvell/mv643xx_eth.c
+@@ -60,6 +60,9 @@
+ #include <linux/types.h>
+ #include <linux/slab.h>
+ #include <linux/clk.h>
++#include <linux/of.h>
++#include <linux/of_irq.h>
++#include <linux/of_net.h>
+ #include <linux/of_mdio.h>
+
+ static char mv643xx_eth_driver_name[] = "mv643xx_eth";
+@@ -2453,13 +2456,148 @@ static void infer_hw_params(struct mv643xx_eth_shared_private *msp)
+ }
+ }
+
++#if defined(CONFIG_OF)
++static const struct of_device_id mv643xx_eth_shared_ids[] = {
++ { .compatible = "marvell,orion-eth", },
++ { .compatible = "marvell,kirkwood-eth", },
++ { }
++};
++MODULE_DEVICE_TABLE(of, mv643xx_eth_shared_ids);
++#endif
++
++#if defined(CONFIG_OF) && !defined(CONFIG_MV64X60)
++#define mv643xx_eth_property(_np, _name, _v) \
++ do { \
++ u32 tmp; \
++ if (!of_property_read_u32(_np, "marvell," _name, &tmp)) \
++ _v = tmp; \
++ } while (0)
++
++static struct platform_device *port_platdev[3];
++
++static int mv643xx_eth_shared_of_add_port(struct platform_device *pdev,
++ struct device_node *pnp)
++{
++ struct platform_device *ppdev;
++ struct mv643xx_eth_platform_data ppd;
++ struct resource res;
++ const char *mac_addr;
++ int ret;
++
++ memset(&ppd, 0, sizeof(ppd));
++ ppd.shared = pdev;
++
++ memset(&res, 0, sizeof(res));
++ if (!of_irq_to_resource(pnp, 0, &res)) {
++ dev_err(&pdev->dev, "missing interrupt on %s\n", pnp->name);
++ return -EINVAL;
++ }
++
++ if (of_property_read_u32(pnp, "reg", &ppd.port_number)) {
++ dev_err(&pdev->dev, "missing reg property on %s\n", pnp->name);
++ return -EINVAL;
++ }
++
++ if (ppd.port_number >= 3) {
++ dev_err(&pdev->dev, "invalid reg property on %s\n", pnp->name);
++ return -EINVAL;
++ }
++
++ mac_addr = of_get_mac_address(pnp);
++ if (mac_addr)
++ memcpy(ppd.mac_addr, mac_addr, 6);
++
++ mv643xx_eth_property(pnp, "tx-queue-size", ppd.tx_queue_size);
++ mv643xx_eth_property(pnp, "tx-sram-addr", ppd.tx_sram_addr);
++ mv643xx_eth_property(pnp, "tx-sram-size", ppd.tx_sram_size);
++ mv643xx_eth_property(pnp, "rx-queue-size", ppd.rx_queue_size);
++ mv643xx_eth_property(pnp, "rx-sram-addr", ppd.rx_sram_addr);
++ mv643xx_eth_property(pnp, "rx-sram-size", ppd.rx_sram_size);
++
++ ppd.phy_node = of_parse_phandle(pnp, "phy-handle", 0);
++ if (!ppd.phy_node) {
++ ppd.phy_addr = MV643XX_ETH_PHY_NONE;
++ of_property_read_u32(pnp, "speed", &ppd.speed);
++ of_property_read_u32(pnp, "duplex", &ppd.duplex);
++ }
++
++ ppdev = platform_device_alloc(MV643XX_ETH_NAME, ppd.port_number);
++ if (!ppdev)
++ return -ENOMEM;
++ ppdev->dev.coherent_dma_mask = DMA_BIT_MASK(32);
++
++ ret = platform_device_add_resources(ppdev, &res, 1);
++ if (ret)
++ goto port_err;
++
++ ret = platform_device_add_data(ppdev, &ppd, sizeof(ppd));
++ if (ret)
++ goto port_err;
++
++ ret = platform_device_add(ppdev);
++ if (ret)
++ goto port_err;
++
++ port_platdev[ppd.port_number] = ppdev;
++
++ return 0;
++
++port_err:
++ platform_device_put(ppdev);
++ return ret;
++}
++
++static int mv643xx_eth_shared_of_probe(struct platform_device *pdev)
++{
++ struct mv643xx_eth_shared_platform_data *pd;
++ struct device_node *pnp, *np = pdev->dev.of_node;
++ int ret;
++
++ /* bail out if not registered from DT */
++ if (!np)
++ return 0;
++
++ pd = devm_kzalloc(&pdev->dev, sizeof(*pd), GFP_KERNEL);
++ if (!pd)
++ return -ENOMEM;
++ pdev->dev.platform_data = pd;
++
++ mv643xx_eth_property(np, "tx-checksum-limit", pd->tx_csum_limit);
++
++ for_each_available_child_of_node(np, pnp) {
++ ret = mv643xx_eth_shared_of_add_port(pdev, pnp);
++ if (ret)
++ return ret;
++ }
++ return 0;
++}
++
++static void mv643xx_eth_shared_of_remove(void)
++{
++ int n;
++
++ for (n = 0; n < 3; n++) {
++ platform_device_del(port_platdev[n]);
++ port_platdev[n] = NULL;
++ }
++}
++#else
++static int mv643xx_eth_shared_of_probe(struct platform_device *pdev)
++{
++ return 0
++}
++
++#define mv643xx_eth_shared_of_remove()
++#endif
++
+ static int mv643xx_eth_shared_probe(struct platform_device *pdev)
+ {
+ static int mv643xx_eth_version_printed;
+- struct mv643xx_eth_shared_platform_data *pd = pdev->dev.platform_data;
++ struct mv643xx_eth_shared_platform_data *pd;
+ struct mv643xx_eth_shared_private *msp;
+ const struct mbus_dram_target_info *dram;
+ struct resource *res;
++ int ret;
+
+ if (!mv643xx_eth_version_printed++)
+ pr_notice("MV-643xx 10/100/1000 ethernet driver version %s\n",
+@@ -2472,6 +2610,7 @@ static int mv643xx_eth_shared_probe(struct platform_device *pdev)
+ msp = devm_kzalloc(&pdev->dev, sizeof(*msp), GFP_KERNEL);
+ if (msp == NULL)
+ return -ENOMEM;
++ platform_set_drvdata(pdev, msp);
+
+ msp->base = devm_ioremap(&pdev->dev, res->start, resource_size(res));
+ if (msp->base == NULL)
+@@ -2488,12 +2627,15 @@ static int mv643xx_eth_shared_probe(struct platform_device *pdev)
+ if (dram)
+ mv643xx_eth_conf_mbus_windows(msp, dram);
+
++ ret = mv643xx_eth_shared_of_probe(pdev);
++ if (ret)
++ return ret;
++ pd = pdev->dev.platform_data;
++
+ msp->tx_csum_limit = (pd != NULL && pd->tx_csum_limit) ?
+ pd->tx_csum_limit : 9 * 1024;
+ infer_hw_params(msp);
+
+- platform_set_drvdata(pdev, msp);
+-
+ return 0;
+ }
+
+@@ -2501,9 +2643,9 @@ static int mv643xx_eth_shared_remove(struct platform_device *pdev)
+ {
+ struct mv643xx_eth_shared_private *msp = platform_get_drvdata(pdev);
+
++ mv643xx_eth_shared_of_remove();
+ if (!IS_ERR(msp->clk))
+ clk_disable_unprepare(msp->clk);
+-
+ return 0;
+ }
+
+@@ -2513,6 +2655,7 @@ static struct platform_driver mv643xx_eth_shared_driver = {
+ .driver = {
+ .name = MV643XX_ETH_SHARED_NAME,
+ .owner = THIS_MODULE,
++ .of_match_table = of_match_ptr(mv643xx_eth_shared_ids),
+ },
+ };
+
+@@ -2721,6 +2864,8 @@ static int mv643xx_eth_probe(struct platform_device *pdev)
+ if (!IS_ERR(mp->clk)) {
+ clk_prepare_enable(mp->clk);
+ mp->t_clk = clk_get_rate(mp->clk);
++ } else if (!IS_ERR(mp->shared->clk)) {
++ mp->t_clk = clk_get_rate(mp->shared->clk);
+ }
+
+ set_params(mp, pd);
+--
+1.8.4.rc1
+
--- /dev/null
+From 81547b563bd8340d98cdf2c020449ef2e7e8821d Mon Sep 17 00:00:00 2001
+From: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
+Date: Tue, 2 Jul 2013 13:00:19 +0200
+Subject: [PATCH 24/29] ARM: kirkwood: add gigabit ethernet and mvmdio device
+ tree nodes
+
+This patch adds mv643xx_eth and mvmdio device tree nodes for DT enabled
+Kirkwood boards. Phy nodes are also added with reg property set on a
+per-board basis.
+
+Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
+---
+ arch/arm/boot/dts/kirkwood-cloudbox.dts | 16 +++++++
+ arch/arm/boot/dts/kirkwood-db.dtsi | 16 +++++++
+ arch/arm/boot/dts/kirkwood-dnskw.dtsi | 16 +++++++
+ arch/arm/boot/dts/kirkwood-dockstar.dts | 17 +++++++
+ arch/arm/boot/dts/kirkwood-dreamplug.dts | 28 ++++++++++++
+ arch/arm/boot/dts/kirkwood-goflexnet.dts | 16 +++++++
+ .../arm/boot/dts/kirkwood-guruplug-server-plus.dts | 30 +++++++++++++
+ arch/arm/boot/dts/kirkwood-ib62x0.dts | 16 +++++++
+ arch/arm/boot/dts/kirkwood-iconnect.dts | 16 +++++++
+ arch/arm/boot/dts/kirkwood-iomega_ix2_200.dts | 24 ++++++++++
+ arch/arm/boot/dts/kirkwood-is2.dts | 2 +
+ arch/arm/boot/dts/kirkwood-km_kirkwood.dts | 16 +++++++
+ arch/arm/boot/dts/kirkwood-lsxl.dtsi | 28 ++++++++++++
+ arch/arm/boot/dts/kirkwood-mplcec4.dts | 27 +++++++++++
+ .../boot/dts/kirkwood-netgear_readynas_duo_v2.dts | 16 +++++++
+ arch/arm/boot/dts/kirkwood-ns2-common.dtsi | 16 +++++++
+ arch/arm/boot/dts/kirkwood-ns2.dts | 2 +
+ arch/arm/boot/dts/kirkwood-ns2lite.dts | 2 +
+ arch/arm/boot/dts/kirkwood-ns2max.dts | 2 +
+ arch/arm/boot/dts/kirkwood-ns2mini.dts | 2 +
+ arch/arm/boot/dts/kirkwood-openblocks_a6.dts | 16 +++++++
+ arch/arm/boot/dts/kirkwood-topkick.dts | 16 +++++++
+ arch/arm/boot/dts/kirkwood-ts219-6281.dts | 4 +-
+ arch/arm/boot/dts/kirkwood-ts219-6282.dts | 4 +-
+ arch/arm/boot/dts/kirkwood-ts219.dtsi | 16 +++++++
+ arch/arm/boot/dts/kirkwood.dtsi | 52 ++++++++++++++++++++++
+ 26 files changed, 414 insertions(+), 2 deletions(-)
+
+diff --git a/arch/arm/boot/dts/kirkwood-cloudbox.dts b/arch/arm/boot/dts/kirkwood-cloudbox.dts
+index 5f21d4e..03e1b68 100644
+--- a/arch/arm/boot/dts/kirkwood-cloudbox.dts
++++ b/arch/arm/boot/dts/kirkwood-cloudbox.dts
+@@ -87,3 +87,19 @@
+ gpios = <&gpio0 17 0>;
+ };
+ };
++
++&mdio {
++ status = "okay";
++
++ ethphy0: ethernet-phy@0 {
++ device_type = "ethernet-phy";
++ reg = <0>;
++ };
++};
++
++ð0 {
++ status = "okay";
++ ethernet0-port@0 {
++ phy-handle = <ðphy0>;
++ };
++};
+diff --git a/arch/arm/boot/dts/kirkwood-db.dtsi b/arch/arm/boot/dts/kirkwood-db.dtsi
+index c87cfb8..ca8bf36 100644
+--- a/arch/arm/boot/dts/kirkwood-db.dtsi
++++ b/arch/arm/boot/dts/kirkwood-db.dtsi
+@@ -87,3 +87,19 @@
+ };
+ };
+ };
++
++&mdio {
++ status = "okay";
++
++ ethphy0: ethernet-phy@8 {
++ device_type = "ethernet-phy";
++ reg = <8>;
++ };
++};
++
++ð0 {
++ status = "okay";
++ ethernet0-port@0 {
++ phy-handle = <ðphy0>;
++ };
++};
+diff --git a/arch/arm/boot/dts/kirkwood-dnskw.dtsi b/arch/arm/boot/dts/kirkwood-dnskw.dtsi
+index 6875ac0..7c8bc17 100644
+--- a/arch/arm/boot/dts/kirkwood-dnskw.dtsi
++++ b/arch/arm/boot/dts/kirkwood-dnskw.dtsi
+@@ -217,3 +217,19 @@
+ };
+ };
+ };
++
++&mdio {
++ status = "okay";
++
++ ethphy0: ethernet-phy@8 {
++ device_type = "ethernet-phy";
++ reg = <8>;
++ };
++};
++
++ð0 {
++ status = "okay";
++ ethernet0-port@0 {
++ phy-handle = <ðphy0>;
++ };
++};
+diff --git a/arch/arm/boot/dts/kirkwood-dockstar.dts b/arch/arm/boot/dts/kirkwood-dockstar.dts
+index 0196cf6..b5aebbc 100644
+--- a/arch/arm/boot/dts/kirkwood-dockstar.dts
++++ b/arch/arm/boot/dts/kirkwood-dockstar.dts
+@@ -91,3 +91,20 @@
+ };
+ };
+ };
++
++&mdio {
++ status = "okay";
++
++ ethphy0: ethernet-phy@0 {
++ device_type = "ethernet-phy";
++ compatible = "marvell,88e1116";
++ reg = <0>;
++ };
++};
++
++ð0 {
++ status = "okay";
++ ethernet0-port@0 {
++ phy-handle = <ðphy0>;
++ };
++};
+diff --git a/arch/arm/boot/dts/kirkwood-dreamplug.dts b/arch/arm/boot/dts/kirkwood-dreamplug.dts
+index 289e51d..e0c93d4 100644
+--- a/arch/arm/boot/dts/kirkwood-dreamplug.dts
++++ b/arch/arm/boot/dts/kirkwood-dreamplug.dts
+@@ -99,3 +99,31 @@
+ };
+ };
+ };
++
++&mdio {
++ status = "okay";
++
++ ethphy0: ethernet-phy@0 {
++ device_type = "ethernet-phy";
++ reg = <0>;
++ };
++
++ ethphy1: ethernet-phy@1 {
++ device_type = "ethernet-phy";
++ reg = <1>;
++ };
++};
++
++ð0 {
++ status = "okay";
++ ethernet0-port@0 {
++ phy-handle = <ðphy0>;
++ };
++};
++
++ð1 {
++ status = "okay";
++ ethernet1-port@0 {
++ phy-handle = <ðphy1>;
++ };
++};
+diff --git a/arch/arm/boot/dts/kirkwood-goflexnet.dts b/arch/arm/boot/dts/kirkwood-goflexnet.dts
+index c3573be..aba5849 100644
+--- a/arch/arm/boot/dts/kirkwood-goflexnet.dts
++++ b/arch/arm/boot/dts/kirkwood-goflexnet.dts
+@@ -170,3 +170,19 @@
+ };
+ };
+ };
++
++&mdio {
++ status = "okay";
++
++ ethphy0: ethernet-phy@0 {
++ device_type = "ethernet-phy";
++ reg = <0>;
++ };
++};
++
++ð0 {
++ status = "okay";
++ ethernet0-port@0 {
++ phy-handle = <ðphy0>;
++ };
++};
+diff --git a/arch/arm/boot/dts/kirkwood-guruplug-server-plus.dts b/arch/arm/boot/dts/kirkwood-guruplug-server-plus.dts
+index 44fd97d..210dfb9 100644
+--- a/arch/arm/boot/dts/kirkwood-guruplug-server-plus.dts
++++ b/arch/arm/boot/dts/kirkwood-guruplug-server-plus.dts
+@@ -96,3 +96,33 @@
+ };
+ };
+ };
++
++&mdio {
++ status = "okay";
++
++ ethphy0: ethernet-phy@0 {
++ device_type = "ethernet-phy";
++ compatible = "marvell,88e1121";
++ reg = <0>;
++ };
++
++ ethphy1: ethernet-phy@1 {
++ device_type = "ethernet-phy";
++ compatible = "marvell,88e1121";
++ reg = <1>;
++ };
++};
++
++ð0 {
++ status = "okay";
++ ethernet0-port@0 {
++ phy-handle = <ðphy0>;
++ };
++};
++
++ð1 {
++ status = "okay";
++ ethernet1-port@0 {
++ phy-handle = <ðphy1>;
++ };
++};
+diff --git a/arch/arm/boot/dts/kirkwood-ib62x0.dts b/arch/arm/boot/dts/kirkwood-ib62x0.dts
+index 5335b1a..fff3e65 100644
+--- a/arch/arm/boot/dts/kirkwood-ib62x0.dts
++++ b/arch/arm/boot/dts/kirkwood-ib62x0.dts
+@@ -119,3 +119,19 @@
+
+
+ };
++
++&mdio {
++ status = "okay";
++
++ ethphy0: ethernet-phy@8 {
++ device_type = "ethernet-phy";
++ reg = <8>;
++ };
++};
++
++ð0 {
++ status = "okay";
++ ethernet0-port@0 {
++ phy-handle = <ðphy0>;
++ };
++};
+diff --git a/arch/arm/boot/dts/kirkwood-iconnect.dts b/arch/arm/boot/dts/kirkwood-iconnect.dts
+index e591d5d..9fe8ba2 100644
+--- a/arch/arm/boot/dts/kirkwood-iconnect.dts
++++ b/arch/arm/boot/dts/kirkwood-iconnect.dts
+@@ -176,3 +176,19 @@
+ };
+ };
+ };
++
++&mdio {
++ status = "okay";
++
++ ethphy0: ethernet-phy@11 {
++ device_type = "ethernet-phy";
++ reg = <11>;
++ };
++};
++
++ð0 {
++ status = "okay";
++ ethernet0-port@0 {
++ phy-handle = <ðphy0>;
++ };
++};
+diff --git a/arch/arm/boot/dts/kirkwood-iomega_ix2_200.dts b/arch/arm/boot/dts/kirkwood-iomega_ix2_200.dts
+index 3694e94..315f095 100644
+--- a/arch/arm/boot/dts/kirkwood-iomega_ix2_200.dts
++++ b/arch/arm/boot/dts/kirkwood-iomega_ix2_200.dts
+@@ -191,3 +191,27 @@
+ };
+ };
+ };
++
++&mdio {
++ status = "okay";
++
++ ethphy1: ethernet-phy@11 {
++ device_type = "ethernet-phy";
++ reg = <11>;
++ };
++};
++
++ð0 {
++ status = "okay";
++ ethernet0-port@0 {
++ speed = <1000>;
++ duplex = <1>;
++ };
++};
++
++ð1 {
++ status = "okay";
++ ethernet1-port@0 {
++ phy-handle = <ðphy1>;
++ };
++};
+diff --git a/arch/arm/boot/dts/kirkwood-is2.dts b/arch/arm/boot/dts/kirkwood-is2.dts
+index 0bdce0a..2e5fe72 100644
+--- a/arch/arm/boot/dts/kirkwood-is2.dts
++++ b/arch/arm/boot/dts/kirkwood-is2.dts
+@@ -28,3 +28,5 @@
+ };
+ };
+ };
++
++ðphy0 { reg = <8>; };
+diff --git a/arch/arm/boot/dts/kirkwood-km_kirkwood.dts b/arch/arm/boot/dts/kirkwood-km_kirkwood.dts
+index 5bbd054..f9194b1 100644
+--- a/arch/arm/boot/dts/kirkwood-km_kirkwood.dts
++++ b/arch/arm/boot/dts/kirkwood-km_kirkwood.dts
+@@ -43,3 +43,19 @@
+ };
+ };
+ };
++
++&mdio {
++ status = "okay";
++
++ ethphy0: ethernet-phy@0 {
++ device_type = "ethernet-phy";
++ reg = <0>;
++ };
++};
++
++ð0 {
++ status = "okay";
++ ethernet0-port@0 {
++ phy-handle = <ðphy0>;
++ };
++};
+diff --git a/arch/arm/boot/dts/kirkwood-lsxl.dtsi b/arch/arm/boot/dts/kirkwood-lsxl.dtsi
+index 37d45c4..dcc6470 100644
+--- a/arch/arm/boot/dts/kirkwood-lsxl.dtsi
++++ b/arch/arm/boot/dts/kirkwood-lsxl.dtsi
+@@ -201,3 +201,31 @@
+ };
+ };
+ };
++
++&mdio {
++ status = "okay";
++
++ ethphy0: ethernet-phy@0 {
++ device_type = "ethernet-phy";
++ reg = <0>;
++ };
++
++ ethphy1: ethernet-phy@8 {
++ device_type = "ethernet-phy";
++ reg = <8>;
++ };
++};
++
++ð0 {
++ status = "okay";
++ ethernet0-port@0 {
++ phy-handle = <ðphy0>;
++ };
++};
++
++ð1 {
++ status = "okay";
++ ethernet1-port@0 {
++ phy-handle = <ðphy1>;
++ };
++};
+diff --git a/arch/arm/boot/dts/kirkwood-mplcec4.dts b/arch/arm/boot/dts/kirkwood-mplcec4.dts
+index 90501cf..32a0133 100644
+--- a/arch/arm/boot/dts/kirkwood-mplcec4.dts
++++ b/arch/arm/boot/dts/kirkwood-mplcec4.dts
+@@ -190,3 +190,30 @@
+ };
+ };
+
++&mdio {
++ status = "okay";
++
++ ethphy0: ethernet-phy@1 {
++ device_type = "ethernet-phy";
++ reg = <1>;
++ };
++
++ ethphy1: ethernet-phy@2 {
++ device_type = "ethernet-phy";
++ reg = <2>;
++ };
++};
++
++ð0 {
++ status = "okay";
++ ethernet0-port@0 {
++ phy-handle = <ðphy0>;
++ };
++};
++
++ð1 {
++ status = "okay";
++ ethernet1-port@0 {
++ phy-handle = <ðphy1>;
++ };
++};
+diff --git a/arch/arm/boot/dts/kirkwood-netgear_readynas_duo_v2.dts b/arch/arm/boot/dts/kirkwood-netgear_readynas_duo_v2.dts
+index 1ca66ab..b66b2cd 100644
+--- a/arch/arm/boot/dts/kirkwood-netgear_readynas_duo_v2.dts
++++ b/arch/arm/boot/dts/kirkwood-netgear_readynas_duo_v2.dts
+@@ -178,3 +178,19 @@
+ };
+ };
+ };
++
++&mdio {
++ status = "okay";
++
++ ethphy0: ethernet-phy@0 {
++ device_type = "ethernet-phy";
++ reg = <0>;
++ };
++};
++
++ð0 {
++ status = "okay";
++ ethernet0-port@0 {
++ phy-handle = <ðphy0>;
++ };
++};
+diff --git a/arch/arm/boot/dts/kirkwood-ns2-common.dtsi b/arch/arm/boot/dts/kirkwood-ns2-common.dtsi
+index 6affd92..6a48bfd 100644
+--- a/arch/arm/boot/dts/kirkwood-ns2-common.dtsi
++++ b/arch/arm/boot/dts/kirkwood-ns2-common.dtsi
+@@ -82,3 +82,19 @@
+ };
+
+ };
++
++&mdio {
++ status = "okay";
++
++ ethphy0: ethernet-phy {
++ device_type = "ethernet-phy";
++ /* overwrite reg property in board file */
++ };
++};
++
++ð0 {
++ status = "okay";
++ ethernet0-port@0 {
++ phy-handle = <ðphy0>;
++ };
++};
+diff --git a/arch/arm/boot/dts/kirkwood-ns2.dts b/arch/arm/boot/dts/kirkwood-ns2.dts
+index f2d36ecf..8ffd552 100644
+--- a/arch/arm/boot/dts/kirkwood-ns2.dts
++++ b/arch/arm/boot/dts/kirkwood-ns2.dts
+@@ -28,3 +28,5 @@
+ };
+ };
+ };
++
++ðphy0 { reg = <8>; };
+diff --git a/arch/arm/boot/dts/kirkwood-ns2lite.dts b/arch/arm/boot/dts/kirkwood-ns2lite.dts
+index b02eb4e..16332f8 100644
+--- a/arch/arm/boot/dts/kirkwood-ns2lite.dts
++++ b/arch/arm/boot/dts/kirkwood-ns2lite.dts
+@@ -28,3 +28,5 @@
+ };
+ };
+ };
++
++ðphy0 { reg = <0>; };
+diff --git a/arch/arm/boot/dts/kirkwood-ns2max.dts b/arch/arm/boot/dts/kirkwood-ns2max.dts
+index bcec4d6..68d767d 100644
+--- a/arch/arm/boot/dts/kirkwood-ns2max.dts
++++ b/arch/arm/boot/dts/kirkwood-ns2max.dts
+@@ -47,3 +47,5 @@
+ };
+ };
+ };
++
++ðphy0 { reg = <8>; };
+diff --git a/arch/arm/boot/dts/kirkwood-ns2mini.dts b/arch/arm/boot/dts/kirkwood-ns2mini.dts
+index adab1ab..5b1b17b 100644
+--- a/arch/arm/boot/dts/kirkwood-ns2mini.dts
++++ b/arch/arm/boot/dts/kirkwood-ns2mini.dts
+@@ -48,3 +48,5 @@
+ };
+ };
+ };
++
++ðphy0 { reg = <0>; };
+diff --git a/arch/arm/boot/dts/kirkwood-openblocks_a6.dts b/arch/arm/boot/dts/kirkwood-openblocks_a6.dts
+index d27f724..f8be3e3 100644
+--- a/arch/arm/boot/dts/kirkwood-openblocks_a6.dts
++++ b/arch/arm/boot/dts/kirkwood-openblocks_a6.dts
+@@ -210,3 +210,19 @@
+ };
+ };
+ };
++
++&mdio {
++ status = "okay";
++
++ ethphy0: ethernet-phy@0 {
++ device_type = "ethernet-phy";
++ reg = <0>;
++ };
++};
++
++ð0 {
++ status = "okay";
++ ethernet0-port@0 {
++ phy-handle = <ðphy0>;
++ };
++};
+diff --git a/arch/arm/boot/dts/kirkwood-topkick.dts b/arch/arm/boot/dts/kirkwood-topkick.dts
+index 66eb45b..34eacf2 100644
+--- a/arch/arm/boot/dts/kirkwood-topkick.dts
++++ b/arch/arm/boot/dts/kirkwood-topkick.dts
+@@ -201,3 +201,19 @@
+ };
+ };
+ };
++
++&mdio {
++ status = "okay";
++
++ ethphy0: ethernet-phy@0 {
++ device_type = "ethernet-phy";
++ reg = <0>;
++ };
++};
++
++ð0 {
++ status = "okay";
++ ethernet0-port@0 {
++ phy-handle = <ðphy0>;
++ };
++};
+diff --git a/arch/arm/boot/dts/kirkwood-ts219-6281.dts b/arch/arm/boot/dts/kirkwood-ts219-6281.dts
+index 42648ab..fff3a3e 100644
+--- a/arch/arm/boot/dts/kirkwood-ts219-6281.dts
++++ b/arch/arm/boot/dts/kirkwood-ts219-6281.dts
+@@ -50,4 +50,6 @@
+ gpios = <&gpio0 16 1>;
+ };
+ };
+-};
+\ No newline at end of file
++};
++
++ðphy0 { reg = <8>; };
+diff --git a/arch/arm/boot/dts/kirkwood-ts219-6282.dts b/arch/arm/boot/dts/kirkwood-ts219-6282.dts
+index 95ceeb9..ed0441a 100644
+--- a/arch/arm/boot/dts/kirkwood-ts219-6282.dts
++++ b/arch/arm/boot/dts/kirkwood-ts219-6282.dts
+@@ -50,4 +50,6 @@
+ gpios = <&gpio1 5 1>;
+ };
+ };
+-};
+\ No newline at end of file
++};
++
++ðphy0 { reg = <0>; };
+diff --git a/arch/arm/boot/dts/kirkwood-ts219.dtsi b/arch/arm/boot/dts/kirkwood-ts219.dtsi
+index 7c022fd..6b063eb 100644
+--- a/arch/arm/boot/dts/kirkwood-ts219.dtsi
++++ b/arch/arm/boot/dts/kirkwood-ts219.dtsi
+@@ -81,3 +81,19 @@
+ };
+ };
+ };
++
++&mdio {
++ status = "okay";
++
++ ethphy0: ethernet-phy {
++ device_type = "ethernet-phy";
++ /* overwrite reg property in board file */
++ };
++};
++
++ð0 {
++ status = "okay";
++ ethernet0-port@0 {
++ phy-handle = <ðphy0>;
++ };
++};
+diff --git a/arch/arm/boot/dts/kirkwood.dtsi b/arch/arm/boot/dts/kirkwood.dtsi
+index 7eef88f..ebc6dc4 100644
+--- a/arch/arm/boot/dts/kirkwood.dtsi
++++ b/arch/arm/boot/dts/kirkwood.dtsi
+@@ -203,5 +203,57 @@
+ clocks = <&gate_clk 4>;
+ status = "disabled";
+ };
++
++ mdio: mdio-bus@72004 {
++ compatible = "marvell,orion-mdio";
++ #address-cells = <1>;
++ #size-cells = <0>;
++ reg = <0x72004 0x84>;
++ interrupts = <46>;
++ clocks = <&gate_clk 0>;
++ status = "disabled";
++
++ /* add phy nodes in board file */
++ };
++
++ eth0: ethernet-controller@72000 {
++ compatible = "marvell,kirkwood-eth";
++ #address-cells = <1>;
++ #size-cells = <0>;
++ reg = <0x72000 0x4000>;
++ clocks = <&gate_clk 0>;
++ marvell,tx-checksum-limit = <1600>;
++ status = "disabled";
++
++ ethernet0-port@0 {
++ device_type = "network";
++ compatible = "marvell,kirkwood-eth-port";
++ reg = <0>;
++ interrupts = <11>;
++ /* overwrite MAC address in bootloader */
++ local-mac-address = [00 00 00 00 00 00];
++ /* set phy-handle property in board file */
++ };
++ };
++
++ eth1: ethernet-controller@76000 {
++ compatible = "marvell,kirkwood-eth";
++ #address-cells = <1>;
++ #size-cells = <0>;
++ reg = <0x76000 0x4000>;
++ clocks = <&gate_clk 19>;
++ marvell,tx-checksum-limit = <1600>;
++ status = "disabled";
++
++ ethernet1-port@0 {
++ device_type = "network";
++ compatible = "marvell,kirkwood-eth-port";
++ reg = <0>;
++ interrupts = <15>;
++ /* overwrite MAC address in bootloader */
++ local-mac-address = [00 00 00 00 00 00];
++ /* set phy-handle property in board file */
++ };
++ };
+ };
+ };
+--
+1.8.4.rc1
+
--- /dev/null
+From 3bfe255171bf03fa4b776e8e10b93d4dbd7df1e8 Mon Sep 17 00:00:00 2001
+From: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
+Date: Tue, 2 Jul 2013 13:00:22 +0200
+Subject: [PATCH 25/29] ARM: kirkwood: remove redundant DT board files
+
+With DT support for mv643xx_eth board specific init for some boards now
+is unneccessary. Remove those board files, Kconfig entries, and
+corresponding entries in kirkwood_defconfig.
+
+Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
+---
+ arch/arm/mach-kirkwood/Kconfig | 148 --------------------------------
+ arch/arm/mach-kirkwood/Makefile | 22 +----
+ arch/arm/mach-kirkwood/board-dnskw.c | 7 --
+ arch/arm/mach-kirkwood/board-dt.c | 80 +----------------
+ arch/arm/mach-kirkwood/board-lsxl.c | 52 -----------
+ arch/arm/mach-kirkwood/board-readynas.c | 28 ------
+ 6 files changed, 2 insertions(+), 335 deletions(-)
+ delete mode 100644 arch/arm/mach-kirkwood/board-lsxl.c
+ delete mode 100644 arch/arm/mach-kirkwood/board-readynas.c
+
+diff --git a/arch/arm/mach-kirkwood/Kconfig b/arch/arm/mach-kirkwood/Kconfig
+index b56bd3d..dc99588 100644
+--- a/arch/arm/mach-kirkwood/Kconfig
++++ b/arch/arm/mach-kirkwood/Kconfig
+@@ -140,20 +140,6 @@ config ARCH_KIRKWOOD_DT
+ Say 'Y' here if you want your kernel to support the
+ Marvell Kirkwood using flattened device tree.
+
+-config MACH_CLOUDBOX_DT
+- bool "LaCie CloudBox NAS (Flattened Device Tree)"
+- select ARCH_KIRKWOOD_DT
+- help
+- Say 'Y' here if you want your kernel to support the LaCie
+- CloudBox NAS, using Flattened Device Tree.
+-
+-config MACH_DB88F628X_BP_DT
+- bool "Marvell DB-88F628x-BP Development Board (Flattened Device Tree)"
+- help
+- Say 'Y' here if you want your kernel to support the Marvell
+- DB-88F6281-BP and DB-88F6282-BP Development Board (Flattened
+- Device Tree).
+-
+ config MACH_DLINK_KIRKWOOD_DT
+ bool "D-Link Kirkwood-based NAS (Flattened Device Tree)"
+ select ARCH_KIRKWOOD_DT
+@@ -162,140 +148,6 @@ config MACH_DLINK_KIRKWOOD_DT
+ Kirkwood-based D-Link NASes such as DNS-320 & DNS-325,
+ using Flattened Device Tree.
+
+-config MACH_DOCKSTAR_DT
+- bool "Seagate FreeAgent Dockstar (Flattened Device Tree)"
+- select ARCH_KIRKWOOD_DT
+- help
+- Say 'Y' here if you want your kernel to support the
+- Seagate FreeAgent Dockstar (Flattened Device Tree).
+-
+-config MACH_DREAMPLUG_DT
+- bool "Marvell DreamPlug (Flattened Device Tree)"
+- select ARCH_KIRKWOOD_DT
+- help
+- Say 'Y' here if you want your kernel to support the
+- Marvell DreamPlug (Flattened Device Tree).
+-
+-config MACH_GOFLEXNET_DT
+- bool "Seagate GoFlex Net (Flattened Device Tree)"
+- select ARCH_KIRKWOOD_DT
+- help
+- Say 'Y' here if you want your kernel to support the
+- Seagate GoFlex Net (Flattened Device Tree).
+-
+-config MACH_GURUPLUG_DT
+- bool "Marvell GuruPlug Reference Board (Flattened Device Tree)"
+- select ARCH_KIRKWOOD_DT
+- help
+- Say 'Y' here if you want your kernel to support the
+- Marvell GuruPlug Reference Board (Flattened Device Tree).
+-
+-config MACH_IB62X0_DT
+- bool "RaidSonic IB-NAS6210, IB-NAS6220 (Flattened Device Tree)"
+- select ARCH_KIRKWOOD_DT
+- help
+- Say 'Y' here if you want your kernel to support the
+- RaidSonic IB-NAS6210 & IB-NAS6220 devices, using
+- Flattened Device Tree.
+-
+-config MACH_ICONNECT_DT
+- bool "Iomega Iconnect (Flattened Device Tree)"
+- select ARCH_KIRKWOOD_DT
+- help
+- Say 'Y' here to enable Iomega Iconnect support.
+-
+-config MACH_INETSPACE_V2_DT
+- bool "LaCie Internet Space v2 NAS (Flattened Device Tree)"
+- select ARCH_KIRKWOOD_DT
+- help
+- Say 'Y' here if you want your kernel to support the LaCie
+- Internet Space v2 NAS, using Flattened Device Tree.
+-
+-config MACH_IOMEGA_IX2_200_DT
+- bool "Iomega StorCenter ix2-200 (Flattened Device Tree)"
+- select ARCH_KIRKWOOD_DT
+- help
+- Say 'Y' here if you want your kernel to support the
+- Iomega StorCenter ix2-200 (Flattened Device Tree).
+-
+-config MACH_KM_KIRKWOOD_DT
+- bool "Keymile Kirkwood Reference Design (Flattened Device Tree)"
+- select ARCH_KIRKWOOD_DT
+- help
+- Say 'Y' here if you want your kernel to support the
+- Keymile Kirkwood Reference Desgin, using Flattened Device Tree.
+-
+-config MACH_LSXL_DT
+- bool "Buffalo Linkstation LS-XHL, LS-CHLv2 (Flattened Device Tree)"
+- select ARCH_KIRKWOOD_DT
+- help
+- Say 'Y' here if you want your kernel to support the
+- Buffalo Linkstation LS-XHL & LS-CHLv2 devices, using
+- Flattened Device Tree.
+-
+-config MACH_MPLCEC4_DT
+- bool "MPL CEC4 (Flattened Device Tree)"
+- select ARCH_KIRKWOOD_DT
+- help
+- Say 'Y' here if you want your kernel to support the
+- MPL CEC4 (Flattened Device Tree).
+-
+-config MACH_NETSPACE_LITE_V2_DT
+- bool "LaCie Network Space Lite v2 NAS (Flattened Device Tree)"
+- select ARCH_KIRKWOOD_DT
+- help
+- Say 'Y' here if you want your kernel to support the LaCie
+- Network Space Lite v2 NAS, using Flattened Device Tree.
+-
+-config MACH_NETSPACE_MAX_V2_DT
+- bool "LaCie Network Space Max v2 NAS (Flattened Device Tree)"
+- select ARCH_KIRKWOOD_DT
+- help
+- Say 'Y' here if you want your kernel to support the LaCie
+- Network Space Max v2 NAS, using Flattened Device Tree.
+-
+-config MACH_NETSPACE_MINI_V2_DT
+- bool "LaCie Network Space Mini v2 NAS (Flattened Device Tree)"
+- select ARCH_KIRKWOOD_DT
+- help
+- Say 'Y' here if you want your kernel to support the LaCie
+- Network Space Mini v2 NAS using Flattened Device Tree.
+-
+- This board is embedded in a product named CloudBox, which
+- provides automatic backup on a 100GB cloud storage. This
+- should not confused with a more recent LaCie NAS also named
+- CloudBox. For this last, the disk capacity is 1TB or above.
+-
+-config MACH_NETSPACE_V2_DT
+- bool "LaCie Network Space v2 NAS (Flattened Device Tree)"
+- select ARCH_KIRKWOOD_DT
+- help
+- Say 'Y' here if you want your kernel to support the LaCie
+- Network Space v2 NAS, using Flattened Device Tree.
+-
+-config MACH_OPENBLOCKS_A6_DT
+- bool "Plat'Home OpenBlocks A6 (Flattened Device Tree)"
+- select ARCH_KIRKWOOD_DT
+- help
+- Say 'Y' here if you want your kernel to support the
+- Plat'Home OpenBlocks A6 (Flattened Device Tree).
+-
+-config MACH_READYNAS_DT
+- bool "NETGEAR ReadyNAS Duo v2 (Flattened Device Tree)"
+- select ARCH_KIRKWOOD_DT
+- select ARM_APPENDED_DTB
+- select ARM_ATAG_DTB_COMPAT
+- help
+- Say 'Y' here if you want your kernel to support the
+- NETGEAR ReadyNAS Duo v2 using Fattened Device Tree.
+-
+-config MACH_TOPKICK_DT
+- bool "USI Topkick (Flattened Device Tree)"
+- select ARCH_KIRKWOOD_DT
+- help
+- Say 'Y' here if you want your kernel to support the
+- USI Topkick, using Flattened Device Tree
+-
+ config MACH_TS219_DT
+ bool "Device Tree for QNAP TS-11X, TS-21X NAS"
+ select ARCH_KIRKWOOD_DT
+diff --git a/arch/arm/mach-kirkwood/Makefile b/arch/arm/mach-kirkwood/Makefile
+index 2fdc3a7..062f8c7 100644
+--- a/arch/arm/mach-kirkwood/Makefile
++++ b/arch/arm/mach-kirkwood/Makefile
+@@ -19,25 +19,5 @@ obj-$(CONFIG_MACH_TS219) += ts219-setup.o tsx1x-common.o
+ obj-$(CONFIG_MACH_TS41X) += ts41x-setup.o tsx1x-common.o
+
+ obj-$(CONFIG_ARCH_KIRKWOOD_DT) += board-dt.o
+-obj-$(CONFIG_MACH_CLOUDBOX_DT) += board-ns2.o
+-obj-$(CONFIG_MACH_DB88F628X_BP_DT) += board-db88f628x-bp.o
+ obj-$(CONFIG_MACH_DLINK_KIRKWOOD_DT) += board-dnskw.o
+-obj-$(CONFIG_MACH_DOCKSTAR_DT) += board-dockstar.o
+-obj-$(CONFIG_MACH_DREAMPLUG_DT) += board-dreamplug.o
+-obj-$(CONFIG_MACH_GOFLEXNET_DT) += board-goflexnet.o
+-obj-$(CONFIG_MACH_GURUPLUG_DT) += board-guruplug.o
+-obj-$(CONFIG_MACH_IB62X0_DT) += board-ib62x0.o
+-obj-$(CONFIG_MACH_ICONNECT_DT) += board-iconnect.o
+-obj-$(CONFIG_MACH_INETSPACE_V2_DT) += board-ns2.o
+-obj-$(CONFIG_MACH_IOMEGA_IX2_200_DT) += board-iomega_ix2_200.o
+-obj-$(CONFIG_MACH_KM_KIRKWOOD_DT) += board-km_kirkwood.o
+-obj-$(CONFIG_MACH_LSXL_DT) += board-lsxl.o
+-obj-$(CONFIG_MACH_MPLCEC4_DT) += board-mplcec4.o
+-obj-$(CONFIG_MACH_NETSPACE_LITE_V2_DT) += board-ns2.o
+-obj-$(CONFIG_MACH_NETSPACE_MAX_V2_DT) += board-ns2.o
+-obj-$(CONFIG_MACH_NETSPACE_MINI_V2_DT) += board-ns2.o
+-obj-$(CONFIG_MACH_NETSPACE_V2_DT) += board-ns2.o
+-obj-$(CONFIG_MACH_OPENBLOCKS_A6_DT) += board-openblocks_a6.o
+-obj-$(CONFIG_MACH_READYNAS_DT) += board-readynas.o
+-obj-$(CONFIG_MACH_TOPKICK_DT) += board-usi_topkick.o
+-obj-$(CONFIG_MACH_TS219_DT) += board-ts219.o tsx1x-common.o
++obj-$(CONFIG_MACH_TS219_DT) += tsx1x-common.o
+diff --git a/arch/arm/mach-kirkwood/board-dnskw.c b/arch/arm/mach-kirkwood/board-dnskw.c
+index a1aa87f..2af7a95 100644
+--- a/arch/arm/mach-kirkwood/board-dnskw.c
++++ b/arch/arm/mach-kirkwood/board-dnskw.c
+@@ -14,14 +14,9 @@
+ #include <linux/kernel.h>
+ #include <linux/init.h>
+ #include <linux/platform_device.h>
+-#include <linux/mv643xx_eth.h>
+ #include <linux/gpio.h>
+ #include "common.h"
+
+-static struct mv643xx_eth_platform_data dnskw_ge00_data = {
+- .phy_addr = MV643XX_ETH_PHY_ADDR(8),
+-};
+-
+ /* Register any GPIO for output and set the value */
+ static void __init dnskw_gpio_register(unsigned gpio, char *name, int def)
+ {
+@@ -36,8 +31,6 @@ static void __init dnskw_gpio_register(unsigned gpio, char *name, int def)
+
+ void __init dnskw_init(void)
+ {
+- kirkwood_ge00_init(&dnskw_ge00_data);
+-
+ /* Set NAS to turn back on after a power failure */
+ dnskw_gpio_register(37, "dnskw:power:recover", 1);
+ }
+diff --git a/arch/arm/mach-kirkwood/board-dt.c b/arch/arm/mach-kirkwood/board-dt.c
+index f5aed1f..15e61c8 100644
+--- a/arch/arm/mach-kirkwood/board-dt.c
++++ b/arch/arm/mach-kirkwood/board-dt.c
+@@ -106,92 +106,14 @@ static void __init kirkwood_dt_init(void)
+ kexec_reinit = kirkwood_enable_pcie;
+ #endif
+
+- if (of_machine_is_compatible("globalscale,dreamplug"))
+- dreamplug_init();
+-
+- if (of_machine_is_compatible("globalscale,guruplug"))
+- guruplug_dt_init();
+-
+ if (of_machine_is_compatible("dlink,dns-kirkwood"))
+ dnskw_init();
+
+- if (of_machine_is_compatible("iom,iconnect"))
+- iconnect_init();
+-
+- if (of_machine_is_compatible("raidsonic,ib-nas62x0"))
+- ib62x0_init();
+-
+- if (of_machine_is_compatible("qnap,ts219"))
+- qnap_dt_ts219_init();
+-
+- if (of_machine_is_compatible("seagate,dockstar"))
+- dockstar_dt_init();
+-
+- if (of_machine_is_compatible("seagate,goflexnet"))
+- goflexnet_init();
+-
+- if (of_machine_is_compatible("buffalo,lsxl"))
+- lsxl_init();
+-
+- if (of_machine_is_compatible("iom,ix2-200"))
+- iomega_ix2_200_init();
+-
+- if (of_machine_is_compatible("keymile,km_kirkwood"))
+- km_kirkwood_init();
+-
+- if (of_machine_is_compatible("lacie,cloudbox") ||
+- of_machine_is_compatible("lacie,inetspace_v2") ||
+- of_machine_is_compatible("lacie,netspace_lite_v2") ||
+- of_machine_is_compatible("lacie,netspace_max_v2") ||
+- of_machine_is_compatible("lacie,netspace_mini_v2") ||
+- of_machine_is_compatible("lacie,netspace_v2"))
+- ns2_init();
+-
+- if (of_machine_is_compatible("marvell,db-88f6281-bp") ||
+- of_machine_is_compatible("marvell,db-88f6282-bp"))
+- db88f628x_init();
+-
+- if (of_machine_is_compatible("mpl,cec4"))
+- mplcec4_init();
+-
+- if (of_machine_is_compatible("netgear,readynas-duo-v2"))
+- netgear_readynas_init();
+-
+- if (of_machine_is_compatible("plathome,openblocks-a6"))
+- openblocks_a6_init();
+-
+- if (of_machine_is_compatible("usi,topkick"))
+- usi_topkick_init();
+-
+ of_platform_populate(NULL, kirkwood_dt_match_table, NULL, NULL);
+ }
+
+ static const char * const kirkwood_dt_board_compat[] = {
+- "globalscale,dreamplug",
+- "globalscale,guruplug",
+- "dlink,dns-320",
+- "dlink,dns-325",
+- "iom,iconnect",
+- "raidsonic,ib-nas62x0",
+- "qnap,ts219",
+- "seagate,dockstar",
+- "seagate,goflexnet",
+- "buffalo,lsxl",
+- "iom,ix2-200",
+- "keymile,km_kirkwood",
+- "lacie,cloudbox",
+- "lacie,inetspace_v2",
+- "lacie,netspace_lite_v2",
+- "lacie,netspace_max_v2",
+- "lacie,netspace_mini_v2",
+- "lacie,netspace_v2",
+- "marvell,db-88f6281-bp",
+- "marvell,db-88f6282-bp",
+- "mpl,cec4",
+- "netgear,readynas-duo-v2",
+- "plathome,openblocks-a6",
+- "usi,topkick",
+- "zyxel,nsa310",
++ "marvell,kirkwood",
+ NULL
+ };
+
+diff --git a/arch/arm/mach-kirkwood/board-lsxl.c b/arch/arm/mach-kirkwood/board-lsxl.c
+deleted file mode 100644
+index 4ec8b7a..0000000
+--- a/arch/arm/mach-kirkwood/board-lsxl.c
++++ /dev/null
+@@ -1,52 +0,0 @@
+-/*
+- * Copyright 2012 (C), Michael Walle <michael@walle.cc>
+- *
+- * arch/arm/mach-kirkwood/board-lsxl.c
+- *
+- * Buffalo Linkstation LS-XHL and LS-CHLv2 init for drivers not
+- * converted to flattened device tree yet.
+- *
+- * This file is licensed under the terms of the GNU General Public
+- * License version 2. This program is licensed "as is" without any
+- * warranty of any kind, whether express or implied.
+- */
+-
+-#include <linux/kernel.h>
+-#include <linux/init.h>
+-#include <linux/platform_device.h>
+-#include <linux/mv643xx_eth.h>
+-#include "common.h"
+-
+-static struct mv643xx_eth_platform_data lsxl_ge00_data = {
+- .phy_addr = MV643XX_ETH_PHY_ADDR(0),
+-};
+-
+-static struct mv643xx_eth_platform_data lsxl_ge01_data = {
+- .phy_addr = MV643XX_ETH_PHY_ADDR(8),
+-};
+-
+-/*
+- * On the LS-XHL/LS-CHLv2, the shutdown process is following:
+- * - Userland monitors key events until the power switch goes to off position
+- * - The board reboots
+- * - U-boot starts and goes into an idle mode waiting for the user
+- * to move the switch to ON position
+- *
+- */
+-static void lsxl_power_off(void)
+-{
+- kirkwood_restart('h', NULL);
+-}
+-
+-void __init lsxl_init(void)
+-{
+- /*
+- * Basic setup. Needs to be called early.
+- */
+-
+- kirkwood_ge00_init(&lsxl_ge00_data);
+- kirkwood_ge01_init(&lsxl_ge01_data);
+-
+- /* register power-off method */
+- pm_power_off = lsxl_power_off;
+-}
+diff --git a/arch/arm/mach-kirkwood/board-readynas.c b/arch/arm/mach-kirkwood/board-readynas.c
+deleted file mode 100644
+index fb42c20..0000000
+--- a/arch/arm/mach-kirkwood/board-readynas.c
++++ /dev/null
+@@ -1,28 +0,0 @@
+-/*
+- * NETGEAR ReadyNAS Duo v2 Board setup for drivers not already
+- * converted to DT.
+- *
+- * Copyright (C) 2013, Arnaud EBALARD <arno@natisbad.org>
+- *
+- * This program is free software; you can redistribute it and/or
+- * modify it under the terms of the GNU General Public License
+- * as published by the Free Software Foundation; either version
+- * 2 of the License, or (at your option) any later version.
+- */
+-
+-#include <linux/kernel.h>
+-#include <linux/init.h>
+-#include <linux/platform_device.h>
+-#include <linux/mv643xx_eth.h>
+-#include <mach/kirkwood.h>
+-#include "common.h"
+-
+-static struct mv643xx_eth_platform_data netgear_readynas_ge00_data = {
+- .phy_addr = MV643XX_ETH_PHY_ADDR(0),
+-};
+-
+-void __init netgear_readynas_init(void)
+-{
+- kirkwood_ge00_init(&netgear_readynas_ge00_data);
+- kirkwood_pcie_init(KW_PCIE0);
+-}
+--
+1.8.4.rc1
+
--- /dev/null
+From dcfe8d8652de29fae2e247137d0e776fdda60b14 Mon Sep 17 00:00:00 2001
+From: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
+Date: Tue, 2 Jul 2013 13:00:23 +0200
+Subject: [PATCH 26/29] ARM: kirkwood: remove legacy clk alias for mv643xx_eth
+
+With all boards converted to DT enabled mv643xx_eth we can now
+remove the clock alias for gbe clocks.
+
+Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
+---
+ arch/arm/mach-kirkwood/board-dt.c | 2 --
+ 1 file changed, 2 deletions(-)
+
+diff --git a/arch/arm/mach-kirkwood/board-dt.c b/arch/arm/mach-kirkwood/board-dt.c
+index 15e61c8..a6ff0a8 100644
+--- a/arch/arm/mach-kirkwood/board-dt.c
++++ b/arch/arm/mach-kirkwood/board-dt.c
+@@ -66,12 +66,10 @@ static void __init kirkwood_legacy_clk_init(void)
+ */
+ clkspec.args[0] = CGC_BIT_GE0;
+ clk = of_clk_get_from_provider(&clkspec);
+- orion_clkdev_add(NULL, "mv643xx_eth_port.0", clk);
+ clk_prepare_enable(clk);
+
+ clkspec.args[0] = CGC_BIT_GE1;
+ clk = of_clk_get_from_provider(&clkspec);
+- orion_clkdev_add(NULL, "mv643xx_eth_port.1", clk);
+ clk_prepare_enable(clk);
+ }
+
+--
+1.8.4.rc1
+
--- /dev/null
+From eac92acae29cfab34785d61cbb3218e88e487b77 Mon Sep 17 00:00:00 2001
+From: Jonas Gorski <jogo@openwrt.org>
+Date: Mon, 8 Jul 2013 00:35:12 +0200
+Subject: [PATCH 27/29] net: mv643xx_eth: do not use port number as platform
+ device id
+
+The port number is only local to the ethernet block, not global, so
+there can be two ethernet blocks both using the same port, like
+kirkwood with both using port 0.
+
+Fix this by using the array index offset for the allocated platform
+devices as the id.
+
+Signed-off-by: Jonas Gorski <jogo@openwrt.org>
+---
+ drivers/net/ethernet/marvell/mv643xx_eth.c | 13 +++++++++++--
+ 1 file changed, 11 insertions(+), 2 deletions(-)
+
+diff --git a/drivers/net/ethernet/marvell/mv643xx_eth.c b/drivers/net/ethernet/marvell/mv643xx_eth.c
+index 004a250..e57d292 100644
+--- a/drivers/net/ethernet/marvell/mv643xx_eth.c
++++ b/drivers/net/ethernet/marvell/mv643xx_eth.c
+@@ -2483,6 +2483,7 @@ static int mv643xx_eth_shared_of_add_port(struct platform_device *pdev,
+ struct resource res;
+ const char *mac_addr;
+ int ret;
++ int dev_num = 0;
+
+ memset(&ppd, 0, sizeof(ppd));
+ ppd.shared = pdev;
+@@ -2503,6 +2504,14 @@ static int mv643xx_eth_shared_of_add_port(struct platform_device *pdev,
+ return -EINVAL;
+ }
+
++ while (dev_num < 3 && port_platdev[dev_num])
++ dev_num++;
++
++ if (dev_num == 3) {
++ dev_err(&pdev->dev, "too many ports registered\n");
++ return -EINVAL;
++ }
++
+ mac_addr = of_get_mac_address(pnp);
+ if (mac_addr)
+ memcpy(ppd.mac_addr, mac_addr, 6);
+@@ -2521,7 +2530,7 @@ static int mv643xx_eth_shared_of_add_port(struct platform_device *pdev,
+ of_property_read_u32(pnp, "duplex", &ppd.duplex);
+ }
+
+- ppdev = platform_device_alloc(MV643XX_ETH_NAME, ppd.port_number);
++ ppdev = platform_device_alloc(MV643XX_ETH_NAME, dev_num);
+ if (!ppdev)
+ return -ENOMEM;
+ ppdev->dev.coherent_dma_mask = DMA_BIT_MASK(32);
+@@ -2538,7 +2547,7 @@ static int mv643xx_eth_shared_of_add_port(struct platform_device *pdev,
+ if (ret)
+ goto port_err;
+
+- port_platdev[ppd.port_number] = ppdev;
++ port_platdev[dev_num] = ppdev;
+
+ return 0;
+
+--
+1.8.4.rc1
+
--- /dev/null
+From f7d3f7790b75b098e1c92530dc3d28ba3b40b5a4 Mon Sep 17 00:00:00 2001
+From: Jonas Gorski <jogo@openwrt.org>
+Date: Sat, 10 Aug 2013 12:48:51 +0200
+Subject: [PATCH 28/29] of: add support for parsing mac addresses from mtd
+
+Signed-off-by: Jonas Gorski <jogo@openwrt.org>
+---
+ drivers/of/of_net.c | 100 +++++++++++++++++++++++++++++++++++++++++++++++++++-
+ 1 file changed, 99 insertions(+), 1 deletion(-)
+
+diff --git a/drivers/of/of_net.c b/drivers/of/of_net.c
+index ffab033..8b40ac6 100644
+--- a/drivers/of/of_net.c
++++ b/drivers/of/of_net.c
+@@ -10,6 +10,7 @@
+ #include <linux/of_net.h>
+ #include <linux/phy.h>
+ #include <linux/export.h>
++#include <linux/mtd/mtd.h>
+
+ /**
+ * It maps 'enum phy_interface_t' found in include/linux/phy.h
+@@ -55,6 +56,103 @@ const int of_get_phy_mode(struct device_node *np)
+ }
+ EXPORT_SYMBOL_GPL(of_get_phy_mode);
+
++static const void *of_get_mac_address_mtd(struct device_node *np)
++{
++ const __be32 *list;
++ int size, ret;
++ size_t ret_len;
++ phandle phandle;
++ struct device_node *part_node;
++ struct mtd_info *mtd;
++ const char *part;
++ u8 mac[ETH_ALEN];
++ u64 offset;
++ bool parse_mac = false;
++
++ if (!IS_ENABLED(CONFIG_MTD))
++ return NULL;
++
++ list = of_get_property(np, "mtd-mac-address", &size);
++
++ if (!list) {
++ list = of_get_property(np, "mtd-mac-address-string", &size);
++ parse_mac = true;
++ }
++
++ if (!list)
++ return NULL;
++
++ if (size != sizeof(*list) * 2)
++ return NULL;
++
++ phandle = be32_to_cpup(list++);
++ if (!phandle)
++ return NULL;
++
++ part_node = of_find_node_by_phandle(phandle);
++ if (!part_node)
++ return NULL;
++
++ offset = be32_to_cpup(list++);
++
++ part = of_get_property(part_node, "label", NULL);
++ if (!part)
++ part = part_node->name;
++
++ mtd = get_mtd_device_nm(part);
++
++ of_node_put(part_node);
++
++ if (IS_ERR(mtd))
++ return NULL;
++
++ if (parse_mac) {
++ u8 mac_str[18];
++
++ ret = mtd_read(mtd, offset, 18, &ret_len, (u_char *)&mac_str);
++ if (!ret && ret_len != 18)
++ ret = -EIO;
++
++ if (!ret)
++ ret_len = sscanf(mac_str, "%02hhx:%02hhx:%02hhx:%02hhx:%02hhx:%02hhx",
++ mac, mac + 1, mac + 2, mac + 3,
++ mac + 4, mac + 5);
++
++ } else {
++ ret = mtd_read(mtd, offset, ETH_ALEN, &ret_len, (u_char *)&mac);
++ }
++
++ put_mtd_device(mtd);
++
++ if (!ret && ret_len == ETH_ALEN && is_valid_ether_addr(mac)) {
++ struct property *pp = kzalloc(sizeof(*pp), GFP_KERNEL);
++
++ if (!pp)
++ return NULL;
++
++ pp->name = kstrdup("mac-address", GFP_KERNEL);
++ pp->value = kzalloc(ETH_ALEN, GFP_KERNEL);
++
++ if (!pp->name || !pp->value) {
++ kfree(pp->name);
++ kfree(pp);
++ return NULL;
++ }
++
++ memcpy(pp->value, mac, ETH_ALEN);
++ pp->length = ETH_ALEN;
++
++ if (of_find_property(np, "mac-address", NULL))
++ of_update_property(np, pp);
++ else
++ of_add_property(np, pp);
++
++ return pp->value;
++ }
++
++ return NULL;
++}
++
+ /**
+ * Search the device tree for the best MAC address to use. 'mac-address' is
+ * checked first, because that is supposed to contain to "most recent" MAC
+@@ -89,6 +187,6 @@ const void *of_get_mac_address(struct device_node *np)
+ if (pp && (pp->length == 6) && is_valid_ether_addr(pp->value))
+ return pp->value;
+
+- return NULL;
++ return of_get_mac_address_mtd(np);
+ }
+ EXPORT_SYMBOL(of_get_mac_address);
+--
+1.8.4.rc1
+
projects / openwrt / staging / dangole.git / commitdiff