drm/amdgpu: abstract system domain enablement for gfxhub/mmhub

Signed-off-by: Huang Rui <ray.huang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Acked-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c b/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c
index 1e65b5edd38fb39f64a8354acd2325d269c97b89..2bd9185cc55d706ebb242025a44d884a0186e804 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c
@@ -165,14 +165,27 @@ static void gfxhub_v1_0_init_cache_regs(struct amdgpu_device *adev)
        WREG32(SOC15_REG_OFFSET(GC, 0, mmVM_L2_CNTL4), tmp);
 }
 
+static void gfxhub_v1_0_enable_system_domain(struct amdgpu_device *adev)
+{
+       uint32_t tmp;
+
+       tmp = RREG32(SOC15_REG_OFFSET(GC, 0, mmVM_CONTEXT0_CNTL));
+       tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, ENABLE_CONTEXT, 1);
+       tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, PAGE_TABLE_DEPTH, 0);
+       WREG32(SOC15_REG_OFFSET(GC, 0, mmVM_CONTEXT0_CNTL), tmp);
+}
+
 int gfxhub_v1_0_gart_enable(struct amdgpu_device *adev)
 {
        u32 tmp;
        u32 i;
 
        if (amdgpu_sriov_vf(adev)) {
-               /* MC_VM_FB_LOCATION_BASE/TOP is NULL for VF, becuase they are VF copy registers so
-               vbios post doesn't program them, for SRIOV driver need to program them */
+               /*
+                * MC_VM_FB_LOCATION_BASE/TOP is NULL for VF, becuase they are
+                * VF copy registers so vbios post doesn't program them, for
+                * SRIOV driver need to program them
+                */
                WREG32(SOC15_REG_OFFSET(GC, 0, mmMC_VM_FB_LOCATION_BASE),
                                adev->mc.vram_start >> 24);
                WREG32(SOC15_REG_OFFSET(GC, 0, mmMC_VM_FB_LOCATION_TOP),
@@ -185,10 +198,7 @@ int gfxhub_v1_0_gart_enable(struct amdgpu_device *adev)
        gfxhub_v1_0_init_tlb_regs(adev);
        gfxhub_v1_0_init_cache_regs(adev);
 
-       tmp = RREG32(SOC15_REG_OFFSET(GC, 0, mmVM_CONTEXT0_CNTL));
-       tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, ENABLE_CONTEXT, 1);
-       tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, PAGE_TABLE_DEPTH, 0);
-       WREG32(SOC15_REG_OFFSET(GC, 0, mmVM_CONTEXT0_CNTL), tmp);
+       gfxhub_v1_0_enable_system_domain(adev);
 
        /* Disable identity aperture.*/
        WREG32(SOC15_REG_OFFSET(GC, 0,

diff --git a/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c b/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c
index 0cb651b20c49e51d0297e301a8426ab02e08f62b..261416165fdf0a5353524899de1c6ff1e0066a7f 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c
@@ -176,15 +176,27 @@ static void mmhub_v1_0_init_cache_regs(struct amdgpu_device *adev)
        WREG32(SOC15_REG_OFFSET(MMHUB, 0, mmVM_L2_CNTL4), tmp);
 }
 
+static void mmhub_v1_0_enable_system_domain(struct amdgpu_device *adev)
+{
+       uint32_t tmp;
+
+       tmp = RREG32(SOC15_REG_OFFSET(MMHUB, 0, mmVM_CONTEXT0_CNTL));
+       tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, ENABLE_CONTEXT, 1);
+       tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, PAGE_TABLE_DEPTH, 0);
+       WREG32(SOC15_REG_OFFSET(MMHUB, 0, mmVM_CONTEXT0_CNTL), tmp);
+}
+
 int mmhub_v1_0_gart_enable(struct amdgpu_device *adev)
 {
        u32 tmp;
-       uint64_t addr;
        u32 i;
 
        if (amdgpu_sriov_vf(adev)) {
-               /* MC_VM_FB_LOCATION_BASE/TOP is NULL for VF, becuase they are VF copy registers so
-               vbios post doesn't program them, for SRIOV driver need to program them */
+               /*
+                * MC_VM_FB_LOCATION_BASE/TOP is NULL for VF, becuase they are
+                * VF copy registers so vbios post doesn't program them, for
+                * SRIOV driver need to program them
+                */
                WREG32(SOC15_REG_OFFSET(MMHUB, 0, mmMC_VM_FB_LOCATION_BASE),
                        adev->mc.vram_start >> 24);
                WREG32(SOC15_REG_OFFSET(MMHUB, 0, mmMC_VM_FB_LOCATION_TOP),
@@ -197,14 +209,7 @@ int mmhub_v1_0_gart_enable(struct amdgpu_device *adev)
        mmhub_v1_0_init_tlb_regs(adev);
        mmhub_v1_0_init_cache_regs(adev);
 
-       addr = SOC15_REG_OFFSET(MMHUB, 0, mmVM_CONTEXT0_CNTL);
-       tmp = RREG32(addr);
-
-       tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, ENABLE_CONTEXT, 1);
-       tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, PAGE_TABLE_DEPTH, 0);
-       WREG32(SOC15_REG_OFFSET(MMHUB, 0, mmVM_CONTEXT0_CNTL), tmp);
-
-       tmp = RREG32(addr);
+       mmhub_v1_0_enable_system_domain(adev);
 
        /* Disable identity aperture.*/
        WREG32(SOC15_REG_OFFSET(MMHUB, 0,