Tegra: drivers: memctrl: move chip specific defines to tegra_def.h

This patch moves the chip specific memory controller driver defines to
the appropriate tegra_def.h files, for future compatibility.

Change-Id: I3179fb771d8b32e913ca29bd94af95f4b2fc1961
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

diff --git a/plat/nvidia/tegra/common/drivers/memctrl/memctrl_v1.c b/plat/nvidia/tegra/common/drivers/memctrl/memctrl_v1.c
index c4170504c43801bbd2985fa053ff2fa9e267d9f2..859ecd53edbd7e5f506e48a402a55a74bd1cdc21 100644 (file)
--- a/plat/nvidia/tegra/common/drivers/memctrl/memctrl_v1.c
+++ b/plat/nvidia/tegra/common/drivers/memctrl/memctrl_v1.c
@@ -43,7 +43,7 @@
 #define  GPU_RESET_BIT                 (1 << 24)
 
 /* Video Memory base and size (live values) */
-static uintptr_t video_mem_base;
+static uint64_t video_mem_base;
 static uint64_t video_mem_size;
 
 /*
@@ -85,7 +85,9 @@ void tegra_memctrl_setup(void)
        (void)tegra_mc_read_32(MC_SMMU_CONFIG_0); /* read to flush writes */
 
        /* video memory carveout */
-       tegra_mc_write_32(MC_VIDEO_PROTECT_BASE, video_mem_base);
+       tegra_mc_write_32(MC_VIDEO_PROTECT_BASE_HI,
+                         (uint32_t)(video_mem_base >> 32));
+       tegra_mc_write_32(MC_VIDEO_PROTECT_BASE_LO, (uint32_t)video_mem_base);
        tegra_mc_write_32(MC_VIDEO_PROTECT_SIZE_MB, video_mem_size);
 }
 
@@ -208,7 +210,8 @@ void tegra_memctrl_videomem_setup(uint64_t phys_base, uint32_t size_in_bytes)
        enable_mmu_el3(0);
 
 done:
-       tegra_mc_write_32(MC_VIDEO_PROTECT_BASE, phys_base);
+       tegra_mc_write_32(MC_VIDEO_PROTECT_BASE_HI, (uint32_t)(phys_base >> 32));
+       tegra_mc_write_32(MC_VIDEO_PROTECT_BASE_LO, (uint32_t)phys_base);
        tegra_mc_write_32(MC_VIDEO_PROTECT_SIZE_MB, size_in_bytes >> 20);
 
        /* store new values */

diff --git a/plat/nvidia/tegra/include/drivers/memctrl_v1.h b/plat/nvidia/tegra/include/drivers/memctrl_v1.h
index e44a9ea9240e826aa4242d777d2148d005a5ed12..b504594bf05069077b4c2908f85dd33fa2f9249c 100644 (file)
--- a/plat/nvidia/tegra/include/drivers/memctrl_v1.h
+++ b/plat/nvidia/tegra/include/drivers/memctrl_v1.h
@@ -60,14 +60,6 @@
 #define MC_SMMU_TRANSLATION_ENABLE_4_0         0xb98
 #define  MC_SMMU_TRANSLATION_ENABLE            (~0)
 
-/* TZDRAM carveout configuration registers */
-#define MC_SECURITY_CFG0_0                     0x70
-#define MC_SECURITY_CFG1_0                     0x74
-
-/* Video Memory carveout configuration registers */
-#define MC_VIDEO_PROTECT_BASE                  0x648
-#define MC_VIDEO_PROTECT_SIZE_MB               0x64c
-
 static inline uint32_t tegra_mc_read_32(uint32_t off)
 {
        return mmio_read_32(TEGRA_MC_BASE + off);

diff --git a/plat/nvidia/tegra/include/drivers/memctrl_v2.h b/plat/nvidia/tegra/include/drivers/memctrl_v2.h
index e1abe14346eff3ded3bfcd1150d4119fc9adbeac..8b12dcd035c65154ba47882ef0b8588a8a3ba299 100644 (file)
--- a/plat/nvidia/tegra/include/drivers/memctrl_v2.h
+++ b/plat/nvidia/tegra/include/drivers/memctrl_v2.h
@@ -352,51 +352,6 @@ typedef struct mc_streamid_security_cfg {
 
 #endif /* __ASSEMBLY__ */
 
-/*******************************************************************************
- * TZDRAM carveout configuration registers
- ******************************************************************************/
-#define MC_SECURITY_CFG0_0                             0x70
-#define MC_SECURITY_CFG1_0                             0x74
-#define MC_SECURITY_CFG3_0                             0x9BC
-
-/*******************************************************************************
- * Video Memory carveout configuration registers
- ******************************************************************************/
-#define MC_VIDEO_PROTECT_BASE_HI                       0x978
-#define MC_VIDEO_PROTECT_BASE_LO                       0x648
-#define MC_VIDEO_PROTECT_SIZE_MB                       0x64c
-
-/*******************************************************************************
- * TZRAM carveout (MC_SECURITY_CARVEOUT11) configuration registers
- ******************************************************************************/
-#define MC_TZRAM_BASE_LO                               0x2194
-#define  TZRAM_BASE_LO_SHIFT                           12
-#define  TZRAM_BASE_LO_MASK                            0xFFFFF
-#define MC_TZRAM_BASE_HI                               0x2198
-#define  TZRAM_BASE_HI_SHIFT                           0
-#define  TZRAM_BASE_HI_MASK                            3
-#define MC_TZRAM_SIZE                                  0x219C
-#define  TZRAM_SIZE_RANGE_4KB_SHIFT                    27
-
-#define MC_TZRAM_CARVEOUT_CFG                          0x2190
-#define  TZRAM_LOCK_CFG_SETTINGS_BIT                   (1 << 1)
-#define  TZRAM_ENABLE_TZ_LOCK_BIT                      (1 << 0)
-#define MC_TZRAM_CARVEOUT_CLIENT_ACCESS_CFG0           0x21A0
-#define MC_TZRAM_CARVEOUT_CLIENT_ACCESS_CFG1           0x21A4
-#define  TZRAM_CARVEOUT_CPU_WRITE_ACCESS_BIT           (1 << 25)
-#define  TZRAM_CARVEOUT_CPU_READ_ACCESS_BIT            (1 << 7)
-#define MC_TZRAM_CARVEOUT_CLIENT_ACCESS_CFG2           0x21A8
-#define MC_TZRAM_CARVEOUT_CLIENT_ACCESS_CFG3           0x21AC
-#define MC_TZRAM_CARVEOUT_CLIENT_ACCESS_CFG4           0x21B0
-#define MC_TZRAM_CARVEOUT_CLIENT_ACCESS_CFG5           0x21B4
-
-#define MC_TZRAM_CARVEOUT_FORCE_INTERNAL_ACCESS0       0x21B8
-#define MC_TZRAM_CARVEOUT_FORCE_INTERNAL_ACCESS1       0x21BC
-#define MC_TZRAM_CARVEOUT_FORCE_INTERNAL_ACCESS2       0x21C0
-#define MC_TZRAM_CARVEOUT_FORCE_INTERNAL_ACCESS3       0x21C4
-#define MC_TZRAM_CARVEOUT_FORCE_INTERNAL_ACCESS4       0x21C8
-#define MC_TZRAM_CARVEOUT_FORCE_INTERNAL_ACCESS5       0x21CC
-
 /*******************************************************************************
  * Memory Controller Reset Control registers
  ******************************************************************************/

diff --git a/plat/nvidia/tegra/include/t132/tegra_def.h b/plat/nvidia/tegra/include/t132/tegra_def.h
index 314b700715e740bf6af83048b3b9c04d105d5ae1..4ba4f12c5e76e71f479bfaa847d6697d52665abd 100644 (file)
--- a/plat/nvidia/tegra/include/t132/tegra_def.h
+++ b/plat/nvidia/tegra/include/t132/tegra_def.h
@@ -104,6 +104,16 @@
  ******************************************************************************/
 #define TEGRA_MC_BASE                  0x70019000
 
+/* TZDRAM carveout configuration registers */
+#define MC_SECURITY_CFG0_0             0x70
+#define MC_SECURITY_CFG1_0             0x74
+#define MC_SECURITY_CFG3_0             0x9BC
+
+/* Video Memory carveout configuration registers */
+#define MC_VIDEO_PROTECT_BASE_HI       0x978
+#define MC_VIDEO_PROTECT_BASE_LO       0x648
+#define MC_VIDEO_PROTECT_SIZE_MB       0x64c
+
 /*******************************************************************************
  * Tegra TZRAM constants
  ******************************************************************************/

diff --git a/plat/nvidia/tegra/include/t186/tegra_def.h b/plat/nvidia/tegra/include/t186/tegra_def.h
index b5a8ab38d327cf95307f2b84ea2e80ccaccd69fe..01da884f7b85913d963d78cec6a85c16f6b9f9ff 100644 (file)
--- a/plat/nvidia/tegra/include/t186/tegra_def.h
+++ b/plat/nvidia/tegra/include/t186/tegra_def.h
@@ -120,6 +120,45 @@
 #define TEGRA_MC_STREAMID_BASE         0x02C00000
 #define TEGRA_MC_BASE                  0x02C10000
 
+/* TZDRAM carveout configuration registers */
+#define MC_SECURITY_CFG0_0             0x70
+#define MC_SECURITY_CFG1_0             0x74
+#define MC_SECURITY_CFG3_0             0x9BC
+
+/* Video Memory carveout configuration registers */
+#define MC_VIDEO_PROTECT_BASE_HI       0x978
+#define MC_VIDEO_PROTECT_BASE_LO       0x648
+#define MC_VIDEO_PROTECT_SIZE_MB       0x64c
+
+/* TZRAM carveout (MC_SECURITY_CARVEOUT11) configuration registers */
+#define MC_TZRAM_BASE_LO               0x2194
+#define  TZRAM_BASE_LO_SHIFT           12
+#define  TZRAM_BASE_LO_MASK            0xFFFFF
+#define MC_TZRAM_BASE_HI               0x2198
+#define  TZRAM_BASE_HI_SHIFT           0
+#define  TZRAM_BASE_HI_MASK            3
+#define MC_TZRAM_SIZE                  0x219C
+#define  TZRAM_SIZE_RANGE_4KB_SHIFT    27
+
+#define MC_TZRAM_CARVEOUT_CFG                  0x2190
+#define  TZRAM_LOCK_CFG_SETTINGS_BIT           (1 << 1)
+#define  TZRAM_ENABLE_TZ_LOCK_BIT              (1 << 0)
+#define MC_TZRAM_CARVEOUT_CLIENT_ACCESS_CFG0   0x21A0
+#define MC_TZRAM_CARVEOUT_CLIENT_ACCESS_CFG1   0x21A4
+#define  TZRAM_CARVEOUT_CPU_WRITE_ACCESS_BIT   (1 << 25)
+#define  TZRAM_CARVEOUT_CPU_READ_ACCESS_BIT    (1 << 7)
+#define MC_TZRAM_CARVEOUT_CLIENT_ACCESS_CFG2   0x21A8
+#define MC_TZRAM_CARVEOUT_CLIENT_ACCESS_CFG3   0x21AC
+#define MC_TZRAM_CARVEOUT_CLIENT_ACCESS_CFG4   0x21B0
+#define MC_TZRAM_CARVEOUT_CLIENT_ACCESS_CFG5   0x21B4
+
+#define MC_TZRAM_CARVEOUT_FORCE_INTERNAL_ACCESS0       0x21B8
+#define MC_TZRAM_CARVEOUT_FORCE_INTERNAL_ACCESS1       0x21BC
+#define MC_TZRAM_CARVEOUT_FORCE_INTERNAL_ACCESS2       0x21C0
+#define MC_TZRAM_CARVEOUT_FORCE_INTERNAL_ACCESS3       0x21C4
+#define MC_TZRAM_CARVEOUT_FORCE_INTERNAL_ACCESS4       0x21C8
+#define MC_TZRAM_CARVEOUT_FORCE_INTERNAL_ACCESS5       0x21CC
+
 /*******************************************************************************
  * Tegra UART Controller constants
  ******************************************************************************/

diff --git a/plat/nvidia/tegra/include/t210/tegra_def.h b/plat/nvidia/tegra/include/t210/tegra_def.h
index d24377da343e870605aef2bf082732a3e0d371f3..0961355143a13c915812305f24b5486cc02de081 100644 (file)
--- a/plat/nvidia/tegra/include/t210/tegra_def.h
+++ b/plat/nvidia/tegra/include/t210/tegra_def.h
@@ -129,6 +129,16 @@
  ******************************************************************************/
 #define TEGRA_MC_BASE                  0x70019000
 
+/* TZDRAM carveout configuration registers */
+#define MC_SECURITY_CFG0_0             0x70
+#define MC_SECURITY_CFG1_0             0x74
+#define MC_SECURITY_CFG3_0             0x9BC
+
+/* Video Memory carveout configuration registers */
+#define MC_VIDEO_PROTECT_BASE_HI       0x978
+#define MC_VIDEO_PROTECT_BASE_LO       0x648
+#define MC_VIDEO_PROTECT_SIZE_MB       0x64c
+
 /*******************************************************************************
  * Tegra TZRAM constants
  ******************************************************************************/