--- a/arch/mips/ralink/early_printk.c
+++ b/arch/mips/ralink/early_printk.c
-@@ -12,21 +12,24 @@
+@@ -12,21 +12,26 @@
#include <asm/addrspace.h>
#ifdef CONFIG_SOC_RT288X
+#define MT7628_CHIP_NAME1 0x20203832
+
+#define UART_REG_TX 0x04
++#define UART_REG_LCR 0x0c
+#define UART_REG_LSR 0x14
+#define UART_REG_LSR_RT2880 0x1c
static __iomem void *uart_membase = (__iomem void *) KSEG1ADDR(EARLY_UART_BASE);
+static __iomem void *chipid_membase = (__iomem void *) KSEG1ADDR(CHIPID_BASE);
++static int init_complete;
static inline void uart_w32(u32 val, unsigned reg)
{
-@@ -38,11 +41,23 @@ static inline u32 uart_r32(unsigned reg)
+@@ -38,11 +43,46 @@
return __raw_readl(uart_membase + reg);
}
+ return IS_ENABLED(CONFIG_SOC_MT7620) &&
+ (__raw_readl(chipid_membase) == MT7628_CHIP_NAME1);
+}
++
++static inline void find_uart_base(void)
++{
++ int i;
++
++ if (!soc_is_mt7628())
++ return;
++
++ for (i = 0; i < 3; i++) {
++ u32 reg = uart_r32(UART_REG_LCR + (0x100 * i));
++
++ if (!reg)
++ continue;
++
++ uart_membase = (__iomem void *) KSEG1ADDR(EARLY_UART_BASE + (0x100 * i));
++ break;
++ }
++}
+
void prom_putchar(unsigned char ch)
{
- uart_w32(ch, UART_REG_TX);
- while ((uart_r32(UART_REG_LSR) & UART_LSR_THRE) == 0)
- ;
++ if (!init_complete) {
++ find_uart_base();
++ init_complete = 1;
++ }
++
+ if (IS_ENABLED(CONFIG_SOC_MT7621) || soc_is_mt7628()) {
+ uart_w32(ch, UART_TX);
+ while ((uart_r32(UART_REG_LSR) & UART_LSR_THRE) == 0)