#define IFXMIPS_RCU_RST_REQ_DFE (1 << 7)
#define IFXMIPS_RCU_RST_REQ_AFE (1 << 11)
-
+#define IFXMIPS_RCU_RST_REQ_ARC_JTAG (1 << 20)
/*------------ MCD */
#define ETHERNET_PACKET_DMA_BUFFER_SIZE 0x600
-#define IFXMIPS_PPE32_MEM_MAP (IFXMIPS_PPE32_BASE_ADDR + 0x10000 )
+#define IFXMIPS_PPE32_MEM_MAP ((u32*)(IFXMIPS_PPE32_BASE_ADDR + 0x10000))
+#define IFXMIPS_PPE32_SRST ((u32*)(IFXMIPS_PPE32_BASE_ADDR + 0x10080))
#define MII_MODE 1
-
#define REV_MII_MODE 2
/* mdio access */
#define MEI_XMEM_BAR15 ((u32*)(IFXMIPS_MEI_BASE_ADDR + 0x0090))
#define MEI_XMEM_BAR16 ((u32*)(IFXMIPS_MEI_BASE_ADDR + 0x0094))
+
+/*------------ FUSE */
+
+#define IFXMIPS_FUSE_BASE_ADDR (KSEG1 + 0x1F107354)
+
+
#endif
+obj-$(CONFIG_IFXMIPS_GPIO) += ifxmips_gpio.o
+obj-$(CONFIG_IFXMIPS_SSC) += ifxmips_ssc.o
+obj-$(CONFIG_IFXMIPS_EEPROM) += ifxmips_eeprom.o
-+obj-$(CONFIG_IFXMIPS_MEI) += ifxmips_mei_core.o ifxmips_mei_bsp.c ifxmips_mei_mib.c
++obj-$(CONFIG_IFXMIPS_MEI) += ifxmips_mei_core.o ifxmips_mei_bsp.o ifxmips_mei_mib.o