drm/i915: Shortcut readiness to reset check
authorMika Kuoppala <mika.kuoppala@linux.intel.com>
Fri, 12 Apr 2019 16:53:35 +0000 (19:53 +0300)
committerChris Wilson <chris@chris-wilson.co.uk>
Fri, 12 Apr 2019 18:20:27 +0000 (19:20 +0100)
If the engine says it is ready for reset, it is ready
so avoid further dancing and proceed.

v2: reg (Chris)
v3: request, ack, mask from following patch (Chris)

Cc: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Mika Kuoppala <mika.kuoppala@linux.intel.com>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Link: https://patchwork.freedesktop.org/patch/msgid/20190412165335.16347-1-mika.kuoppala@linux.intel.com
drivers/gpu/drm/i915/i915_reset.c

index 68875ba43b8d7e1cf3936207fdde75b4112c957b..8ce819bbd8ff558bc8d14e380838a8b0e39fa96b 100644 (file)
@@ -490,20 +490,26 @@ static int gen11_reset_engines(struct drm_i915_private *i915,
 static int gen8_engine_reset_prepare(struct intel_engine_cs *engine)
 {
        struct intel_uncore *uncore = engine->uncore;
+       const i915_reg_t reg = RING_RESET_CTL(engine->mmio_base);
+       u32 request, mask, ack;
        int ret;
 
-       intel_uncore_write_fw(uncore,
-                             RING_RESET_CTL(engine->mmio_base),
-                             _MASKED_BIT_ENABLE(RESET_CTL_REQUEST_RESET));
+       ack = intel_uncore_read_fw(uncore, reg);
+       if (!(ack & RESET_CTL_READY_TO_RESET)) {
+               request = RESET_CTL_REQUEST_RESET;
+               mask = RESET_CTL_READY_TO_RESET;
+               ack = RESET_CTL_READY_TO_RESET;
+       } else {
+               return 0;
+       }
 
-       ret = __intel_wait_for_register_fw(uncore,
-                                          RING_RESET_CTL(engine->mmio_base),
-                                          RESET_CTL_READY_TO_RESET,
-                                          RESET_CTL_READY_TO_RESET,
-                                          700, 0,
-                                          NULL);
+       intel_uncore_write_fw(uncore, reg, _MASKED_BIT_ENABLE(request));
+       ret = __intel_wait_for_register_fw(uncore, reg, mask, ack,
+                                          700, 0, NULL);
        if (ret)
-               DRM_ERROR("%s: reset request timeout\n", engine->name);
+               DRM_ERROR("%s reset request timed out: {request: %08x, RESET_CTL: %08x}\n",
+                         engine->name, request,
+                         intel_uncore_read_fw(uncore, reg));
 
        return ret;
 }