drm/i915/tgl: Fixing up list of PG3 power domains.

The DDI-IO power wells (PWR_WELL_CTL_DDI) are backing
the IO/PHY functionality, which doesn't need the PG3
power power well. Accordingly fixing up the list of
PG3 power domains.

Cc: Imre Deak <imre.deak@intel.com>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Anshuman Gupta <anshuman.gupta@intel.com>
Signed-off-by: Imre Deak <imre.deak@intel.com>
Reviewed-by: Imre Deak <imre.deak@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20190811100232.27964-1-anshuman.gupta@intel.com

diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c
index 99ed4b4d7c3c197245ab417730ae3096c4645dc9..374b75602141dafbd2e6500a6b6e6e10be184908 100644 (file)
--- a/drivers/gpu/drm/i915/display/intel_display_power.c
+++ b/drivers/gpu/drm/i915/display/intel_display_power.c
@@ -2570,17 +2570,11 @@ void intel_display_power_put(struct drm_i915_private *dev_priv,
        BIT_ULL(POWER_DOMAIN_TRANSCODER_D) |            \
        BIT_ULL(POWER_DOMAIN_PIPE_B_PANEL_FITTER) |     \
        BIT_ULL(POWER_DOMAIN_PORT_DDI_TC1_LANES) |      \
-       BIT_ULL(POWER_DOMAIN_PORT_DDI_TC1_IO) |         \
        BIT_ULL(POWER_DOMAIN_PORT_DDI_TC2_LANES) |      \
-       BIT_ULL(POWER_DOMAIN_PORT_DDI_TC2_IO) |         \
        BIT_ULL(POWER_DOMAIN_PORT_DDI_TC3_LANES) |      \
-       BIT_ULL(POWER_DOMAIN_PORT_DDI_TC3_IO) |         \
        BIT_ULL(POWER_DOMAIN_PORT_DDI_TC4_LANES) |      \
-       BIT_ULL(POWER_DOMAIN_PORT_DDI_TC4_IO) |         \
        BIT_ULL(POWER_DOMAIN_PORT_DDI_TC5_LANES) |      \
-       BIT_ULL(POWER_DOMAIN_PORT_DDI_TC5_IO) |         \
        BIT_ULL(POWER_DOMAIN_PORT_DDI_TC6_LANES) |      \
-       BIT_ULL(POWER_DOMAIN_PORT_DDI_TC6_IO) |         \
        BIT_ULL(POWER_DOMAIN_AUX_TC1) |         \
        BIT_ULL(POWER_DOMAIN_AUX_TC2) |         \
        BIT_ULL(POWER_DOMAIN_AUX_TC3) |         \