i40e: Opcode and structures required by OEM Post Update AQ command and add new NVM...
authorMichal Kosiarz <michal.kosiarz@intel.com>
Thu, 19 Nov 2015 19:34:20 +0000 (11:34 -0800)
committerJeff Kirsher <jeffrey.t.kirsher@intel.com>
Sun, 13 Dec 2015 05:08:31 +0000 (21:08 -0800)
This is a part of implementation which contains data structures and
opcode for new AQ command. There's a new ARQ message that gets sent
near the end of the NVM update process that the driver should recognize
and ignore, rather than printing an Unknown Event error.

Change-ID: I04830a5bcae14823e16b9424cc4165e169336c1f
Signed-off-by: Michal Kosiarz <michal.kosiarz@intel.com>
Acked-by: Shannon Nelson <shannon.nelson@intel.com>
Tested-by: Andrew Bowers <andrewx.bowers@intel.com>
Signed-off-by: Jeff Kirsher <jeffrey.t.kirsher@intel.com>
drivers/net/ethernet/intel/i40e/i40e_adminq_cmd.h
drivers/net/ethernet/intel/i40e/i40e_main.c
drivers/net/ethernet/intel/i40evf/i40e_adminq_cmd.h

index 61a49793594120b9cd4f006749af5f5ae0d962f8..b22012a446a6e127fc7ed83665e3d629f441e4f2 100644 (file)
@@ -227,6 +227,7 @@ enum i40e_admin_queue_opc {
        i40e_aqc_opc_nvm_update                 = 0x0703,
        i40e_aqc_opc_nvm_config_read            = 0x0704,
        i40e_aqc_opc_nvm_config_write           = 0x0705,
+       i40e_aqc_opc_oem_post_update            = 0x0720,
 
        /* virtualization commands */
        i40e_aqc_opc_send_msg_to_pf             = 0x0801,
@@ -1891,6 +1892,26 @@ struct i40e_aqc_nvm_config_data_immediate_field {
 
 I40E_CHECK_STRUCT_LEN(0xc, i40e_aqc_nvm_config_data_immediate_field);
 
+/* OEM Post Update (indirect 0x0720)
+ * no command data struct used
+ */
+struct i40e_aqc_nvm_oem_post_update {
+#define I40E_AQ_NVM_OEM_POST_UPDATE_EXTERNAL_DATA      0x01
+       u8 sel_data;
+       u8 reserved[7];
+};
+
+I40E_CHECK_STRUCT_LEN(0x8, i40e_aqc_nvm_oem_post_update);
+
+struct i40e_aqc_nvm_oem_post_update_buffer {
+       u8 str_len;
+       u8 dev_addr;
+       __le16 eeprom_addr;
+       u8 data[36];
+};
+
+I40E_CHECK_STRUCT_LEN(0x28, i40e_aqc_nvm_oem_post_update_buffer);
+
 /* Send to PF command (indirect 0x0801) id is only used by PF
  * Send to VF command (indirect 0x0802) id is only used by PF
  * Send to Peer PF command (indirect 0x0803)
index 36d1c2bb0120ab2ffd80e2ab44de87e006b49619..aff401fee2a4d867ac9f7d0750d4008c58d57de5 100644 (file)
@@ -6295,6 +6295,7 @@ static void i40e_clean_adminq_subtask(struct i40e_pf *pf)
                        break;
                case i40e_aqc_opc_nvm_erase:
                case i40e_aqc_opc_nvm_update:
+               case i40e_aqc_opc_oem_post_update:
                        i40e_debug(&pf->hw, I40E_DEBUG_NVM, "ARQ NVM operation completed\n");
                        break;
                default:
index 1c76389bd8882699de5e5a8f7de070982535d5fc..f5b2b369dc7ce883820faae432e1f10947e29d14 100644 (file)
@@ -227,6 +227,7 @@ enum i40e_admin_queue_opc {
        i40e_aqc_opc_nvm_update                 = 0x0703,
        i40e_aqc_opc_nvm_config_read            = 0x0704,
        i40e_aqc_opc_nvm_config_write           = 0x0705,
+       i40e_aqc_opc_oem_post_update            = 0x0720,
 
        /* virtualization commands */
        i40e_aqc_opc_send_msg_to_pf             = 0x0801,
@@ -1888,6 +1889,26 @@ struct i40e_aqc_nvm_config_data_immediate_field {
 
 I40E_CHECK_STRUCT_LEN(0xc, i40e_aqc_nvm_config_data_immediate_field);
 
+/* OEM Post Update (indirect 0x0720)
+ * no command data struct used
+ */
+ struct i40e_aqc_nvm_oem_post_update {
+#define I40E_AQ_NVM_OEM_POST_UPDATE_EXTERNAL_DATA      0x01
+       u8 sel_data;
+       u8 reserved[7];
+};
+
+I40E_CHECK_STRUCT_LEN(0x8, i40e_aqc_nvm_oem_post_update);
+
+struct i40e_aqc_nvm_oem_post_update_buffer {
+       u8 str_len;
+       u8 dev_addr;
+       __le16 eeprom_addr;
+       u8 data[36];
+};
+
+I40E_CHECK_STRUCT_LEN(0x28, i40e_aqc_nvm_oem_post_update_buffer);
+
 /* Send to PF command (indirect 0x0801) id is only used by PF
  * Send to VF command (indirect 0x0802) id is only used by PF
  * Send to Peer PF command (indirect 0x0803)