Merge branch 'for-next' of git://git.kernel.org/pub/scm/linux/kernel/git/jikos/trivial
authorLinus Torvalds <torvalds@linux-foundation.org>
Thu, 13 Jan 2011 18:05:56 +0000 (10:05 -0800)
committerLinus Torvalds <torvalds@linux-foundation.org>
Thu, 13 Jan 2011 18:05:56 +0000 (10:05 -0800)
* 'for-next' of git://git.kernel.org/pub/scm/linux/kernel/git/jikos/trivial: (43 commits)
  Documentation/trace/events.txt: Remove obsolete sched_signal_send.
  writeback: fix global_dirty_limits comment runtime -> real-time
  ppc: fix comment typo singal -> signal
  drivers: fix comment typo diable -> disable.
  m68k: fix comment typo diable -> disable.
  wireless: comment typo fix diable -> disable.
  media: comment typo fix diable -> disable.
  remove doc for obsolete dynamic-printk kernel-parameter
  remove extraneous 'is' from Documentation/iostats.txt
  Fix spelling milisec -> ms in snd_ps3 module parameter description
  Fix spelling mistakes in comments
  Revert conflicting V4L changes
  i7core_edac: fix typos in comments
  mm/rmap.c: fix comment
  sound, ca0106: Fix assignment to 'channel'.
  hrtimer: fix a typo in comment
  init/Kconfig: fix typo
  anon_inodes: fix wrong function name in comment
  fix comment typos concerning "consistent"
  poll: fix a typo in comment
  ...

Fix up trivial conflicts in:
 - drivers/net/wireless/iwlwifi/iwl-core.c (moved to iwl-legacy.c)
 - fs/ext4/ext4.h

Also fix missed 'diabled' typo in drivers/net/bnx2x/bnx2x.h while at it.

112 files changed:
1  2 
Documentation/kernel-parameters.txt
Documentation/networking/dccp.txt
Documentation/powerpc/booting-without-of.txt
MAINTAINERS
arch/arm/common/it8152.c
arch/arm/mach-imx/pm-imx27.c
arch/arm/mach-msm/io.c
arch/arm/mach-omap1/pm.c
arch/arm/mach-omap2/cpuidle34xx.c
arch/arm/mach-omap2/pm24xx.c
arch/arm/mach-omap2/pm34xx.c
arch/arm/mach-omap2/pm44xx.c
arch/arm/mach-omap2/serial.c
arch/arm/mach-pxa/sharpsl_pm.c
arch/arm/mm/flush.c
arch/arm/plat-mxc/include/mach/irqs.h
arch/arm/plat-omap/include/plat/omap_hwmod.h
arch/blackfin/mach-bf537/include/mach/defBF534.h
arch/blackfin/mach-common/pm.c
arch/x86/include/asm/processor.h
arch/x86/kernel/head_32.S
arch/x86/platform/mrst/early_printk_mrst.c
drivers/ata/libata-core.c
drivers/base/bus.c
drivers/base/power/main.c
drivers/edac/edac_core.h
drivers/gpu/drm/nouveau/nouveau_bios.c
drivers/gpu/drm/radeon/atombios.h
drivers/infiniband/hw/cxgb4/iw_cxgb4.h
drivers/infiniband/hw/qib/qib_iba7322.c
drivers/input/serio/Kconfig
drivers/input/touchscreen/Kconfig
drivers/media/video/cx25840/cx25840-ir.c
drivers/media/video/omap/omap_vout.c
drivers/media/video/saa7164/saa7164-core.c
drivers/media/video/via-camera.c
drivers/mmc/host/Kconfig
drivers/net/bnx2x/bnx2x.h
drivers/net/bnx2x/bnx2x_main.c
drivers/net/bnx2x/bnx2x_reg.h
drivers/net/bonding/bond_3ad.c
drivers/net/cxgb3/t3_hw.c
drivers/net/e1000/e1000_hw.h
drivers/net/e1000/e1000_main.c
drivers/net/e1000e/82571.c
drivers/net/e1000e/ich8lan.c
drivers/net/e1000e/phy.c
drivers/net/eepro.c
drivers/net/ixgbe/ixgbe_82599.c
drivers/net/ll_temac_main.c
drivers/net/tehuti.c
drivers/net/tun.c
drivers/net/vxge/vxge-traffic.h
drivers/net/wan/dscc4.c
drivers/net/wimax/i2400m/driver.c
drivers/net/wimax/i2400m/i2400m.h
drivers/net/wireless/ath/ath5k/reg.h
drivers/net/wireless/iwlwifi/iwl-agn.c
drivers/net/wireless/iwlwifi/iwl-legacy.c
drivers/net/wireless/iwlwifi/iwl-sta.c
drivers/net/wireless/rt2x00/rt2x00mac.c
drivers/net/wireless/wl1251/wl1251.h
drivers/net/wireless/wl12xx/acx.h
drivers/net/wireless/wl12xx/wl12xx.h
drivers/platform/x86/acer-wmi.c
drivers/platform/x86/eeepc-laptop.c
drivers/platform/x86/fujitsu-laptop.c
drivers/platform/x86/sony-laptop.c
drivers/platform/x86/thinkpad_acpi.c
drivers/s390/net/lcs.c
drivers/s390/scsi/zfcp_cfdc.c
drivers/scsi/bfa/bfa_fcpim.c
drivers/scsi/bfa/bfa_fcs_lport.c
drivers/scsi/libfc/fc_fcp.c
drivers/scsi/lpfc/lpfc_attr.c
drivers/scsi/lpfc/lpfc_hbadisc.c
drivers/scsi/lpfc/lpfc_init.c
drivers/scsi/lpfc/lpfc_sli.c
drivers/scsi/scsi_sysfs.c
drivers/staging/olpc_dcon/olpc_dcon.c
drivers/telephony/ixj.c
drivers/usb/gadget/imx_udc.c
drivers/usb/gadget/langwell_udc.c
drivers/usb/musb/musb_gadget.c
drivers/video/aty/atyfb_base.c
fs/anon_inodes.c
fs/coda/inode.c
fs/ext4/ext4.h
fs/ext4/extents.c
fs/ext4/inode.c
fs/jbd2/transaction.c
fs/xfs/linux-2.6/xfs_super.c
include/linux/suspend.h
init/Kconfig
kernel/hrtimer.c
kernel/perf_event.c
kernel/power/hibernate.c
kernel/power/suspend.c
kernel/sched.c
kernel/sysctl_binary.c
kernel/time/clocksource.c
lib/nlattr.c
mm/page-writeback.c
mm/percpu.c
net/Kconfig
net/core/dev.c
net/decnet/dn_dev.c
net/ipv4/tcp_output.c
net/ipv6/af_inet6.c
scripts/mod/modpost.c
security/apparmor/include/match.h
sound/soc/codecs/max98088.c

Simple merge
Simple merge
diff --cc MAINTAINERS
Simple merge
Simple merge
Simple merge
Simple merge
Simple merge
Simple merge
index dac2d1d9987dfc205faca395c9e9961f64220652,f3f3bfa230d7218d4a0cd4a87db660ac5fec0710..9e5dc8ed51e9a0530a87361bfcd571c91a36c6f8
@@@ -347,12 -352,18 +347,12 @@@ static int omap2_pm_enter(suspend_state
  static void omap2_pm_end(void)
  {
        suspend_state = PM_SUSPEND_ON;
 +      enable_hlt();
  }
  
- static struct platform_suspend_ops omap_pm_ops = {
+ static const struct platform_suspend_ops omap_pm_ops = {
        .begin          = omap2_pm_begin,
 -      .prepare        = omap2_pm_prepare,
        .enter          = omap2_pm_enter,
 -      .finish         = omap2_pm_finish,
        .end            = omap2_pm_end,
        .valid          = suspend_valid_only_mem,
  };
index 5b323f28da2dce177c49da1729ed884a0d741e96,0cb20d29f70c006f3fb09d61f669d474de36772a..8cbbeade4b8a87df8eafe3de9ce7292131947969
@@@ -605,10 -617,12 +605,10 @@@ static void omap3_pm_end(void
        return;
  }
  
- static struct platform_suspend_ops omap_pm_ops = {
+ static const struct platform_suspend_ops omap_pm_ops = {
        .begin          = omap3_pm_begin,
        .end            = omap3_pm_end,
 -      .prepare        = omap3_pm_prepare,
        .enter          = omap3_pm_enter,
 -      .finish         = omap3_pm_finish,
        .valid          = suspend_valid_only_mem,
  };
  #endif /* CONFIG_SUSPEND */
index e9f4862c4de4f4e2f54d1162ff536c05ac67af73,dc8b1ef9f84c4c4f11496f1a05b549f63f054291..76cfff2db5141e26b2b0b7a0396abb37f342ec92
@@@ -65,10 -75,12 +65,10 @@@ static void omap4_pm_end(void
        return;
  }
  
- static struct platform_suspend_ops omap_pm_ops = {
+ static const struct platform_suspend_ops omap_pm_ops = {
        .begin          = omap4_pm_begin,
        .end            = omap4_pm_end,
 -      .prepare        = omap4_pm_prepare,
        .enter          = omap4_pm_enter,
 -      .finish         = omap4_pm_finish,
        .valid          = suspend_valid_only_mem,
  };
  #endif /* CONFIG_SUSPEND */
Simple merge
Simple merge
Simple merge
Simple merge
Simple merge
Simple merge
Simple merge
index 65df603622b2a64bf04639ecc644bf6e43c7e784,0000000000000000000000000000000000000000..25bfdbb5b1302937ce93343bcbd20372c6064b1a
mode 100644,000000..100644
--- /dev/null
@@@ -1,319 -1,0 +1,319 @@@
- /* Always contains an accessable address, start with 0 */
 +/*
 + * early_printk_mrst.c - early consoles for Intel MID platforms
 + *
 + * Copyright (c) 2008-2010, Intel Corporation
 + *
 + * This program is free software; you can redistribute it and/or
 + * modify it under the terms of the GNU General Public License
 + * as published by the Free Software Foundation; version 2
 + * of the License.
 + */
 +
 +/*
 + * This file implements two early consoles named mrst and hsu.
 + * mrst is based on Maxim3110 spi-uart device, it exists in both
 + * Moorestown and Medfield platforms, while hsu is based on a High
 + * Speed UART device which only exists in the Medfield platform
 + */
 +
 +#include <linux/serial_reg.h>
 +#include <linux/serial_mfd.h>
 +#include <linux/kmsg_dump.h>
 +#include <linux/console.h>
 +#include <linux/kernel.h>
 +#include <linux/delay.h>
 +#include <linux/init.h>
 +#include <linux/io.h>
 +
 +#include <asm/fixmap.h>
 +#include <asm/pgtable.h>
 +#include <asm/mrst.h>
 +
 +#define MRST_SPI_TIMEOUT              0x200000
 +#define MRST_REGBASE_SPI0             0xff128000
 +#define MRST_REGBASE_SPI1             0xff128400
 +#define MRST_CLK_SPI0_REG             0xff11d86c
 +
 +/* Bit fields in CTRLR0 */
 +#define SPI_DFS_OFFSET                        0
 +
 +#define SPI_FRF_OFFSET                        4
 +#define SPI_FRF_SPI                   0x0
 +#define SPI_FRF_SSP                   0x1
 +#define SPI_FRF_MICROWIRE             0x2
 +#define SPI_FRF_RESV                  0x3
 +
 +#define SPI_MODE_OFFSET                       6
 +#define SPI_SCPH_OFFSET                       6
 +#define SPI_SCOL_OFFSET                       7
 +#define SPI_TMOD_OFFSET                       8
 +#define       SPI_TMOD_TR                     0x0             /* xmit & recv */
 +#define SPI_TMOD_TO                   0x1             /* xmit only */
 +#define SPI_TMOD_RO                   0x2             /* recv only */
 +#define SPI_TMOD_EPROMREAD            0x3             /* eeprom read mode */
 +
 +#define SPI_SLVOE_OFFSET              10
 +#define SPI_SRL_OFFSET                        11
 +#define SPI_CFS_OFFSET                        12
 +
 +/* Bit fields in SR, 7 bits */
 +#define SR_MASK                               0x7f            /* cover 7 bits */
 +#define SR_BUSY                               (1 << 0)
 +#define SR_TF_NOT_FULL                        (1 << 1)
 +#define SR_TF_EMPT                    (1 << 2)
 +#define SR_RF_NOT_EMPT                        (1 << 3)
 +#define SR_RF_FULL                    (1 << 4)
 +#define SR_TX_ERR                     (1 << 5)
 +#define SR_DCOL                               (1 << 6)
 +
 +struct dw_spi_reg {
 +      u32     ctrl0;
 +      u32     ctrl1;
 +      u32     ssienr;
 +      u32     mwcr;
 +      u32     ser;
 +      u32     baudr;
 +      u32     txfltr;
 +      u32     rxfltr;
 +      u32     txflr;
 +      u32     rxflr;
 +      u32     sr;
 +      u32     imr;
 +      u32     isr;
 +      u32     risr;
 +      u32     txoicr;
 +      u32     rxoicr;
 +      u32     rxuicr;
 +      u32     msticr;
 +      u32     icr;
 +      u32     dmacr;
 +      u32     dmatdlr;
 +      u32     dmardlr;
 +      u32     idr;
 +      u32     version;
 +
 +      /* Currently operates as 32 bits, though only the low 16 bits matter */
 +      u32     dr;
 +} __packed;
 +
 +#define dw_readl(dw, name)            __raw_readl(&(dw)->name)
 +#define dw_writel(dw, name, val)      __raw_writel((val), &(dw)->name)
 +
 +/* Default use SPI0 register for mrst, we will detect Penwell and use SPI1 */
 +static unsigned long mrst_spi_paddr = MRST_REGBASE_SPI0;
 +
 +static u32 *pclk_spi0;
++/* Always contains an accessible address, start with 0 */
 +static struct dw_spi_reg *pspi;
 +
 +static struct kmsg_dumper dw_dumper;
 +static int dumper_registered;
 +
 +static void dw_kmsg_dump(struct kmsg_dumper *dumper,
 +                      enum kmsg_dump_reason reason,
 +                      const char *s1, unsigned long l1,
 +                      const char *s2, unsigned long l2)
 +{
 +      int i;
 +
 +      /* When run to this, we'd better re-init the HW */
 +      mrst_early_console_init();
 +
 +      for (i = 0; i < l1; i++)
 +              early_mrst_console.write(&early_mrst_console, s1 + i, 1);
 +      for (i = 0; i < l2; i++)
 +              early_mrst_console.write(&early_mrst_console, s2 + i, 1);
 +}
 +
 +/* Set the ratio rate to 115200, 8n1, IRQ disabled */
 +static void max3110_write_config(void)
 +{
 +      u16 config;
 +
 +      config = 0xc001;
 +      dw_writel(pspi, dr, config);
 +}
 +
 +/* Translate char to a eligible word and send to max3110 */
 +static void max3110_write_data(char c)
 +{
 +      u16 data;
 +
 +      data = 0x8000 | c;
 +      dw_writel(pspi, dr, data);
 +}
 +
 +void mrst_early_console_init(void)
 +{
 +      u32 ctrlr0 = 0;
 +      u32 spi0_cdiv;
 +      u32 freq; /* Freqency info only need be searched once */
 +
 +      /* Base clk is 100 MHz, the actual clk = 100M / (clk_divider + 1) */
 +      pclk_spi0 = (void *)set_fixmap_offset_nocache(FIX_EARLYCON_MEM_BASE,
 +                                                      MRST_CLK_SPI0_REG);
 +      spi0_cdiv = ((*pclk_spi0) & 0xe00) >> 9;
 +      freq = 100000000 / (spi0_cdiv + 1);
 +
 +      if (mrst_identify_cpu() == MRST_CPU_CHIP_PENWELL)
 +              mrst_spi_paddr = MRST_REGBASE_SPI1;
 +
 +      pspi = (void *)set_fixmap_offset_nocache(FIX_EARLYCON_MEM_BASE,
 +                                              mrst_spi_paddr);
 +
 +      /* Disable SPI controller */
 +      dw_writel(pspi, ssienr, 0);
 +
 +      /* Set control param, 8 bits, transmit only mode */
 +      ctrlr0 = dw_readl(pspi, ctrl0);
 +
 +      ctrlr0 &= 0xfcc0;
 +      ctrlr0 |= 0xf | (SPI_FRF_SPI << SPI_FRF_OFFSET)
 +                    | (SPI_TMOD_TO << SPI_TMOD_OFFSET);
 +      dw_writel(pspi, ctrl0, ctrlr0);
 +
 +      /*
 +       * Change the spi0 clk to comply with 115200 bps, use 100000 to
 +       * calculate the clk dividor to make the clock a little slower
 +       * than real baud rate.
 +       */
 +      dw_writel(pspi, baudr, freq/100000);
 +
 +      /* Disable all INT for early phase */
 +      dw_writel(pspi, imr, 0x0);
 +
 +      /* Set the cs to spi-uart */
 +      dw_writel(pspi, ser, 0x2);
 +
 +      /* Enable the HW, the last step for HW init */
 +      dw_writel(pspi, ssienr, 0x1);
 +
 +      /* Set the default configuration */
 +      max3110_write_config();
 +
 +      /* Register the kmsg dumper */
 +      if (!dumper_registered) {
 +              dw_dumper.dump = dw_kmsg_dump;
 +              kmsg_dump_register(&dw_dumper);
 +              dumper_registered = 1;
 +      }
 +}
 +
 +/* Slave select should be called in the read/write function */
 +static void early_mrst_spi_putc(char c)
 +{
 +      unsigned int timeout;
 +      u32 sr;
 +
 +      timeout = MRST_SPI_TIMEOUT;
 +      /* Early putc needs to make sure the TX FIFO is not full */
 +      while (--timeout) {
 +              sr = dw_readl(pspi, sr);
 +              if (!(sr & SR_TF_NOT_FULL))
 +                      cpu_relax();
 +              else
 +                      break;
 +      }
 +
 +      if (!timeout)
 +              pr_warning("MRST earlycon: timed out\n");
 +      else
 +              max3110_write_data(c);
 +}
 +
 +/* Early SPI only uses polling mode */
 +static void early_mrst_spi_write(struct console *con, const char *str, unsigned n)
 +{
 +      int i;
 +
 +      for (i = 0; i < n && *str; i++) {
 +              if (*str == '\n')
 +                      early_mrst_spi_putc('\r');
 +              early_mrst_spi_putc(*str);
 +              str++;
 +      }
 +}
 +
 +struct console early_mrst_console = {
 +      .name =         "earlymrst",
 +      .write =        early_mrst_spi_write,
 +      .flags =        CON_PRINTBUFFER,
 +      .index =        -1,
 +};
 +
 +/*
 + * Following is the early console based on Medfield HSU (High
 + * Speed UART) device.
 + */
 +#define HSU_PORT2_PADDR               0xffa28180
 +
 +static void __iomem *phsu;
 +
 +void hsu_early_console_init(void)
 +{
 +      u8 lcr;
 +
 +      phsu = (void *)set_fixmap_offset_nocache(FIX_EARLYCON_MEM_BASE,
 +                                                      HSU_PORT2_PADDR);
 +
 +      /* Disable FIFO */
 +      writeb(0x0, phsu + UART_FCR);
 +
 +      /* Set to default 115200 bps, 8n1 */
 +      lcr = readb(phsu + UART_LCR);
 +      writeb((0x80 | lcr), phsu + UART_LCR);
 +      writeb(0x18, phsu + UART_DLL);
 +      writeb(lcr,  phsu + UART_LCR);
 +      writel(0x3600, phsu + UART_MUL*4);
 +
 +      writeb(0x8, phsu + UART_MCR);
 +      writeb(0x7, phsu + UART_FCR);
 +      writeb(0x3, phsu + UART_LCR);
 +
 +      /* Clear IRQ status */
 +      readb(phsu + UART_LSR);
 +      readb(phsu + UART_RX);
 +      readb(phsu + UART_IIR);
 +      readb(phsu + UART_MSR);
 +
 +      /* Enable FIFO */
 +      writeb(0x7, phsu + UART_FCR);
 +}
 +
 +#define BOTH_EMPTY (UART_LSR_TEMT | UART_LSR_THRE)
 +
 +static void early_hsu_putc(char ch)
 +{
 +      unsigned int timeout = 10000; /* 10ms */
 +      u8 status;
 +
 +      while (--timeout) {
 +              status = readb(phsu + UART_LSR);
 +              if (status & BOTH_EMPTY)
 +                      break;
 +              udelay(1);
 +      }
 +
 +      /* Only write the char when there was no timeout */
 +      if (timeout)
 +              writeb(ch, phsu + UART_TX);
 +}
 +
 +static void early_hsu_write(struct console *con, const char *str, unsigned n)
 +{
 +      int i;
 +
 +      for (i = 0; i < n && *str; i++) {
 +              if (*str == '\n')
 +                      early_hsu_putc('\r');
 +              early_hsu_putc(*str);
 +              str++;
 +      }
 +}
 +
 +struct console early_hsu_console = {
 +      .name =         "earlyhsu",
 +      .write =        early_hsu_write,
 +      .flags =        CON_PRINTBUFFER,
 +      .index =        -1,
 +};
Simple merge
Simple merge
Simple merge
Simple merge
Simple merge
Simple merge
Simple merge
Simple merge
Simple merge
Simple merge
index 6a858a29db56127d3f9346adb6b7ab31c617cf0c,d255428122fc0b87d3e4ff2925410b5b2d5f6a47..a6cd335c943656a9ac67d37c15ea5d9eea3cc899
@@@ -1377,54 -1280,11 +1377,54 @@@ struct bnx2x_func_init_params 
        u16             spq_prod;       /* valid iff FUNC_FLG_SPQ */
  };
  
 +#define for_each_eth_queue(bp, var) \
 +                      for (var = 0; var < BNX2X_NUM_ETH_QUEUES(bp); var++)
 +
 +#define for_each_nondefault_eth_queue(bp, var) \
 +                      for (var = 1; var < BNX2X_NUM_ETH_QUEUES(bp); var++)
 +
 +#define for_each_napi_queue(bp, var) \
 +      for (var = 0; \
 +              var < BNX2X_NUM_ETH_QUEUES(bp) + FCOE_CONTEXT_USE; var++) \
 +              if (skip_queue(bp, var))        \
 +                      continue;               \
 +              else
 +
  #define for_each_queue(bp, var) \
 -                      for (var = 0; var < BNX2X_NUM_QUEUES(bp); var++)
 +      for (var = 0; var < BNX2X_NUM_QUEUES(bp); var++) \
 +              if (skip_queue(bp, var))        \
 +                      continue;               \
 +              else
 +
 +#define for_each_rx_queue(bp, var) \
 +      for (var = 0; var < BNX2X_NUM_QUEUES(bp); var++) \
 +              if (skip_rx_queue(bp, var))     \
 +                      continue;               \
 +              else
 +
 +#define for_each_tx_queue(bp, var) \
 +      for (var = 0; var < BNX2X_NUM_QUEUES(bp); var++) \
 +              if (skip_tx_queue(bp, var))     \
 +                      continue;               \
 +              else
 +
  #define for_each_nondefault_queue(bp, var) \
 -                      for (var = 1; var < BNX2X_NUM_QUEUES(bp); var++)
 +      for (var = 1; var < BNX2X_NUM_QUEUES(bp); var++) \
 +              if (skip_queue(bp, var))        \
 +                      continue;               \
 +              else
 +
 +/* skip rx queue
-  * if FCOE l2 support is diabled and this is the fcoe L2 queue
++ * if FCOE l2 support is disabled and this is the fcoe L2 queue
 + */
 +#define skip_rx_queue(bp, idx)        (NO_FCOE(bp) && IS_FCOE_IDX(idx))
  
-  * if FCOE l2 support is diabled and this is the fcoe L2 queue
 +/* skip tx queue
++ * if FCOE l2 support is disabled and this is the fcoe L2 queue
 + */
 +#define skip_tx_queue(bp, idx)        (NO_FCOE(bp) && IS_FCOE_IDX(idx))
 +
 +#define skip_queue(bp, idx)   (NO_FCOE(bp) && IS_FCOE_IDX(idx))
  
  #define WAIT_RAMROD_POLL      0x01
  #define WAIT_RAMROD_COMMON    0x02
Simple merge
Simple merge
Simple merge
Simple merge
Simple merge
Simple merge
Simple merge
Simple merge
Simple merge
Simple merge
Simple merge
Simple merge
Simple merge
Simple merge
Simple merge
Simple merge
Simple merge
Simple merge
Simple merge
index a08b4e56e6b169dad9ab17b6039beb41e2485c8f,0000000000000000000000000000000000000000..bb1a742a98a0ed86b95f0643b2747a7e37b69ca3
mode 100644,000000..100644
--- /dev/null
@@@ -1,662 -1,0 +1,662 @@@
-       /* only Re-enable if diabled by irq */
 +/******************************************************************************
 + *
 + * GPL LICENSE SUMMARY
 + *
 + * Copyright(c) 2008 - 2010 Intel Corporation. All rights reserved.
 + *
 + * This program is free software; you can redistribute it and/or modify
 + * it under the terms of version 2 of the GNU General Public License as
 + * published by the Free Software Foundation.
 + *
 + * This program is distributed in the hope that it will be useful, but
 + * WITHOUT ANY WARRANTY; without even the implied warranty of
 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
 + * General Public License for more details.
 + *
 + * You should have received a copy of the GNU General Public License
 + * along with this program; if not, write to the Free Software
 + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110,
 + * USA
 + *
 + * The full GNU General Public License is included in this distribution
 + * in the file called LICENSE.GPL.
 + *
 + * Contact Information:
 + *  Intel Linux Wireless <ilw@linux.intel.com>
 + * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
 + *****************************************************************************/
 +
 +#include <linux/kernel.h>
 +#include <net/mac80211.h>
 +
 +#include "iwl-dev.h"
 +#include "iwl-core.h"
 +#include "iwl-helpers.h"
 +#include "iwl-legacy.h"
 +
 +static void iwl_update_qos(struct iwl_priv *priv, struct iwl_rxon_context *ctx)
 +{
 +      if (test_bit(STATUS_EXIT_PENDING, &priv->status))
 +              return;
 +
 +      if (!ctx->is_active)
 +              return;
 +
 +      ctx->qos_data.def_qos_parm.qos_flags = 0;
 +
 +      if (ctx->qos_data.qos_active)
 +              ctx->qos_data.def_qos_parm.qos_flags |=
 +                      QOS_PARAM_FLG_UPDATE_EDCA_MSK;
 +
 +      if (ctx->ht.enabled)
 +              ctx->qos_data.def_qos_parm.qos_flags |= QOS_PARAM_FLG_TGN_MSK;
 +
 +      IWL_DEBUG_QOS(priv, "send QoS cmd with Qos active=%d FLAGS=0x%X\n",
 +                    ctx->qos_data.qos_active,
 +                    ctx->qos_data.def_qos_parm.qos_flags);
 +
 +      iwl_send_cmd_pdu_async(priv, ctx->qos_cmd,
 +                             sizeof(struct iwl_qosparam_cmd),
 +                             &ctx->qos_data.def_qos_parm, NULL);
 +}
 +
 +/**
 + * iwl_legacy_mac_config - mac80211 config callback
 + */
 +int iwl_legacy_mac_config(struct ieee80211_hw *hw, u32 changed)
 +{
 +      struct iwl_priv *priv = hw->priv;
 +      const struct iwl_channel_info *ch_info;
 +      struct ieee80211_conf *conf = &hw->conf;
 +      struct ieee80211_channel *channel = conf->channel;
 +      struct iwl_ht_config *ht_conf = &priv->current_ht_config;
 +      struct iwl_rxon_context *ctx;
 +      unsigned long flags = 0;
 +      int ret = 0;
 +      u16 ch;
 +      int scan_active = 0;
 +      bool ht_changed[NUM_IWL_RXON_CTX] = {};
 +
 +      if (WARN_ON(!priv->cfg->ops->legacy))
 +              return -EOPNOTSUPP;
 +
 +      mutex_lock(&priv->mutex);
 +
 +      IWL_DEBUG_MAC80211(priv, "enter to channel %d changed 0x%X\n",
 +                                      channel->hw_value, changed);
 +
 +      if (unlikely(!priv->cfg->mod_params->disable_hw_scan &&
 +                      test_bit(STATUS_SCANNING, &priv->status))) {
 +              scan_active = 1;
 +              IWL_DEBUG_MAC80211(priv, "leave - scanning\n");
 +      }
 +
 +      if (changed & (IEEE80211_CONF_CHANGE_SMPS |
 +                     IEEE80211_CONF_CHANGE_CHANNEL)) {
 +              /* mac80211 uses static for non-HT which is what we want */
 +              priv->current_ht_config.smps = conf->smps_mode;
 +
 +              /*
 +               * Recalculate chain counts.
 +               *
 +               * If monitor mode is enabled then mac80211 will
 +               * set up the SM PS mode to OFF if an HT channel is
 +               * configured.
 +               */
 +              if (priv->cfg->ops->hcmd->set_rxon_chain)
 +                      for_each_context(priv, ctx)
 +                              priv->cfg->ops->hcmd->set_rxon_chain(priv, ctx);
 +      }
 +
 +      /* during scanning mac80211 will delay channel setting until
 +       * scan finish with changed = 0
 +       */
 +      if (!changed || (changed & IEEE80211_CONF_CHANGE_CHANNEL)) {
 +              if (scan_active)
 +                      goto set_ch_out;
 +
 +              ch = channel->hw_value;
 +              ch_info = iwl_get_channel_info(priv, channel->band, ch);
 +              if (!is_channel_valid(ch_info)) {
 +                      IWL_DEBUG_MAC80211(priv, "leave - invalid channel\n");
 +                      ret = -EINVAL;
 +                      goto set_ch_out;
 +              }
 +
 +              spin_lock_irqsave(&priv->lock, flags);
 +
 +              for_each_context(priv, ctx) {
 +                      /* Configure HT40 channels */
 +                      if (ctx->ht.enabled != conf_is_ht(conf)) {
 +                              ctx->ht.enabled = conf_is_ht(conf);
 +                              ht_changed[ctx->ctxid] = true;
 +                      }
 +                      if (ctx->ht.enabled) {
 +                              if (conf_is_ht40_minus(conf)) {
 +                                      ctx->ht.extension_chan_offset =
 +                                              IEEE80211_HT_PARAM_CHA_SEC_BELOW;
 +                                      ctx->ht.is_40mhz = true;
 +                              } else if (conf_is_ht40_plus(conf)) {
 +                                      ctx->ht.extension_chan_offset =
 +                                              IEEE80211_HT_PARAM_CHA_SEC_ABOVE;
 +                                      ctx->ht.is_40mhz = true;
 +                              } else {
 +                                      ctx->ht.extension_chan_offset =
 +                                              IEEE80211_HT_PARAM_CHA_SEC_NONE;
 +                                      ctx->ht.is_40mhz = false;
 +                              }
 +                      } else
 +                              ctx->ht.is_40mhz = false;
 +
 +                      /*
 +                       * Default to no protection. Protection mode will
 +                       * later be set from BSS config in iwl_ht_conf
 +                       */
 +                      ctx->ht.protection = IEEE80211_HT_OP_MODE_PROTECTION_NONE;
 +
 +                      /* if we are switching from ht to 2.4 clear flags
 +                       * from any ht related info since 2.4 does not
 +                       * support ht */
 +                      if ((le16_to_cpu(ctx->staging.channel) != ch))
 +                              ctx->staging.flags = 0;
 +
 +                      iwl_set_rxon_channel(priv, channel, ctx);
 +                      iwl_set_rxon_ht(priv, ht_conf);
 +
 +                      iwl_set_flags_for_band(priv, ctx, channel->band,
 +                                             ctx->vif);
 +              }
 +
 +              spin_unlock_irqrestore(&priv->lock, flags);
 +
 +              if (priv->cfg->ops->legacy->update_bcast_stations)
 +                      ret = priv->cfg->ops->legacy->update_bcast_stations(priv);
 +
 + set_ch_out:
 +              /* The list of supported rates and rate mask can be different
 +               * for each band; since the band may have changed, reset
 +               * the rate mask to what mac80211 lists */
 +              iwl_set_rate(priv);
 +      }
 +
 +      if (changed & (IEEE80211_CONF_CHANGE_PS |
 +                      IEEE80211_CONF_CHANGE_IDLE)) {
 +              ret = iwl_power_update_mode(priv, false);
 +              if (ret)
 +                      IWL_DEBUG_MAC80211(priv, "Error setting sleep level\n");
 +      }
 +
 +      if (changed & IEEE80211_CONF_CHANGE_POWER) {
 +              IWL_DEBUG_MAC80211(priv, "TX Power old=%d new=%d\n",
 +                      priv->tx_power_user_lmt, conf->power_level);
 +
 +              iwl_set_tx_power(priv, conf->power_level, false);
 +      }
 +
 +      if (!iwl_is_ready(priv)) {
 +              IWL_DEBUG_MAC80211(priv, "leave - not ready\n");
 +              goto out;
 +      }
 +
 +      if (scan_active)
 +              goto out;
 +
 +      for_each_context(priv, ctx) {
 +              if (memcmp(&ctx->active, &ctx->staging, sizeof(ctx->staging)))
 +                      iwlcore_commit_rxon(priv, ctx);
 +              else
 +                      IWL_DEBUG_INFO(priv,
 +                              "Not re-sending same RXON configuration.\n");
 +              if (ht_changed[ctx->ctxid])
 +                      iwl_update_qos(priv, ctx);
 +      }
 +
 +out:
 +      IWL_DEBUG_MAC80211(priv, "leave\n");
 +      mutex_unlock(&priv->mutex);
 +      return ret;
 +}
 +EXPORT_SYMBOL(iwl_legacy_mac_config);
 +
 +void iwl_legacy_mac_reset_tsf(struct ieee80211_hw *hw)
 +{
 +      struct iwl_priv *priv = hw->priv;
 +      unsigned long flags;
 +      /* IBSS can only be the IWL_RXON_CTX_BSS context */
 +      struct iwl_rxon_context *ctx = &priv->contexts[IWL_RXON_CTX_BSS];
 +
 +      if (WARN_ON(!priv->cfg->ops->legacy))
 +              return;
 +
 +      mutex_lock(&priv->mutex);
 +      IWL_DEBUG_MAC80211(priv, "enter\n");
 +
 +      spin_lock_irqsave(&priv->lock, flags);
 +      memset(&priv->current_ht_config, 0, sizeof(struct iwl_ht_config));
 +      spin_unlock_irqrestore(&priv->lock, flags);
 +
 +      spin_lock_irqsave(&priv->lock, flags);
 +
 +      /* new association get rid of ibss beacon skb */
 +      if (priv->beacon_skb)
 +              dev_kfree_skb(priv->beacon_skb);
 +
 +      priv->beacon_skb = NULL;
 +
 +      priv->timestamp = 0;
 +
 +      spin_unlock_irqrestore(&priv->lock, flags);
 +
 +      iwl_scan_cancel_timeout(priv, 100);
 +      if (!iwl_is_ready_rf(priv)) {
 +              IWL_DEBUG_MAC80211(priv, "leave - not ready\n");
 +              mutex_unlock(&priv->mutex);
 +              return;
 +      }
 +
 +      /* we are restarting association process
 +       * clear RXON_FILTER_ASSOC_MSK bit
 +       */
 +      ctx->staging.filter_flags &= ~RXON_FILTER_ASSOC_MSK;
 +      iwlcore_commit_rxon(priv, ctx);
 +
 +      iwl_set_rate(priv);
 +
 +      mutex_unlock(&priv->mutex);
 +
 +      IWL_DEBUG_MAC80211(priv, "leave\n");
 +}
 +EXPORT_SYMBOL(iwl_legacy_mac_reset_tsf);
 +
 +static void iwl_ht_conf(struct iwl_priv *priv,
 +                      struct ieee80211_vif *vif)
 +{
 +      struct iwl_ht_config *ht_conf = &priv->current_ht_config;
 +      struct ieee80211_sta *sta;
 +      struct ieee80211_bss_conf *bss_conf = &vif->bss_conf;
 +      struct iwl_rxon_context *ctx = iwl_rxon_ctx_from_vif(vif);
 +
 +      IWL_DEBUG_ASSOC(priv, "enter:\n");
 +
 +      if (!ctx->ht.enabled)
 +              return;
 +
 +      ctx->ht.protection =
 +              bss_conf->ht_operation_mode & IEEE80211_HT_OP_MODE_PROTECTION;
 +      ctx->ht.non_gf_sta_present =
 +              !!(bss_conf->ht_operation_mode & IEEE80211_HT_OP_MODE_NON_GF_STA_PRSNT);
 +
 +      ht_conf->single_chain_sufficient = false;
 +
 +      switch (vif->type) {
 +      case NL80211_IFTYPE_STATION:
 +              rcu_read_lock();
 +              sta = ieee80211_find_sta(vif, bss_conf->bssid);
 +              if (sta) {
 +                      struct ieee80211_sta_ht_cap *ht_cap = &sta->ht_cap;
 +                      int maxstreams;
 +
 +                      maxstreams = (ht_cap->mcs.tx_params &
 +                                    IEEE80211_HT_MCS_TX_MAX_STREAMS_MASK)
 +                                      >> IEEE80211_HT_MCS_TX_MAX_STREAMS_SHIFT;
 +                      maxstreams += 1;
 +
 +                      if ((ht_cap->mcs.rx_mask[1] == 0) &&
 +                          (ht_cap->mcs.rx_mask[2] == 0))
 +                              ht_conf->single_chain_sufficient = true;
 +                      if (maxstreams <= 1)
 +                              ht_conf->single_chain_sufficient = true;
 +              } else {
 +                      /*
 +                       * If at all, this can only happen through a race
 +                       * when the AP disconnects us while we're still
 +                       * setting up the connection, in that case mac80211
 +                       * will soon tell us about that.
 +                       */
 +                      ht_conf->single_chain_sufficient = true;
 +              }
 +              rcu_read_unlock();
 +              break;
 +      case NL80211_IFTYPE_ADHOC:
 +              ht_conf->single_chain_sufficient = true;
 +              break;
 +      default:
 +              break;
 +      }
 +
 +      IWL_DEBUG_ASSOC(priv, "leave\n");
 +}
 +
 +static inline void iwl_set_no_assoc(struct iwl_priv *priv,
 +                                  struct ieee80211_vif *vif)
 +{
 +      struct iwl_rxon_context *ctx = iwl_rxon_ctx_from_vif(vif);
 +
 +      iwl_led_disassociate(priv);
 +      /*
 +       * inform the ucode that there is no longer an
 +       * association and that no more packets should be
 +       * sent
 +       */
 +      ctx->staging.filter_flags &= ~RXON_FILTER_ASSOC_MSK;
 +      ctx->staging.assoc_id = 0;
 +      iwlcore_commit_rxon(priv, ctx);
 +}
 +
 +static void iwlcore_beacon_update(struct ieee80211_hw *hw,
 +                                struct ieee80211_vif *vif)
 +{
 +      struct iwl_priv *priv = hw->priv;
 +      unsigned long flags;
 +      __le64 timestamp;
 +      struct sk_buff *skb = ieee80211_beacon_get(hw, vif);
 +
 +      if (!skb)
 +              return;
 +
 +      IWL_DEBUG_MAC80211(priv, "enter\n");
 +
 +      lockdep_assert_held(&priv->mutex);
 +
 +      if (!priv->beacon_ctx) {
 +              IWL_ERR(priv, "update beacon but no beacon context!\n");
 +              dev_kfree_skb(skb);
 +              return;
 +      }
 +
 +      spin_lock_irqsave(&priv->lock, flags);
 +
 +      if (priv->beacon_skb)
 +              dev_kfree_skb(priv->beacon_skb);
 +
 +      priv->beacon_skb = skb;
 +
 +      timestamp = ((struct ieee80211_mgmt *)skb->data)->u.beacon.timestamp;
 +      priv->timestamp = le64_to_cpu(timestamp);
 +
 +      IWL_DEBUG_MAC80211(priv, "leave\n");
 +      spin_unlock_irqrestore(&priv->lock, flags);
 +
 +      if (!iwl_is_ready_rf(priv)) {
 +              IWL_DEBUG_MAC80211(priv, "leave - RF not ready\n");
 +              return;
 +      }
 +
 +      priv->cfg->ops->legacy->post_associate(priv);
 +}
 +
 +void iwl_legacy_mac_bss_info_changed(struct ieee80211_hw *hw,
 +                                   struct ieee80211_vif *vif,
 +                                   struct ieee80211_bss_conf *bss_conf,
 +                                   u32 changes)
 +{
 +      struct iwl_priv *priv = hw->priv;
 +      struct iwl_rxon_context *ctx = iwl_rxon_ctx_from_vif(vif);
 +      int ret;
 +
 +      if (WARN_ON(!priv->cfg->ops->legacy))
 +              return;
 +
 +      IWL_DEBUG_MAC80211(priv, "changes = 0x%X\n", changes);
 +
 +      if (!iwl_is_alive(priv))
 +              return;
 +
 +      mutex_lock(&priv->mutex);
 +
 +      if (changes & BSS_CHANGED_QOS) {
 +              unsigned long flags;
 +
 +              spin_lock_irqsave(&priv->lock, flags);
 +              ctx->qos_data.qos_active = bss_conf->qos;
 +              iwl_update_qos(priv, ctx);
 +              spin_unlock_irqrestore(&priv->lock, flags);
 +      }
 +
 +      if (changes & BSS_CHANGED_BEACON_ENABLED) {
 +              /*
 +               * the add_interface code must make sure we only ever
 +               * have a single interface that could be beaconing at
 +               * any time.
 +               */
 +              if (vif->bss_conf.enable_beacon)
 +                      priv->beacon_ctx = ctx;
 +              else
 +                      priv->beacon_ctx = NULL;
 +      }
 +
 +      if (changes & BSS_CHANGED_BEACON && vif->type == NL80211_IFTYPE_AP) {
 +              dev_kfree_skb(priv->beacon_skb);
 +              priv->beacon_skb = ieee80211_beacon_get(hw, vif);
 +      }
 +
 +      if (changes & BSS_CHANGED_BEACON_INT && vif->type == NL80211_IFTYPE_AP)
 +              iwl_send_rxon_timing(priv, ctx);
 +
 +      if (changes & BSS_CHANGED_BSSID) {
 +              IWL_DEBUG_MAC80211(priv, "BSSID %pM\n", bss_conf->bssid);
 +
 +              /*
 +               * If there is currently a HW scan going on in the
 +               * background then we need to cancel it else the RXON
 +               * below/in post_associate will fail.
 +               */
 +              if (iwl_scan_cancel_timeout(priv, 100)) {
 +                      IWL_WARN(priv, "Aborted scan still in progress after 100ms\n");
 +                      IWL_DEBUG_MAC80211(priv, "leaving - scan abort failed.\n");
 +                      mutex_unlock(&priv->mutex);
 +                      return;
 +              }
 +
 +              /* mac80211 only sets assoc when in STATION mode */
 +              if (vif->type == NL80211_IFTYPE_ADHOC || bss_conf->assoc) {
 +                      memcpy(ctx->staging.bssid_addr,
 +                             bss_conf->bssid, ETH_ALEN);
 +
 +                      /* currently needed in a few places */
 +                      memcpy(priv->bssid, bss_conf->bssid, ETH_ALEN);
 +              } else {
 +                      ctx->staging.filter_flags &=
 +                              ~RXON_FILTER_ASSOC_MSK;
 +              }
 +
 +      }
 +
 +      /*
 +       * This needs to be after setting the BSSID in case
 +       * mac80211 decides to do both changes at once because
 +       * it will invoke post_associate.
 +       */
 +      if (vif->type == NL80211_IFTYPE_ADHOC && changes & BSS_CHANGED_BEACON)
 +              iwlcore_beacon_update(hw, vif);
 +
 +      if (changes & BSS_CHANGED_ERP_PREAMBLE) {
 +              IWL_DEBUG_MAC80211(priv, "ERP_PREAMBLE %d\n",
 +                                 bss_conf->use_short_preamble);
 +              if (bss_conf->use_short_preamble)
 +                      ctx->staging.flags |= RXON_FLG_SHORT_PREAMBLE_MSK;
 +              else
 +                      ctx->staging.flags &= ~RXON_FLG_SHORT_PREAMBLE_MSK;
 +      }
 +
 +      if (changes & BSS_CHANGED_ERP_CTS_PROT) {
 +              IWL_DEBUG_MAC80211(priv, "ERP_CTS %d\n", bss_conf->use_cts_prot);
 +              if (bss_conf->use_cts_prot && (priv->band != IEEE80211_BAND_5GHZ))
 +                      ctx->staging.flags |= RXON_FLG_TGG_PROTECT_MSK;
 +              else
 +                      ctx->staging.flags &= ~RXON_FLG_TGG_PROTECT_MSK;
 +              if (bss_conf->use_cts_prot)
 +                      ctx->staging.flags |= RXON_FLG_SELF_CTS_EN;
 +              else
 +                      ctx->staging.flags &= ~RXON_FLG_SELF_CTS_EN;
 +      }
 +
 +      if (changes & BSS_CHANGED_BASIC_RATES) {
 +              /* XXX use this information
 +               *
 +               * To do that, remove code from iwl_set_rate() and put something
 +               * like this here:
 +               *
 +              if (A-band)
 +                      ctx->staging.ofdm_basic_rates =
 +                              bss_conf->basic_rates;
 +              else
 +                      ctx->staging.ofdm_basic_rates =
 +                              bss_conf->basic_rates >> 4;
 +                      ctx->staging.cck_basic_rates =
 +                              bss_conf->basic_rates & 0xF;
 +               */
 +      }
 +
 +      if (changes & BSS_CHANGED_HT) {
 +              iwl_ht_conf(priv, vif);
 +
 +              if (priv->cfg->ops->hcmd->set_rxon_chain)
 +                      priv->cfg->ops->hcmd->set_rxon_chain(priv, ctx);
 +      }
 +
 +      if (changes & BSS_CHANGED_ASSOC) {
 +              IWL_DEBUG_MAC80211(priv, "ASSOC %d\n", bss_conf->assoc);
 +              if (bss_conf->assoc) {
 +                      priv->timestamp = bss_conf->timestamp;
 +
 +                      iwl_led_associate(priv);
 +
 +                      if (!iwl_is_rfkill(priv))
 +                              priv->cfg->ops->legacy->post_associate(priv);
 +              } else
 +                      iwl_set_no_assoc(priv, vif);
 +      }
 +
 +      if (changes && iwl_is_associated_ctx(ctx) && bss_conf->aid) {
 +              IWL_DEBUG_MAC80211(priv, "Changes (%#x) while associated\n",
 +                                 changes);
 +              ret = iwl_send_rxon_assoc(priv, ctx);
 +              if (!ret) {
 +                      /* Sync active_rxon with latest change. */
 +                      memcpy((void *)&ctx->active,
 +                              &ctx->staging,
 +                              sizeof(struct iwl_rxon_cmd));
 +              }
 +      }
 +
 +      if (changes & BSS_CHANGED_BEACON_ENABLED) {
 +              if (vif->bss_conf.enable_beacon) {
 +                      memcpy(ctx->staging.bssid_addr,
 +                             bss_conf->bssid, ETH_ALEN);
 +                      memcpy(priv->bssid, bss_conf->bssid, ETH_ALEN);
 +                      iwl_led_associate(priv);
 +                      priv->cfg->ops->legacy->config_ap(priv);
 +              } else
 +                      iwl_set_no_assoc(priv, vif);
 +      }
 +
 +      if (changes & BSS_CHANGED_IBSS) {
 +              ret = priv->cfg->ops->legacy->manage_ibss_station(priv, vif,
 +                                                      bss_conf->ibss_joined);
 +              if (ret)
 +                      IWL_ERR(priv, "failed to %s IBSS station %pM\n",
 +                              bss_conf->ibss_joined ? "add" : "remove",
 +                              bss_conf->bssid);
 +      }
 +
 +      mutex_unlock(&priv->mutex);
 +
 +      IWL_DEBUG_MAC80211(priv, "leave\n");
 +}
 +EXPORT_SYMBOL(iwl_legacy_mac_bss_info_changed);
 +
 +irqreturn_t iwl_isr_legacy(int irq, void *data)
 +{
 +      struct iwl_priv *priv = data;
 +      u32 inta, inta_mask;
 +      u32 inta_fh;
 +      unsigned long flags;
 +      if (!priv)
 +              return IRQ_NONE;
 +
 +      spin_lock_irqsave(&priv->lock, flags);
 +
 +      /* Disable (but don't clear!) interrupts here to avoid
 +       *    back-to-back ISRs and sporadic interrupts from our NIC.
 +       * If we have something to service, the tasklet will re-enable ints.
 +       * If we *don't* have something, we'll re-enable before leaving here. */
 +      inta_mask = iwl_read32(priv, CSR_INT_MASK);  /* just for debug */
 +      iwl_write32(priv, CSR_INT_MASK, 0x00000000);
 +
 +      /* Discover which interrupts are active/pending */
 +      inta = iwl_read32(priv, CSR_INT);
 +      inta_fh = iwl_read32(priv, CSR_FH_INT_STATUS);
 +
 +      /* Ignore interrupt if there's nothing in NIC to service.
 +       * This may be due to IRQ shared with another device,
 +       * or due to sporadic interrupts thrown from our NIC. */
 +      if (!inta && !inta_fh) {
 +              IWL_DEBUG_ISR(priv,
 +                      "Ignore interrupt, inta == 0, inta_fh == 0\n");
 +              goto none;
 +      }
 +
 +      if ((inta == 0xFFFFFFFF) || ((inta & 0xFFFFFFF0) == 0xa5a5a5a0)) {
 +              /* Hardware disappeared. It might have already raised
 +               * an interrupt */
 +              IWL_WARN(priv, "HARDWARE GONE?? INTA == 0x%08x\n", inta);
 +              goto unplugged;
 +      }
 +
 +      IWL_DEBUG_ISR(priv, "ISR inta 0x%08x, enabled 0x%08x, fh 0x%08x\n",
 +                    inta, inta_mask, inta_fh);
 +
 +      inta &= ~CSR_INT_BIT_SCD;
 +
 +      /* iwl_irq_tasklet() will service interrupts and re-enable them */
 +      if (likely(inta || inta_fh))
 +              tasklet_schedule(&priv->irq_tasklet);
 +
 +unplugged:
 +      spin_unlock_irqrestore(&priv->lock, flags);
 +      return IRQ_HANDLED;
 +
 +none:
 +      /* re-enable interrupts here since we don't have anything to service. */
++      /* only Re-enable if disabled by irq */
 +      if (test_bit(STATUS_INT_ENABLED, &priv->status))
 +              iwl_enable_interrupts(priv);
 +      spin_unlock_irqrestore(&priv->lock, flags);
 +      return IRQ_NONE;
 +}
 +EXPORT_SYMBOL(iwl_isr_legacy);
 +
 +/*
 + *  iwl_legacy_tx_cmd_protection: Set rts/cts. 3945 and 4965 only share this
 + *  function.
 + */
 +void iwl_legacy_tx_cmd_protection(struct iwl_priv *priv,
 +                             struct ieee80211_tx_info *info,
 +                             __le16 fc, __le32 *tx_flags)
 +{
 +      if (info->control.rates[0].flags & IEEE80211_TX_RC_USE_RTS_CTS) {
 +              *tx_flags |= TX_CMD_FLG_RTS_MSK;
 +              *tx_flags &= ~TX_CMD_FLG_CTS_MSK;
 +              *tx_flags |= TX_CMD_FLG_FULL_TXOP_PROT_MSK;
 +
 +              if (!ieee80211_is_mgmt(fc))
 +                      return;
 +
 +              switch (fc & cpu_to_le16(IEEE80211_FCTL_STYPE)) {
 +              case cpu_to_le16(IEEE80211_STYPE_AUTH):
 +              case cpu_to_le16(IEEE80211_STYPE_DEAUTH):
 +              case cpu_to_le16(IEEE80211_STYPE_ASSOC_REQ):
 +              case cpu_to_le16(IEEE80211_STYPE_REASSOC_REQ):
 +                      *tx_flags &= ~TX_CMD_FLG_RTS_MSK;
 +                      *tx_flags |= TX_CMD_FLG_CTS_MSK;
 +                      break;
 +              }
 +      } else if (info->control.rates[0].flags &
 +                 IEEE80211_TX_RC_USE_CTS_PROTECT) {
 +              *tx_flags &= ~TX_CMD_FLG_RTS_MSK;
 +              *tx_flags |= TX_CMD_FLG_CTS_MSK;
 +              *tx_flags |= TX_CMD_FLG_FULL_TXOP_PROT_MSK;
 +      }
 +}
 +EXPORT_SYMBOL(iwl_legacy_tx_cmd_protection);
Simple merge
index 9cbc3f40c8dd2c4b6dfb6c0ae3b2f69698f1500d,0000000000000000000000000000000000000000..7bd8e4db4a71368f0fb756888124b9d28ea6a68c
mode 100644,000000..100644
--- /dev/null
@@@ -1,1190 -1,0 +1,1190 @@@
- /* Trace meassge on MBOX #A */
 +/*
 + * This file is part of wl1271
 + *
 + * Copyright (C) 1998-2009 Texas Instruments. All rights reserved.
 + * Copyright (C) 2008-2010 Nokia Corporation
 + *
 + * Contact: Luciano Coelho <luciano.coelho@nokia.com>
 + *
 + * This program is free software; you can redistribute it and/or
 + * modify it under the terms of the GNU General Public License
 + * version 2 as published by the Free Software Foundation.
 + *
 + * This program is distributed in the hope that it will be useful, but
 + * WITHOUT ANY WARRANTY; without even the implied warranty of
 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
 + * General Public License for more details.
 + *
 + * You should have received a copy of the GNU General Public License
 + * along with this program; if not, write to the Free Software
 + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
 + * 02110-1301 USA
 + *
 + */
 +
 +#ifndef __ACX_H__
 +#define __ACX_H__
 +
 +#include "wl12xx.h"
 +#include "cmd.h"
 +
 +/*************************************************************************
 +
 +    Host Interrupt Register (WiLink -> Host)
 +
 +**************************************************************************/
 +/* HW Initiated interrupt Watchdog timer expiration */
 +#define WL1271_ACX_INTR_WATCHDOG           BIT(0)
 +/* Init sequence is done (masked interrupt, detection through polling only ) */
 +#define WL1271_ACX_INTR_INIT_COMPLETE      BIT(1)
 +/* Event was entered to Event MBOX #A*/
 +#define WL1271_ACX_INTR_EVENT_A            BIT(2)
 +/* Event was entered to Event MBOX #B*/
 +#define WL1271_ACX_INTR_EVENT_B            BIT(3)
 +/* Command processing completion*/
 +#define WL1271_ACX_INTR_CMD_COMPLETE       BIT(4)
 +/* Signaling the host on HW wakeup */
 +#define WL1271_ACX_INTR_HW_AVAILABLE       BIT(5)
 +/* The MISC bit is used for aggregation of RX, TxComplete and TX rate update */
 +#define WL1271_ACX_INTR_DATA               BIT(6)
- /* Trace meassge on MBOX #B */
++/* Trace message on MBOX #A */
 +#define WL1271_ACX_INTR_TRACE_A            BIT(7)
++/* Trace message on MBOX #B */
 +#define WL1271_ACX_INTR_TRACE_B            BIT(8)
 +
 +#define WL1271_ACX_INTR_ALL              0xFFFFFFFF
 +#define WL1271_ACX_ALL_EVENTS_VECTOR       (WL1271_ACX_INTR_WATCHDOG      | \
 +                                          WL1271_ACX_INTR_INIT_COMPLETE | \
 +                                          WL1271_ACX_INTR_EVENT_A       | \
 +                                          WL1271_ACX_INTR_EVENT_B       | \
 +                                          WL1271_ACX_INTR_CMD_COMPLETE  | \
 +                                          WL1271_ACX_INTR_HW_AVAILABLE  | \
 +                                          WL1271_ACX_INTR_DATA)
 +
 +#define WL1271_INTR_MASK                   (WL1271_ACX_INTR_WATCHDOG     | \
 +                                          WL1271_ACX_INTR_EVENT_A      | \
 +                                          WL1271_ACX_INTR_EVENT_B      | \
 +                                          WL1271_ACX_INTR_HW_AVAILABLE | \
 +                                          WL1271_ACX_INTR_DATA)
 +
 +/* Target's information element */
 +struct acx_header {
 +      struct wl1271_cmd_header cmd;
 +
 +      /* acx (or information element) header */
 +      __le16 id;
 +
 +      /* payload length (not including headers */
 +      __le16 len;
 +} __packed;
 +
 +struct acx_error_counter {
 +      struct acx_header header;
 +
 +      /* The number of PLCP errors since the last time this */
 +      /* information element was interrogated. This field is */
 +      /* automatically cleared when it is interrogated.*/
 +      __le32 PLCP_error;
 +
 +      /* The number of FCS errors since the last time this */
 +      /* information element was interrogated. This field is */
 +      /* automatically cleared when it is interrogated.*/
 +      __le32 FCS_error;
 +
 +      /* The number of MPDUs without PLCP header errors received*/
 +      /* since the last time this information element was interrogated. */
 +      /* This field is automatically cleared when it is interrogated.*/
 +      __le32 valid_frame;
 +
 +      /* the number of missed sequence numbers in the squentially */
 +      /* values of frames seq numbers */
 +      __le32 seq_num_miss;
 +} __packed;
 +
 +enum wl1271_psm_mode {
 +      /* Active mode */
 +      WL1271_PSM_CAM = 0,
 +
 +      /* Power save mode */
 +      WL1271_PSM_PS = 1,
 +
 +      /* Extreme low power */
 +      WL1271_PSM_ELP = 2,
 +};
 +
 +struct acx_sleep_auth {
 +      struct acx_header header;
 +
 +      /* The sleep level authorization of the device. */
 +      /* 0 - Always active*/
 +      /* 1 - Power down mode: light / fast sleep*/
 +      /* 2 - ELP mode: Deep / Max sleep*/
 +      u8  sleep_auth;
 +      u8  padding[3];
 +} __packed;
 +
 +enum {
 +      HOSTIF_PCI_MASTER_HOST_INDIRECT,
 +      HOSTIF_PCI_MASTER_HOST_DIRECT,
 +      HOSTIF_SLAVE,
 +      HOSTIF_PKT_RING,
 +      HOSTIF_DONTCARE = 0xFF
 +};
 +
 +#define DEFAULT_UCAST_PRIORITY          0
 +#define DEFAULT_RX_Q_PRIORITY           0
 +#define DEFAULT_NUM_STATIONS            1
 +#define DEFAULT_RXQ_PRIORITY            0 /* low 0 .. 15 high  */
 +#define DEFAULT_RXQ_TYPE                0x07    /* All frames, Data/Ctrl/Mgmt */
 +#define TRACE_BUFFER_MAX_SIZE           256
 +
 +#define  DP_RX_PACKET_RING_CHUNK_SIZE 1600
 +#define  DP_TX_PACKET_RING_CHUNK_SIZE 1600
 +#define  DP_RX_PACKET_RING_CHUNK_NUM 2
 +#define  DP_TX_PACKET_RING_CHUNK_NUM 2
 +#define  DP_TX_COMPLETE_TIME_OUT 20
 +
 +#define TX_MSDU_LIFETIME_MIN       0
 +#define TX_MSDU_LIFETIME_MAX       3000
 +#define TX_MSDU_LIFETIME_DEF       512
 +#define RX_MSDU_LIFETIME_MIN       0
 +#define RX_MSDU_LIFETIME_MAX       0xFFFFFFFF
 +#define RX_MSDU_LIFETIME_DEF       512000
 +
 +struct acx_rx_msdu_lifetime {
 +      struct acx_header header;
 +
 +      /*
 +       * The maximum amount of time, in TU, before the
 +       * firmware discards the MSDU.
 +       */
 +      __le32 lifetime;
 +} __packed;
 +
 +/*
 + * RX Config Options Table
 + * Bit                Definition
 + * ===                ==========
 + * 31:14              Reserved
 + * 13         Copy RX Status - when set, write three receive status words
 + *            to top of rx'd MPDUs.
 + *            When cleared, do not write three status words (added rev 1.5)
 + * 12         Reserved
 + * 11         RX Complete upon FCS error - when set, give rx complete
 + *            interrupt for FCS errors, after the rx filtering, e.g. unicast
 + *            frames not to us with FCS error will not generate an interrupt.
 + * 10         SSID Filter Enable - When set, the WiLink discards all beacon,
 + *            probe request, and probe response frames with an SSID that does
 + *            not match the SSID specified by the host in the START/JOIN
 + *            command.
 + *            When clear, the WiLink receives frames with any SSID.
 + * 9          Broadcast Filter Enable - When set, the WiLink discards all
 + *            broadcast frames. When clear, the WiLink receives all received
 + *            broadcast frames.
 + * 8:6                Reserved
 + * 5          BSSID Filter Enable - When set, the WiLink discards any frames
 + *            with a BSSID that does not match the BSSID specified by the
 + *            host.
 + *            When clear, the WiLink receives frames from any BSSID.
 + * 4          MAC Addr Filter - When set, the WiLink discards any frames
 + *            with a destination address that does not match the MAC address
 + *            of the adaptor.
 + *            When clear, the WiLink receives frames destined to any MAC
 + *            address.
 + * 3          Promiscuous - When set, the WiLink receives all valid frames
 + *            (i.e., all frames that pass the FCS check).
 + *            When clear, only frames that pass the other filters specified
 + *            are received.
 + * 2          FCS - When set, the WiLink includes the FCS with the received
 + *            frame.
 + *            When cleared, the FCS is discarded.
 + * 1          PLCP header - When set, write all data from baseband to frame
 + *            buffer including PHY header.
 + * 0          Reserved - Always equal to 0.
 + *
 + * RX Filter Options Table
 + * Bit                Definition
 + * ===                ==========
 + * 31:12              Reserved - Always equal to 0.
 + * 11         Association - When set, the WiLink receives all association
 + *            related frames (association request/response, reassocation
 + *            request/response, and disassociation). When clear, these frames
 + *            are discarded.
 + * 10         Auth/De auth - When set, the WiLink receives all authentication
 + *            and de-authentication frames. When clear, these frames are
 + *            discarded.
 + * 9          Beacon - When set, the WiLink receives all beacon frames.
 + *            When clear, these frames are discarded.
 + * 8          Contention Free - When set, the WiLink receives all contention
 + *            free frames.
 + *            When clear, these frames are discarded.
 + * 7          Control - When set, the WiLink receives all control frames.
 + *            When clear, these frames are discarded.
 + * 6          Data - When set, the WiLink receives all data frames.
 + *            When clear, these frames are discarded.
 + * 5          FCS Error - When set, the WiLink receives frames that have FCS
 + *            errors.
 + *            When clear, these frames are discarded.
 + * 4          Management - When set, the WiLink receives all management
 + *            frames.
 + *            When clear, these frames are discarded.
 + * 3          Probe Request - When set, the WiLink receives all probe request
 + *            frames.
 + *            When clear, these frames are discarded.
 + * 2          Probe Response - When set, the WiLink receives all probe
 + *            response frames.
 + *            When clear, these frames are discarded.
 + * 1          RTS/CTS/ACK - When set, the WiLink receives all RTS, CTS and ACK
 + *            frames.
 + *            When clear, these frames are discarded.
 + * 0          Rsvd Type/Sub Type - When set, the WiLink receives all frames
 + *            that have reserved frame types and sub types as defined by the
 + *            802.11 specification.
 + *            When clear, these frames are discarded.
 + */
 +struct acx_rx_config {
 +      struct acx_header header;
 +
 +      __le32 config_options;
 +      __le32 filter_options;
 +} __packed;
 +
 +struct acx_packet_detection {
 +      struct acx_header header;
 +
 +      __le32 threshold;
 +} __packed;
 +
 +
 +enum acx_slot_type {
 +      SLOT_TIME_LONG = 0,
 +      SLOT_TIME_SHORT = 1,
 +      DEFAULT_SLOT_TIME = SLOT_TIME_SHORT,
 +      MAX_SLOT_TIMES = 0xFF
 +};
 +
 +#define STATION_WONE_INDEX 0
 +
 +struct acx_slot {
 +      struct acx_header header;
 +
 +      u8 wone_index; /* Reserved */
 +      u8 slot_time;
 +      u8 reserved[6];
 +} __packed;
 +
 +
 +#define ACX_MC_ADDRESS_GROUP_MAX      (8)
 +#define ADDRESS_GROUP_MAX_LEN         (ETH_ALEN * ACX_MC_ADDRESS_GROUP_MAX)
 +
 +struct acx_dot11_grp_addr_tbl {
 +      struct acx_header header;
 +
 +      u8 enabled;
 +      u8 num_groups;
 +      u8 pad[2];
 +      u8 mac_table[ADDRESS_GROUP_MAX_LEN];
 +} __packed;
 +
 +struct acx_rx_timeout {
 +      struct acx_header header;
 +
 +      __le16 ps_poll_timeout;
 +      __le16 upsd_timeout;
 +} __packed;
 +
 +struct acx_rts_threshold {
 +      struct acx_header header;
 +
 +      __le16 threshold;
 +      u8 pad[2];
 +} __packed;
 +
 +struct acx_beacon_filter_option {
 +      struct acx_header header;
 +
 +      u8 enable;
 +
 +      /*
 +       * The number of beacons without the unicast TIM
 +       * bit set that the firmware buffers before
 +       * signaling the host about ready frames.
 +       * When set to 0 and the filter is enabled, beacons
 +       * without the unicast TIM bit set are dropped.
 +       */
 +      u8 max_num_beacons;
 +      u8 pad[2];
 +} __packed;
 +
 +/*
 + * ACXBeaconFilterEntry (not 221)
 + * Byte Offset     Size (Bytes)    Definition
 + * ===========     ============    ==========
 + * 0               1               IE identifier
 + * 1               1               Treatment bit mask
 + *
 + * ACXBeaconFilterEntry (221)
 + * Byte Offset     Size (Bytes)    Definition
 + * ===========     ============    ==========
 + * 0               1               IE identifier
 + * 1               1               Treatment bit mask
 + * 2               3               OUI
 + * 5               1               Type
 + * 6               2               Version
 + *
 + *
 + * Treatment bit mask - The information element handling:
 + * bit 0 - The information element is compared and transferred
 + * in case of change.
 + * bit 1 - The information element is transferred to the host
 + * with each appearance or disappearance.
 + * Note that both bits can be set at the same time.
 + */
 +#define       BEACON_FILTER_TABLE_MAX_IE_NUM                 (32)
 +#define BEACON_FILTER_TABLE_MAX_VENDOR_SPECIFIC_IE_NUM (6)
 +#define BEACON_FILTER_TABLE_IE_ENTRY_SIZE            (2)
 +#define BEACON_FILTER_TABLE_EXTRA_VENDOR_SPECIFIC_IE_SIZE (6)
 +#define BEACON_FILTER_TABLE_MAX_SIZE ((BEACON_FILTER_TABLE_MAX_IE_NUM * \
 +                          BEACON_FILTER_TABLE_IE_ENTRY_SIZE) + \
 +                         (BEACON_FILTER_TABLE_MAX_VENDOR_SPECIFIC_IE_NUM * \
 +                          BEACON_FILTER_TABLE_EXTRA_VENDOR_SPECIFIC_IE_SIZE))
 +
 +struct acx_beacon_filter_ie_table {
 +      struct acx_header header;
 +
 +      u8 num_ie;
 +      u8 pad[3];
 +      u8 table[BEACON_FILTER_TABLE_MAX_SIZE];
 +} __packed;
 +
 +struct acx_conn_monit_params {
 +       struct acx_header header;
 +
 +       __le32 synch_fail_thold; /* number of beacons missed */
 +       __le32 bss_lose_timeout; /* number of TU's from synch fail */
 +} __packed;
 +
 +struct acx_bt_wlan_coex {
 +      struct acx_header header;
 +
 +      u8 enable;
 +      u8 pad[3];
 +} __packed;
 +
 +struct acx_bt_wlan_coex_param {
 +      struct acx_header header;
 +
 +      __le32 params[CONF_SG_PARAMS_MAX];
 +      u8 param_idx;
 +      u8 padding[3];
 +} __packed;
 +
 +struct acx_dco_itrim_params {
 +      struct acx_header header;
 +
 +      u8 enable;
 +      u8 padding[3];
 +      __le32 timeout;
 +} __packed;
 +
 +struct acx_energy_detection {
 +      struct acx_header header;
 +
 +      /* The RX Clear Channel Assessment threshold in the PHY */
 +      __le16 rx_cca_threshold;
 +      u8 tx_energy_detection;
 +      u8 pad;
 +} __packed;
 +
 +struct acx_beacon_broadcast {
 +      struct acx_header header;
 +
 +      __le16 beacon_rx_timeout;
 +      __le16 broadcast_timeout;
 +
 +      /* Enables receiving of broadcast packets in PS mode */
 +      u8 rx_broadcast_in_ps;
 +
 +      /* Consecutive PS Poll failures before updating the host */
 +      u8 ps_poll_threshold;
 +      u8 pad[2];
 +} __packed;
 +
 +struct acx_event_mask {
 +      struct acx_header header;
 +
 +      __le32 event_mask;
 +      __le32 high_event_mask; /* Unused */
 +} __packed;
 +
 +#define CFG_RX_FCS            BIT(2)
 +#define CFG_RX_ALL_GOOD               BIT(3)
 +#define CFG_UNI_FILTER_EN     BIT(4)
 +#define CFG_BSSID_FILTER_EN   BIT(5)
 +#define CFG_MC_FILTER_EN      BIT(6)
 +#define CFG_MC_ADDR0_EN               BIT(7)
 +#define CFG_MC_ADDR1_EN               BIT(8)
 +#define CFG_BC_REJECT_EN      BIT(9)
 +#define CFG_SSID_FILTER_EN    BIT(10)
 +#define CFG_RX_INT_FCS_ERROR  BIT(11)
 +#define CFG_RX_INT_ENCRYPTED  BIT(12)
 +#define CFG_RX_WR_RX_STATUS   BIT(13)
 +#define CFG_RX_FILTER_NULTI   BIT(14)
 +#define CFG_RX_RESERVE                BIT(15)
 +#define CFG_RX_TIMESTAMP_TSF  BIT(16)
 +
 +#define CFG_RX_RSV_EN         BIT(0)
 +#define CFG_RX_RCTS_ACK               BIT(1)
 +#define CFG_RX_PRSP_EN                BIT(2)
 +#define CFG_RX_PREQ_EN                BIT(3)
 +#define CFG_RX_MGMT_EN                BIT(4)
 +#define CFG_RX_FCS_ERROR      BIT(5)
 +#define CFG_RX_DATA_EN                BIT(6)
 +#define CFG_RX_CTL_EN         BIT(7)
 +#define CFG_RX_CF_EN          BIT(8)
 +#define CFG_RX_BCN_EN         BIT(9)
 +#define CFG_RX_AUTH_EN                BIT(10)
 +#define CFG_RX_ASSOC_EN               BIT(11)
 +
 +#define SCAN_PASSIVE          BIT(0)
 +#define SCAN_5GHZ_BAND                BIT(1)
 +#define SCAN_TRIGGERED                BIT(2)
 +#define SCAN_PRIORITY_HIGH    BIT(3)
 +
 +/* When set, disable HW encryption */
 +#define DF_ENCRYPTION_DISABLE      0x01
 +#define DF_SNIFF_MODE_ENABLE       0x80
 +
 +struct acx_feature_config {
 +      struct acx_header header;
 +
 +      __le32 options;
 +      __le32 data_flow_options;
 +} __packed;
 +
 +struct acx_current_tx_power {
 +      struct acx_header header;
 +
 +      u8  current_tx_power;
 +      u8  padding[3];
 +} __packed;
 +
 +struct acx_wake_up_condition {
 +      struct acx_header header;
 +
 +      u8 wake_up_event; /* Only one bit can be set */
 +      u8 listen_interval;
 +      u8 pad[2];
 +} __packed;
 +
 +struct acx_aid {
 +      struct acx_header header;
 +
 +      /*
 +       * To be set when associated with an AP.
 +       */
 +      __le16 aid;
 +      u8 pad[2];
 +} __packed;
 +
 +enum acx_preamble_type {
 +      ACX_PREAMBLE_LONG = 0,
 +      ACX_PREAMBLE_SHORT = 1
 +};
 +
 +struct acx_preamble {
 +      struct acx_header header;
 +
 +      /*
 +       * When set, the WiLink transmits the frames with a short preamble and
 +       * when cleared, the WiLink transmits the frames with a long preamble.
 +       */
 +      u8 preamble;
 +      u8 padding[3];
 +} __packed;
 +
 +enum acx_ctsprotect_type {
 +      CTSPROTECT_DISABLE = 0,
 +      CTSPROTECT_ENABLE = 1
 +};
 +
 +struct acx_ctsprotect {
 +      struct acx_header header;
 +      u8 ctsprotect;
 +      u8 padding[3];
 +} __packed;
 +
 +struct acx_tx_statistics {
 +      __le32 internal_desc_overflow;
 +}  __packed;
 +
 +struct acx_rx_statistics {
 +      __le32 out_of_mem;
 +      __le32 hdr_overflow;
 +      __le32 hw_stuck;
 +      __le32 dropped;
 +      __le32 fcs_err;
 +      __le32 xfr_hint_trig;
 +      __le32 path_reset;
 +      __le32 reset_counter;
 +} __packed;
 +
 +struct acx_dma_statistics {
 +      __le32 rx_requested;
 +      __le32 rx_errors;
 +      __le32 tx_requested;
 +      __le32 tx_errors;
 +}  __packed;
 +
 +struct acx_isr_statistics {
 +      /* host command complete */
 +      __le32 cmd_cmplt;
 +
 +      /* fiqisr() */
 +      __le32 fiqs;
 +
 +      /* (INT_STS_ND & INT_TRIG_RX_HEADER) */
 +      __le32 rx_headers;
 +
 +      /* (INT_STS_ND & INT_TRIG_RX_CMPLT) */
 +      __le32 rx_completes;
 +
 +      /* (INT_STS_ND & INT_TRIG_NO_RX_BUF) */
 +      __le32 rx_mem_overflow;
 +
 +      /* (INT_STS_ND & INT_TRIG_S_RX_RDY) */
 +      __le32 rx_rdys;
 +
 +      /* irqisr() */
 +      __le32 irqs;
 +
 +      /* (INT_STS_ND & INT_TRIG_TX_PROC) */
 +      __le32 tx_procs;
 +
 +      /* (INT_STS_ND & INT_TRIG_DECRYPT_DONE) */
 +      __le32 decrypt_done;
 +
 +      /* (INT_STS_ND & INT_TRIG_DMA0) */
 +      __le32 dma0_done;
 +
 +      /* (INT_STS_ND & INT_TRIG_DMA1) */
 +      __le32 dma1_done;
 +
 +      /* (INT_STS_ND & INT_TRIG_TX_EXC_CMPLT) */
 +      __le32 tx_exch_complete;
 +
 +      /* (INT_STS_ND & INT_TRIG_COMMAND) */
 +      __le32 commands;
 +
 +      /* (INT_STS_ND & INT_TRIG_RX_PROC) */
 +      __le32 rx_procs;
 +
 +      /* (INT_STS_ND & INT_TRIG_PM_802) */
 +      __le32 hw_pm_mode_changes;
 +
 +      /* (INT_STS_ND & INT_TRIG_ACKNOWLEDGE) */
 +      __le32 host_acknowledges;
 +
 +      /* (INT_STS_ND & INT_TRIG_PM_PCI) */
 +      __le32 pci_pm;
 +
 +      /* (INT_STS_ND & INT_TRIG_ACM_WAKEUP) */
 +      __le32 wakeups;
 +
 +      /* (INT_STS_ND & INT_TRIG_LOW_RSSI) */
 +      __le32 low_rssi;
 +} __packed;
 +
 +struct acx_wep_statistics {
 +      /* WEP address keys configured */
 +      __le32 addr_key_count;
 +
 +      /* default keys configured */
 +      __le32 default_key_count;
 +
 +      __le32 reserved;
 +
 +      /* number of times that WEP key not found on lookup */
 +      __le32 key_not_found;
 +
 +      /* number of times that WEP key decryption failed */
 +      __le32 decrypt_fail;
 +
 +      /* WEP packets decrypted */
 +      __le32 packets;
 +
 +      /* WEP decrypt interrupts */
 +      __le32 interrupt;
 +} __packed;
 +
 +#define ACX_MISSED_BEACONS_SPREAD 10
 +
 +struct acx_pwr_statistics {
 +      /* the amount of enters into power save mode (both PD & ELP) */
 +      __le32 ps_enter;
 +
 +      /* the amount of enters into ELP mode */
 +      __le32 elp_enter;
 +
 +      /* the amount of missing beacon interrupts to the host */
 +      __le32 missing_bcns;
 +
 +      /* the amount of wake on host-access times */
 +      __le32 wake_on_host;
 +
 +      /* the amount of wake on timer-expire */
 +      __le32 wake_on_timer_exp;
 +
 +      /* the number of packets that were transmitted with PS bit set */
 +      __le32 tx_with_ps;
 +
 +      /* the number of packets that were transmitted with PS bit clear */
 +      __le32 tx_without_ps;
 +
 +      /* the number of received beacons */
 +      __le32 rcvd_beacons;
 +
 +      /* the number of entering into PowerOn (power save off) */
 +      __le32 power_save_off;
 +
 +      /* the number of entries into power save mode */
 +      __le16 enable_ps;
 +
 +      /*
 +       * the number of exits from power save, not including failed PS
 +       * transitions
 +       */
 +      __le16 disable_ps;
 +
 +      /*
 +       * the number of times the TSF counter was adjusted because
 +       * of drift
 +       */
 +      __le32 fix_tsf_ps;
 +
 +      /* Gives statistics about the spread continuous missed beacons.
 +       * The 16 LSB are dedicated for the PS mode.
 +       * The 16 MSB are dedicated for the PS mode.
 +       * cont_miss_bcns_spread[0] - single missed beacon.
 +       * cont_miss_bcns_spread[1] - two continuous missed beacons.
 +       * cont_miss_bcns_spread[2] - three continuous missed beacons.
 +       * ...
 +       * cont_miss_bcns_spread[9] - ten and more continuous missed beacons.
 +      */
 +      __le32 cont_miss_bcns_spread[ACX_MISSED_BEACONS_SPREAD];
 +
 +      /* the number of beacons in awake mode */
 +      __le32 rcvd_awake_beacons;
 +} __packed;
 +
 +struct acx_mic_statistics {
 +      __le32 rx_pkts;
 +      __le32 calc_failure;
 +} __packed;
 +
 +struct acx_aes_statistics {
 +      __le32 encrypt_fail;
 +      __le32 decrypt_fail;
 +      __le32 encrypt_packets;
 +      __le32 decrypt_packets;
 +      __le32 encrypt_interrupt;
 +      __le32 decrypt_interrupt;
 +} __packed;
 +
 +struct acx_event_statistics {
 +      __le32 heart_beat;
 +      __le32 calibration;
 +      __le32 rx_mismatch;
 +      __le32 rx_mem_empty;
 +      __le32 rx_pool;
 +      __le32 oom_late;
 +      __le32 phy_transmit_error;
 +      __le32 tx_stuck;
 +} __packed;
 +
 +struct acx_ps_statistics {
 +      __le32 pspoll_timeouts;
 +      __le32 upsd_timeouts;
 +      __le32 upsd_max_sptime;
 +      __le32 upsd_max_apturn;
 +      __le32 pspoll_max_apturn;
 +      __le32 pspoll_utilization;
 +      __le32 upsd_utilization;
 +} __packed;
 +
 +struct acx_rxpipe_statistics {
 +      __le32 rx_prep_beacon_drop;
 +      __le32 descr_host_int_trig_rx_data;
 +      __le32 beacon_buffer_thres_host_int_trig_rx_data;
 +      __le32 missed_beacon_host_int_trig_rx_data;
 +      __le32 tx_xfr_host_int_trig_rx_data;
 +} __packed;
 +
 +struct acx_statistics {
 +      struct acx_header header;
 +
 +      struct acx_tx_statistics tx;
 +      struct acx_rx_statistics rx;
 +      struct acx_dma_statistics dma;
 +      struct acx_isr_statistics isr;
 +      struct acx_wep_statistics wep;
 +      struct acx_pwr_statistics pwr;
 +      struct acx_aes_statistics aes;
 +      struct acx_mic_statistics mic;
 +      struct acx_event_statistics event;
 +      struct acx_ps_statistics ps;
 +      struct acx_rxpipe_statistics rxpipe;
 +} __packed;
 +
 +struct acx_rate_class {
 +      __le32 enabled_rates;
 +      u8 short_retry_limit;
 +      u8 long_retry_limit;
 +      u8 aflags;
 +      u8 reserved;
 +};
 +
 +#define ACX_TX_BASIC_RATE      0
 +#define ACX_TX_AP_FULL_RATE    1
 +#define ACX_TX_RATE_POLICY_CNT 2
 +struct acx_rate_policy {
 +      struct acx_header header;
 +
 +      __le32 rate_class_cnt;
 +      struct acx_rate_class rate_class[CONF_TX_MAX_RATE_CLASSES];
 +} __packed;
 +
 +struct acx_ac_cfg {
 +      struct acx_header header;
 +      u8 ac;
 +      u8 cw_min;
 +      __le16 cw_max;
 +      u8 aifsn;
 +      u8 reserved;
 +      __le16 tx_op_limit;
 +} __packed;
 +
 +struct acx_tid_config {
 +      struct acx_header header;
 +      u8 queue_id;
 +      u8 channel_type;
 +      u8 tsid;
 +      u8 ps_scheme;
 +      u8 ack_policy;
 +      u8 padding[3];
 +      __le32 apsd_conf[2];
 +} __packed;
 +
 +struct acx_frag_threshold {
 +      struct acx_header header;
 +      __le16 frag_threshold;
 +      u8 padding[2];
 +} __packed;
 +
 +struct acx_tx_config_options {
 +      struct acx_header header;
 +      __le16 tx_compl_timeout;     /* msec */
 +      __le16 tx_compl_threshold;   /* number of packets */
 +} __packed;
 +
 +#define ACX_RX_MEM_BLOCKS     70
 +#define ACX_TX_MIN_MEM_BLOCKS 40
 +#define ACX_TX_DESCRIPTORS    32
 +#define ACX_NUM_SSID_PROFILES 1
 +
 +struct wl1271_acx_config_memory {
 +      struct acx_header header;
 +
 +      u8 rx_mem_block_num;
 +      u8 tx_min_mem_block_num;
 +      u8 num_stations;
 +      u8 num_ssid_profiles;
 +      __le32 total_tx_descriptors;
 +} __packed;
 +
 +struct wl1271_acx_mem_map {
 +      struct acx_header header;
 +
 +      __le32 code_start;
 +      __le32 code_end;
 +
 +      __le32 wep_defkey_start;
 +      __le32 wep_defkey_end;
 +
 +      __le32 sta_table_start;
 +      __le32 sta_table_end;
 +
 +      __le32 packet_template_start;
 +      __le32 packet_template_end;
 +
 +      /* Address of the TX result interface (control block) */
 +      __le32 tx_result;
 +      __le32 tx_result_queue_start;
 +
 +      __le32 queue_memory_start;
 +      __le32 queue_memory_end;
 +
 +      __le32 packet_memory_pool_start;
 +      __le32 packet_memory_pool_end;
 +
 +      __le32 debug_buffer1_start;
 +      __le32 debug_buffer1_end;
 +
 +      __le32 debug_buffer2_start;
 +      __le32 debug_buffer2_end;
 +
 +      /* Number of blocks FW allocated for TX packets */
 +      __le32 num_tx_mem_blocks;
 +
 +      /* Number of blocks FW allocated for RX packets */
 +      __le32 num_rx_mem_blocks;
 +
 +      /* the following 4 fields are valid in SLAVE mode only */
 +      u8 *tx_cbuf;
 +      u8 *rx_cbuf;
 +      __le32 rx_ctrl;
 +      __le32 tx_ctrl;
 +} __packed;
 +
 +struct wl1271_acx_rx_config_opt {
 +      struct acx_header header;
 +
 +      __le16 mblk_threshold;
 +      __le16 threshold;
 +      __le16 timeout;
 +      u8 queue_type;
 +      u8 reserved;
 +} __packed;
 +
 +
 +struct wl1271_acx_bet_enable {
 +      struct acx_header header;
 +
 +      u8 enable;
 +      u8 max_consecutive;
 +      u8 padding[2];
 +} __packed;
 +
 +#define ACX_IPV4_VERSION 4
 +#define ACX_IPV6_VERSION 6
 +#define ACX_IPV4_ADDR_SIZE 4
 +
 +/* bitmap of enabled arp_filter features */
 +#define ACX_ARP_FILTER_ARP_FILTERING  BIT(0)
 +#define ACX_ARP_FILTER_AUTO_ARP               BIT(1)
 +
 +struct wl1271_acx_arp_filter {
 +      struct acx_header header;
 +      u8 version;         /* ACX_IPV4_VERSION, ACX_IPV6_VERSION */
 +      u8 enable;          /* bitmap of enabled ARP filtering features */
 +      u8 padding[2];
 +      u8 address[16];     /* The configured device IP address - all ARP
 +                             requests directed to this IP address will pass
 +                             through. For IPv4, the first four bytes are
 +                             used. */
 +} __packed;
 +
 +struct wl1271_acx_pm_config {
 +      struct acx_header header;
 +
 +      __le32 host_clk_settling_time;
 +      u8 host_fast_wakeup_support;
 +      u8 padding[3];
 +} __packed;
 +
 +struct wl1271_acx_keep_alive_mode {
 +      struct acx_header header;
 +
 +      u8 enabled;
 +      u8 padding[3];
 +} __packed;
 +
 +enum {
 +      ACX_KEEP_ALIVE_NO_TX = 0,
 +      ACX_KEEP_ALIVE_PERIOD_ONLY
 +};
 +
 +enum {
 +      ACX_KEEP_ALIVE_TPL_INVALID = 0,
 +      ACX_KEEP_ALIVE_TPL_VALID
 +};
 +
 +struct wl1271_acx_keep_alive_config {
 +      struct acx_header header;
 +
 +      __le32 period;
 +      u8 index;
 +      u8 tpl_validation;
 +      u8 trigger;
 +      u8 padding;
 +} __packed;
 +
 +enum {
 +      WL1271_ACX_TRIG_TYPE_LEVEL = 0,
 +      WL1271_ACX_TRIG_TYPE_EDGE,
 +};
 +
 +enum {
 +      WL1271_ACX_TRIG_DIR_LOW = 0,
 +      WL1271_ACX_TRIG_DIR_HIGH,
 +      WL1271_ACX_TRIG_DIR_BIDIR,
 +};
 +
 +enum {
 +      WL1271_ACX_TRIG_ENABLE = 1,
 +      WL1271_ACX_TRIG_DISABLE,
 +};
 +
 +enum {
 +      WL1271_ACX_TRIG_METRIC_RSSI_BEACON = 0,
 +      WL1271_ACX_TRIG_METRIC_RSSI_DATA,
 +      WL1271_ACX_TRIG_METRIC_SNR_BEACON,
 +      WL1271_ACX_TRIG_METRIC_SNR_DATA,
 +};
 +
 +enum {
 +      WL1271_ACX_TRIG_IDX_RSSI = 0,
 +      WL1271_ACX_TRIG_COUNT = 8,
 +};
 +
 +struct wl1271_acx_rssi_snr_trigger {
 +      struct acx_header header;
 +
 +      __le16 threshold;
 +      __le16 pacing; /* 0 - 60000 ms */
 +      u8 metric;
 +      u8 type;
 +      u8 dir;
 +      u8 hysteresis;
 +      u8 index;
 +      u8 enable;
 +      u8 padding[2];
 +};
 +
 +struct wl1271_acx_rssi_snr_avg_weights {
 +      struct acx_header header;
 +
 +      u8 rssi_beacon;
 +      u8 rssi_data;
 +      u8 snr_beacon;
 +      u8 snr_data;
 +};
 +
 +/*
 + * ACX_PEER_HT_CAP
 + * Configure HT capabilities - declare the capabilities of the peer
 + * we are connected to.
 + */
 +struct wl1271_acx_ht_capabilities {
 +      struct acx_header header;
 +
 +      /*
 +       * bit 0 - Allow HT Operation
 +       * bit 1 - Allow Greenfield format in TX
 +       * bit 2 - Allow Short GI in TX
 +       * bit 3 - Allow L-SIG TXOP Protection in TX
 +       * bit 4 - Allow HT Control fields in TX.
 +       *         Note, driver will still leave space for HT control in packets
 +       *         regardless of the value of this field. FW will be responsible
 +       *         to drop the HT field from any frame when this Bit set to 0.
 +       * bit 5 - Allow RD initiation in TXOP. FW is allowed to initate RD.
 +       *         Exact policy setting for this feature is TBD.
 +       *         Note, this bit can only be set to 1 if bit 3 is set to 1.
 +       */
 +      __le32 ht_capabilites;
 +
 +      /*
 +       * Indicates to which peer these capabilities apply.
 +       * For infrastructure use ff:ff:ff:ff:ff:ff that indicates relevance
 +       * for all peers.
 +       * Only valid for IBSS/DLS operation.
 +       */
 +      u8 mac_address[ETH_ALEN];
 +
 +      /*
 +       * This the maximum A-MPDU length supported by the AP. The FW may not
 +       * exceed this length when sending A-MPDUs
 +       */
 +      u8 ampdu_max_length;
 +
 +      /* This is the minimal spacing required when sending A-MPDUs to the AP*/
 +      u8 ampdu_min_spacing;
 +} __packed;
 +
 +/* HT Capabilites Fw Bit Mask Mapping */
 +#define WL1271_ACX_FW_CAP_HT_OPERATION                 BIT(0)
 +#define WL1271_ACX_FW_CAP_GREENFIELD_FRAME_FORMAT      BIT(1)
 +#define WL1271_ACX_FW_CAP_SHORT_GI_FOR_20MHZ_PACKETS   BIT(2)
 +#define WL1271_ACX_FW_CAP_LSIG_TXOP_PROTECTION         BIT(3)
 +#define WL1271_ACX_FW_CAP_HT_CONTROL_FIELDS            BIT(4)
 +#define WL1271_ACX_FW_CAP_RD_INITIATION                BIT(5)
 +
 +
 +/*
 + * ACX_HT_BSS_OPERATION
 + * Configure HT capabilities - AP rules for behavior in the BSS.
 + */
 +struct wl1271_acx_ht_information {
 +      struct acx_header header;
 +
 +      /* Values: 0 - RIFS not allowed, 1 - RIFS allowed */
 +      u8 rifs_mode;
 +
 +      /* Values: 0 - 3 like in spec */
 +      u8 ht_protection;
 +
 +      /* Values: 0 - GF protection not required, 1 - GF protection required */
 +      u8 gf_protection;
 +
 +      /*Values: 0 - TX Burst limit not required, 1 - TX Burst Limit required*/
 +      u8 ht_tx_burst_limit;
 +
 +      /*
 +       * Values: 0 - Dual CTS protection not required,
 +       *         1 - Dual CTS Protection required
 +       * Note: When this value is set to 1 FW will protect all TXOP with RTS
 +       * frame and will not use CTS-to-self regardless of the value of the
 +       * ACX_CTS_PROTECTION information element
 +       */
 +      u8 dual_cts_protection;
 +
 +      u8 padding[3];
 +} __packed;
 +
 +struct wl1271_acx_fw_tsf_information {
 +      struct acx_header header;
 +
 +      __le32 current_tsf_high;
 +      __le32 current_tsf_low;
 +      __le32 last_bttt_high;
 +      __le32 last_tbtt_low;
 +      u8 last_dtim_count;
 +      u8 padding[3];
 +} __packed;
 +
 +enum {
 +      ACX_WAKE_UP_CONDITIONS      = 0x0002,
 +      ACX_MEM_CFG                 = 0x0003,
 +      ACX_SLOT                    = 0x0004,
 +      ACX_AC_CFG                  = 0x0007,
 +      ACX_MEM_MAP                 = 0x0008,
 +      ACX_AID                     = 0x000A,
 +      /* ACX_FW_REV is missing in the ref driver, but seems to work */
 +      ACX_FW_REV                  = 0x000D,
 +      ACX_MEDIUM_USAGE            = 0x000F,
 +      ACX_RX_CFG                  = 0x0010,
 +      ACX_TX_QUEUE_CFG            = 0x0011, /* FIXME: only used by wl1251 */
 +      ACX_STATISTICS              = 0x0013, /* Debug API */
 +      ACX_PWR_CONSUMPTION_STATISTICS = 0x0014,
 +      ACX_FEATURE_CFG             = 0x0015,
 +      ACX_TID_CFG                 = 0x001A,
 +      ACX_PS_RX_STREAMING         = 0x001B,
 +      ACX_BEACON_FILTER_OPT       = 0x001F,
 +      ACX_NOISE_HIST              = 0x0021,
 +      ACX_HDK_VERSION             = 0x0022, /* ??? */
 +      ACX_PD_THRESHOLD            = 0x0023,
 +      ACX_TX_CONFIG_OPT           = 0x0024,
 +      ACX_CCA_THRESHOLD           = 0x0025,
 +      ACX_EVENT_MBOX_MASK         = 0x0026,
 +      ACX_CONN_MONIT_PARAMS       = 0x002D,
 +      ACX_CONS_TX_FAILURE         = 0x002F,
 +      ACX_BCN_DTIM_OPTIONS        = 0x0031,
 +      ACX_SG_ENABLE               = 0x0032,
 +      ACX_SG_CFG                  = 0x0033,
 +      ACX_BEACON_FILTER_TABLE     = 0x0038,
 +      ACX_ARP_IP_FILTER           = 0x0039,
 +      ACX_ROAMING_STATISTICS_TBL  = 0x003B,
 +      ACX_RATE_POLICY             = 0x003D,
 +      ACX_CTS_PROTECTION          = 0x003E,
 +      ACX_SLEEP_AUTH              = 0x003F,
 +      ACX_PREAMBLE_TYPE           = 0x0040,
 +      ACX_ERROR_CNT               = 0x0041,
 +      ACX_IBSS_FILTER             = 0x0044,
 +      ACX_SERVICE_PERIOD_TIMEOUT  = 0x0045,
 +      ACX_TSF_INFO                = 0x0046,
 +      ACX_CONFIG_PS_WMM           = 0x0049,
 +      ACX_ENABLE_RX_DATA_FILTER   = 0x004A,
 +      ACX_SET_RX_DATA_FILTER      = 0x004B,
 +      ACX_GET_DATA_FILTER_STATISTICS = 0x004C,
 +      ACX_RX_CONFIG_OPT           = 0x004E,
 +      ACX_FRAG_CFG                = 0x004F,
 +      ACX_BET_ENABLE              = 0x0050,
 +      ACX_RSSI_SNR_TRIGGER        = 0x0051,
 +      ACX_RSSI_SNR_WEIGHTS        = 0x0052,
 +      ACX_KEEP_ALIVE_MODE         = 0x0053,
 +      ACX_SET_KEEP_ALIVE_CONFIG   = 0x0054,
 +      ACX_BA_SESSION_RESPONDER_POLICY = 0x0055,
 +      ACX_BA_SESSION_INITIATOR_POLICY = 0x0056,
 +      ACX_PEER_HT_CAP             = 0x0057,
 +      ACX_HT_BSS_OPERATION        = 0x0058,
 +      ACX_COEX_ACTIVITY           = 0x0059,
 +      ACX_SET_DCO_ITRIM_PARAMS    = 0x0061,
 +      DOT11_RX_MSDU_LIFE_TIME     = 0x1004,
 +      DOT11_CUR_TX_PWR            = 0x100D,
 +      DOT11_RX_DOT11_MODE         = 0x1012,
 +      DOT11_RTS_THRESHOLD         = 0x1013,
 +      DOT11_GROUP_ADDRESS_TBL     = 0x1014,
 +      ACX_PM_CONFIG               = 0x1016,
 +
 +      MAX_DOT11_IE = DOT11_GROUP_ADDRESS_TBL,
 +
 +      MAX_IE = 0xFFFF
 +};
 +
 +
 +int wl1271_acx_wake_up_conditions(struct wl1271 *wl);
 +int wl1271_acx_sleep_auth(struct wl1271 *wl, u8 sleep_auth);
 +int wl1271_acx_tx_power(struct wl1271 *wl, int power);
 +int wl1271_acx_feature_cfg(struct wl1271 *wl);
 +int wl1271_acx_mem_map(struct wl1271 *wl,
 +                     struct acx_header *mem_map, size_t len);
 +int wl1271_acx_rx_msdu_life_time(struct wl1271 *wl);
 +int wl1271_acx_rx_config(struct wl1271 *wl, u32 config, u32 filter);
 +int wl1271_acx_pd_threshold(struct wl1271 *wl);
 +int wl1271_acx_slot(struct wl1271 *wl, enum acx_slot_type slot_time);
 +int wl1271_acx_group_address_tbl(struct wl1271 *wl, bool enable,
 +                               void *mc_list, u32 mc_list_len);
 +int wl1271_acx_service_period_timeout(struct wl1271 *wl);
 +int wl1271_acx_rts_threshold(struct wl1271 *wl, u16 rts_threshold);
 +int wl1271_acx_dco_itrim_params(struct wl1271 *wl);
 +int wl1271_acx_beacon_filter_opt(struct wl1271 *wl, bool enable_filter);
 +int wl1271_acx_beacon_filter_table(struct wl1271 *wl);
 +int wl1271_acx_conn_monit_params(struct wl1271 *wl, bool enable);
 +int wl1271_acx_sg_enable(struct wl1271 *wl, bool enable);
 +int wl1271_acx_sg_cfg(struct wl1271 *wl);
 +int wl1271_acx_cca_threshold(struct wl1271 *wl);
 +int wl1271_acx_bcn_dtim_options(struct wl1271 *wl);
 +int wl1271_acx_aid(struct wl1271 *wl, u16 aid);
 +int wl1271_acx_event_mbox_mask(struct wl1271 *wl, u32 event_mask);
 +int wl1271_acx_set_preamble(struct wl1271 *wl, enum acx_preamble_type preamble);
 +int wl1271_acx_cts_protect(struct wl1271 *wl,
 +                         enum acx_ctsprotect_type ctsprotect);
 +int wl1271_acx_statistics(struct wl1271 *wl, struct acx_statistics *stats);
 +int wl1271_acx_rate_policies(struct wl1271 *wl);
 +int wl1271_acx_ac_cfg(struct wl1271 *wl, u8 ac, u8 cw_min, u16 cw_max,
 +                    u8 aifsn, u16 txop);
 +int wl1271_acx_tid_cfg(struct wl1271 *wl, u8 queue_id, u8 channel_type,
 +                     u8 tsid, u8 ps_scheme, u8 ack_policy,
 +                     u32 apsd_conf0, u32 apsd_conf1);
 +int wl1271_acx_frag_threshold(struct wl1271 *wl, u16 frag_threshold);
 +int wl1271_acx_tx_config_options(struct wl1271 *wl);
 +int wl1271_acx_mem_cfg(struct wl1271 *wl);
 +int wl1271_acx_init_mem_config(struct wl1271 *wl);
 +int wl1271_acx_init_rx_interrupt(struct wl1271 *wl);
 +int wl1271_acx_smart_reflex(struct wl1271 *wl);
 +int wl1271_acx_bet_enable(struct wl1271 *wl, bool enable);
 +int wl1271_acx_arp_ip_filter(struct wl1271 *wl, u8 enable, __be32 address);
 +int wl1271_acx_pm_config(struct wl1271 *wl);
 +int wl1271_acx_keep_alive_mode(struct wl1271 *wl, bool enable);
 +int wl1271_acx_keep_alive_config(struct wl1271 *wl, u8 index, u8 tpl_valid);
 +int wl1271_acx_rssi_snr_trigger(struct wl1271 *wl, bool enable,
 +                              s16 thold, u8 hyst);
 +int wl1271_acx_rssi_snr_avg_weights(struct wl1271 *wl);
 +int wl1271_acx_set_ht_capabilities(struct wl1271 *wl,
 +                                  struct ieee80211_sta_ht_cap *ht_cap,
 +                                  bool allow_ht_operation);
 +int wl1271_acx_set_ht_information(struct wl1271 *wl,
 +                                 u16 ht_operation_mode);
 +int wl1271_acx_tsf_info(struct wl1271 *wl, u64 *mactime);
 +
 +#endif /* __WL1271_ACX_H__ */
index ce3d31f98c555cf8fa36171b36f3d53b59e615c0,0000000000000000000000000000000000000000..9050dd9b62d2e9ec46d3860a54b7f6781249e78e
mode 100644,000000..100644
--- /dev/null
@@@ -1,426 -1,0 +1,426 @@@
- #define WL1271_PRE_POWER_ON_SLEEP 20 /* in miliseconds */
- #define WL1271_POWER_ON_SLEEP 200 /* in miliseconds */
 +/*
 + * This file is part of wl1271
 + *
 + * Copyright (C) 1998-2009 Texas Instruments. All rights reserved.
 + * Copyright (C) 2008-2009 Nokia Corporation
 + *
 + * Contact: Luciano Coelho <luciano.coelho@nokia.com>
 + *
 + * This program is free software; you can redistribute it and/or
 + * modify it under the terms of the GNU General Public License
 + * version 2 as published by the Free Software Foundation.
 + *
 + * This program is distributed in the hope that it will be useful, but
 + * WITHOUT ANY WARRANTY; without even the implied warranty of
 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
 + * General Public License for more details.
 + *
 + * You should have received a copy of the GNU General Public License
 + * along with this program; if not, write to the Free Software
 + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
 + * 02110-1301 USA
 + *
 + */
 +
 +#ifndef __WL12XX_H__
 +#define __WL12XX_H__
 +
 +#include <linux/mutex.h>
 +#include <linux/completion.h>
 +#include <linux/spinlock.h>
 +#include <linux/list.h>
 +#include <linux/bitops.h>
 +#include <net/mac80211.h>
 +
 +#include "conf.h"
 +#include "ini.h"
 +
 +#define DRIVER_NAME "wl1271"
 +#define DRIVER_PREFIX DRIVER_NAME ": "
 +
 +enum {
 +      DEBUG_NONE      = 0,
 +      DEBUG_IRQ       = BIT(0),
 +      DEBUG_SPI       = BIT(1),
 +      DEBUG_BOOT      = BIT(2),
 +      DEBUG_MAILBOX   = BIT(3),
 +      DEBUG_TESTMODE  = BIT(4),
 +      DEBUG_EVENT     = BIT(5),
 +      DEBUG_TX        = BIT(6),
 +      DEBUG_RX        = BIT(7),
 +      DEBUG_SCAN      = BIT(8),
 +      DEBUG_CRYPT     = BIT(9),
 +      DEBUG_PSM       = BIT(10),
 +      DEBUG_MAC80211  = BIT(11),
 +      DEBUG_CMD       = BIT(12),
 +      DEBUG_ACX       = BIT(13),
 +      DEBUG_SDIO      = BIT(14),
 +      DEBUG_FILTERS   = BIT(15),
 +      DEBUG_ADHOC     = BIT(16),
 +      DEBUG_ALL       = ~0,
 +};
 +
 +extern u32 wl12xx_debug_level;
 +
 +#define DEBUG_DUMP_LIMIT 1024
 +
 +#define wl1271_error(fmt, arg...) \
 +      pr_err(DRIVER_PREFIX "ERROR " fmt "\n", ##arg)
 +
 +#define wl1271_warning(fmt, arg...) \
 +      pr_warning(DRIVER_PREFIX "WARNING " fmt "\n", ##arg)
 +
 +#define wl1271_notice(fmt, arg...) \
 +      pr_info(DRIVER_PREFIX fmt "\n", ##arg)
 +
 +#define wl1271_info(fmt, arg...) \
 +      pr_info(DRIVER_PREFIX fmt "\n", ##arg)
 +
 +#define wl1271_debug(level, fmt, arg...) \
 +      do { \
 +              if (level & wl12xx_debug_level) \
 +                      pr_debug(DRIVER_PREFIX fmt "\n", ##arg); \
 +      } while (0)
 +
 +/* TODO: use pr_debug_hex_dump when it will be available */
 +#define wl1271_dump(level, prefix, buf, len)  \
 +      do { \
 +              if (level & wl12xx_debug_level) \
 +                      print_hex_dump(KERN_DEBUG, DRIVER_PREFIX prefix, \
 +                                     DUMP_PREFIX_OFFSET, 16, 1,       \
 +                                     buf,                             \
 +                                     min_t(size_t, len, DEBUG_DUMP_LIMIT), \
 +                                     0);                              \
 +      } while (0)
 +
 +#define wl1271_dump_ascii(level, prefix, buf, len)    \
 +      do { \
 +              if (level & wl12xx_debug_level) \
 +                      print_hex_dump(KERN_DEBUG, DRIVER_PREFIX prefix, \
 +                                     DUMP_PREFIX_OFFSET, 16, 1,       \
 +                                     buf,                             \
 +                                     min_t(size_t, len, DEBUG_DUMP_LIMIT), \
 +                                     true);                           \
 +      } while (0)
 +
 +#define WL1271_DEFAULT_RX_CONFIG (CFG_UNI_FILTER_EN | \
 +                                CFG_BSSID_FILTER_EN | \
 +                                CFG_MC_FILTER_EN)
 +
 +#define WL1271_DEFAULT_RX_FILTER (CFG_RX_RCTS_ACK | CFG_RX_PRSP_EN |  \
 +                                CFG_RX_MGMT_EN | CFG_RX_DATA_EN |   \
 +                                CFG_RX_CTL_EN | CFG_RX_BCN_EN |     \
 +                                CFG_RX_AUTH_EN | CFG_RX_ASSOC_EN)
 +
 +#define WL1271_FW_NAME "wl1271-fw.bin"
 +#define WL1271_NVS_NAME "wl1271-nvs.bin"
 +
 +#define WL1271_TX_SECURITY_LO16(s) ((u16)((s) & 0xffff))
 +#define WL1271_TX_SECURITY_HI32(s) ((u32)(((s) >> 16) & 0xffffffff))
 +
 +#define WL1271_CIPHER_SUITE_GEM 0x00147201
 +
 +#define WL1271_BUSY_WORD_CNT 1
 +#define WL1271_BUSY_WORD_LEN (WL1271_BUSY_WORD_CNT * sizeof(u32))
 +
 +#define WL1271_ELP_HW_STATE_ASLEEP 0
 +#define WL1271_ELP_HW_STATE_IRQ    1
 +
 +#define WL1271_DEFAULT_BEACON_INT  100
 +#define WL1271_DEFAULT_DTIM_PERIOD 1
 +
 +#define ACX_TX_DESCRIPTORS         32
 +
 +#define WL1271_AGGR_BUFFER_SIZE (4 * PAGE_SIZE)
 +
 +enum wl1271_state {
 +      WL1271_STATE_OFF,
 +      WL1271_STATE_ON,
 +      WL1271_STATE_PLT,
 +};
 +
 +enum wl1271_partition_type {
 +      PART_DOWN,
 +      PART_WORK,
 +      PART_DRPW,
 +
 +      PART_TABLE_LEN
 +};
 +
 +struct wl1271_partition {
 +      u32 size;
 +      u32 start;
 +};
 +
 +struct wl1271_partition_set {
 +      struct wl1271_partition mem;
 +      struct wl1271_partition reg;
 +      struct wl1271_partition mem2;
 +      struct wl1271_partition mem3;
 +};
 +
 +struct wl1271;
 +
 +/* FIXME: I'm not sure about this structure name */
 +struct wl1271_chip {
 +      u32 id;
 +      char fw_ver[21];
 +};
 +
 +struct wl1271_stats {
 +      struct acx_statistics *fw_stats;
 +      unsigned long fw_stats_update;
 +
 +      unsigned int retry_count;
 +      unsigned int excessive_retries;
 +};
 +
 +#define NUM_TX_QUEUES              4
 +#define NUM_RX_PKT_DESC            8
 +
 +/* FW status registers */
 +struct wl1271_fw_status {
 +      __le32 intr;
 +      u8  fw_rx_counter;
 +      u8  drv_rx_counter;
 +      u8  reserved;
 +      u8  tx_results_counter;
 +      __le32 rx_pkt_descs[NUM_RX_PKT_DESC];
 +      __le32 tx_released_blks[NUM_TX_QUEUES];
 +      __le32 fw_localtime;
 +      __le32 padding[2];
 +} __packed;
 +
 +struct wl1271_rx_mem_pool_addr {
 +      u32 addr;
 +      u32 addr_extra;
 +};
 +
 +struct wl1271_scan {
 +      struct cfg80211_scan_request *req;
 +      bool *scanned_ch;
 +      bool failed;
 +      u8 state;
 +      u8 ssid[IW_ESSID_MAX_SIZE+1];
 +      size_t ssid_len;
 +};
 +
 +struct wl1271_if_operations {
 +      void (*read)(struct wl1271 *wl, int addr, void *buf, size_t len,
 +                   bool fixed);
 +      void (*write)(struct wl1271 *wl, int addr, void *buf, size_t len,
 +                   bool fixed);
 +      void (*reset)(struct wl1271 *wl);
 +      void (*init)(struct wl1271 *wl);
 +      int (*power)(struct wl1271 *wl, bool enable);
 +      struct device* (*dev)(struct wl1271 *wl);
 +      void (*enable_irq)(struct wl1271 *wl);
 +      void (*disable_irq)(struct wl1271 *wl);
 +};
 +
 +struct wl1271 {
 +      struct platform_device *plat_dev;
 +      struct ieee80211_hw *hw;
 +      bool mac80211_registered;
 +
 +      void *if_priv;
 +
 +      struct wl1271_if_operations *if_ops;
 +
 +      void (*set_power)(bool enable);
 +      int irq;
 +      int ref_clock;
 +
 +      spinlock_t wl_lock;
 +
 +      enum wl1271_state state;
 +      struct mutex mutex;
 +
 +#define WL1271_FLAG_STA_RATES_CHANGED  (0)
 +#define WL1271_FLAG_STA_ASSOCIATED     (1)
 +#define WL1271_FLAG_JOINED             (2)
 +#define WL1271_FLAG_GPIO_POWER         (3)
 +#define WL1271_FLAG_TX_QUEUE_STOPPED   (4)
 +#define WL1271_FLAG_IN_ELP             (5)
 +#define WL1271_FLAG_PSM                (6)
 +#define WL1271_FLAG_PSM_REQUESTED      (7)
 +#define WL1271_FLAG_IRQ_PENDING        (8)
 +#define WL1271_FLAG_IRQ_RUNNING        (9)
 +#define WL1271_FLAG_IDLE              (10)
 +#define WL1271_FLAG_IDLE_REQUESTED    (11)
 +#define WL1271_FLAG_PSPOLL_FAILURE    (12)
 +#define WL1271_FLAG_STA_STATE_SENT    (13)
 +#define WL1271_FLAG_FW_TX_BUSY        (14)
 +      unsigned long flags;
 +
 +      struct wl1271_partition_set part;
 +
 +      struct wl1271_chip chip;
 +
 +      int cmd_box_addr;
 +      int event_box_addr;
 +
 +      u8 *fw;
 +      size_t fw_len;
 +      struct wl1271_nvs_file *nvs;
 +      size_t nvs_len;
 +
 +      s8 hw_pg_ver;
 +
 +      u8 bssid[ETH_ALEN];
 +      u8 mac_addr[ETH_ALEN];
 +      u8 bss_type;
 +      u8 set_bss_type;
 +      u8 ssid[IW_ESSID_MAX_SIZE + 1];
 +      u8 ssid_len;
 +      int channel;
 +
 +      struct wl1271_acx_mem_map *target_mem_map;
 +
 +      /* Accounting for allocated / available TX blocks on HW */
 +      u32 tx_blocks_freed[NUM_TX_QUEUES];
 +      u32 tx_blocks_available;
 +      u32 tx_results_count;
 +
 +      /* Transmitted TX packets counter for chipset interface */
 +      u32 tx_packets_count;
 +
 +      /* Time-offset between host and chipset clocks */
 +      s64 time_offset;
 +
 +      /* Session counter for the chipset */
 +      int session_counter;
 +
 +      /* Frames scheduled for transmission, not handled yet */
 +      struct sk_buff_head tx_queue[NUM_TX_QUEUES];
 +      int tx_queue_count;
 +
 +      struct work_struct tx_work;
 +
 +      /* Pending TX frames */
 +      unsigned long tx_frames_map[BITS_TO_LONGS(ACX_TX_DESCRIPTORS)];
 +      struct sk_buff *tx_frames[ACX_TX_DESCRIPTORS];
 +      int tx_frames_cnt;
 +
 +      /* Security sequence number counters */
 +      u8 tx_security_last_seq;
 +      s64 tx_security_seq;
 +
 +      /* FW Rx counter */
 +      u32 rx_counter;
 +
 +      /* Rx memory pool address */
 +      struct wl1271_rx_mem_pool_addr rx_mem_pool_addr;
 +
 +      /* Intermediate buffer, used for packet aggregation */
 +      u8 *aggr_buf;
 +
 +      /* The target interrupt mask */
 +      struct work_struct irq_work;
 +
 +      /* Hardware recovery work */
 +      struct work_struct recovery_work;
 +
 +      /* The mbox event mask */
 +      u32 event_mask;
 +
 +      /* Mailbox pointers */
 +      u32 mbox_ptr[2];
 +
 +      /* Are we currently scanning */
 +      struct wl1271_scan scan;
 +      struct delayed_work scan_complete_work;
 +
 +      /* probe-req template for the current AP */
 +      struct sk_buff *probereq;
 +
 +      /* Our association ID */
 +      u16 aid;
 +
 +      /*
 +       * currently configured rate set:
 +       *      bits  0-15 - 802.11abg rates
 +       *      bits 16-23 - 802.11n   MCS index mask
 +       * support only 1 stream, thus only 8 bits for the MCS rates (0-7).
 +       */
 +      u32 sta_rate_set;
 +      u32 basic_rate_set;
 +      u32 basic_rate;
 +      u32 rate_set;
 +
 +      /* The current band */
 +      enum ieee80211_band band;
 +
 +      /* Beaconing interval (needed for ad-hoc) */
 +      u32 beacon_int;
 +
 +      /* Default key (for WEP) */
 +      u32 default_key;
 +
 +      unsigned int filters;
 +      unsigned int rx_config;
 +      unsigned int rx_filter;
 +
 +      struct completion *elp_compl;
 +      struct delayed_work elp_work;
 +      struct delayed_work pspoll_work;
 +
 +      /* counter for ps-poll delivery failures */
 +      int ps_poll_failures;
 +
 +      /* retry counter for PSM entries */
 +      u8 psm_entry_retry;
 +
 +      /* in dBm */
 +      int power_level;
 +
 +      int rssi_thold;
 +      int last_rssi_event;
 +
 +      struct wl1271_stats stats;
 +      struct dentry *rootdir;
 +
 +      __le32 buffer_32;
 +      u32 buffer_cmd;
 +      u32 buffer_busyword[WL1271_BUSY_WORD_CNT];
 +
 +      struct wl1271_fw_status *fw_status;
 +      struct wl1271_tx_hw_res_if *tx_res_if;
 +
 +      struct ieee80211_vif *vif;
 +
 +      /* Current chipset configuration */
 +      struct conf_drv_settings conf;
 +
 +      bool sg_enabled;
 +
 +      bool enable_11a;
 +
 +      struct list_head list;
 +
 +      /* Most recently reported noise in dBm */
 +      s8 noise;
 +};
 +
 +int wl1271_plt_start(struct wl1271 *wl);
 +int wl1271_plt_stop(struct wl1271 *wl);
 +
 +#define JOIN_TIMEOUT 5000 /* 5000 milliseconds to join */
 +
 +#define SESSION_COUNTER_MAX 7 /* maximum value for the session counter */
 +
 +#define WL1271_DEFAULT_POWER_LEVEL 0
 +
 +#define WL1271_TX_QUEUE_LOW_WATERMARK  10
 +#define WL1271_TX_QUEUE_HIGH_WATERMARK 25
 +
 +/* WL1271 needs a 200ms sleep after power on, and a 20ms sleep before power
 +   on in case is has been shut down shortly before */
++#define WL1271_PRE_POWER_ON_SLEEP 20 /* in milliseconds */
++#define WL1271_POWER_ON_SLEEP 200 /* in milliseconds */
 +
 +/* Macros to handle wl1271.sta_rate_set */
 +#define HW_BG_RATES_MASK      0xffff
 +#define HW_HT_RATES_OFFSET    16
 +
 +#endif
Simple merge
Simple merge
Simple merge
Simple merge
Simple merge
Simple merge
Simple merge
Simple merge
index 4e2eb92ba028f48610872ff29d40e7e22ece8c20,de989fc158dd9b8f688ca23d207d725a59c7ea76..43fa986bb5860b5d932365036dbf8098867b20a5
@@@ -5646,9 -5682,9 +5646,9 @@@ bfa_cb_lps_fdisc_comp(void *bfad, void 
        switch (status) {
        case BFA_STATUS_OK:
                /*
-                * Initialiaze the V-Port fields
+                * Initialize the V-Port fields
                 */
 -              __vport_fcid(vport) = bfa_lps_get_pid(vport->lps);
 +              __vport_fcid(vport) = vport->lps->lp_pid;
                vport->vport_stats.fdisc_accepts++;
                bfa_sm_send_event(vport, BFA_FCS_VPORT_SM_RSP_OK);
                break;
Simple merge
Simple merge
Simple merge
Simple merge
Simple merge
Simple merge
Simple merge
Simple merge
Simple merge
Simple merge
Simple merge
Simple merge
Simple merge
diff --cc fs/coda/inode.c
Simple merge
diff --cc fs/ext4/ext4.h
index bab2387fba43722837b6877abfb02626943abc20,1f253a9a141d3558fb5f278793f52e881c79d708..1de65f5720336c84c27f80e66310660f846e4f31
@@@ -561,7 -561,23 +561,7 @@@ struct ext4_new_group_data 
  #define EXT4_IOC32_SETVERSION_OLD     FS_IOC32_SETVERSION
  #endif
  
- /* Max physical block we can addres w/o extents */
 -
 -/*
 - *  Mount options
 - */
 -struct ext4_mount_options {
 -      unsigned long s_mount_opt;
 -      uid_t s_resuid;
 -      gid_t s_resgid;
 -      unsigned long s_commit_interval;
 -      u32 s_min_batch_time, s_max_batch_time;
 -#ifdef CONFIG_QUOTA
 -      int s_jquota_fmt;
 -      char *s_qf_names[MAXQUOTAS];
 -#endif
 -};
 -
+ /* Max physical block we can address w/o extents */
  #define EXT4_MAX_BLOCK_FILE_PHYS      0xFFFFFFFF
  
  /*
Simple merge
diff --cc fs/ext4/inode.c
Simple merge
Simple merge
Simple merge
Simple merge
diff --cc init/Kconfig
Simple merge
Simple merge
Simple merge
Simple merge
Simple merge
diff --cc kernel/sched.c
Simple merge
Simple merge
Simple merge
diff --cc lib/nlattr.c
Simple merge
Simple merge
diff --cc mm/percpu.c
Simple merge
diff --cc net/Kconfig
Simple merge
diff --cc net/core/dev.c
Simple merge
Simple merge
Simple merge
Simple merge
Simple merge
Simple merge
Simple merge