#include <common_def.h>
+/* CPU topology */
+#define PLAT_MAX_CORES_PER_CLUSTER 2
+#define PLAT_CLUSTER_COUNT 12
+#define PLATFORM_CORE_COUNT (PLAT_CLUSTER_COUNT * \
+ PLAT_MAX_CORES_PER_CLUSTER)
+
#define CACHE_WRITEBACK_SHIFT 6
#define CACHE_WRITEBACK_GRANULE (1 << CACHE_WRITEBACK_SHIFT)
--- /dev/null
+/*
+ * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef __SQ_COMMON_H__
+#define __SQ_COMMON_H__
+
+#include <sys/types.h>
+
+unsigned int sq_calc_core_pos(u_register_t mpidr);
+
+#endif /* __SQ_COMMON_H__ */
--- /dev/null
+/*
+ * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <arch.h>
+#include <sq_common.h>
+#include <platform_def.h>
+
+unsigned char sq_pd_tree_desc[PLAT_CLUSTER_COUNT + 1];
+
+int plat_core_pos_by_mpidr(u_register_t mpidr)
+{
+ unsigned int cluster_id, cpu_id;
+
+ cluster_id = (mpidr >> MPIDR_AFF1_SHIFT) & MPIDR_AFFLVL_MASK;
+ if (cluster_id >= PLAT_CLUSTER_COUNT)
+ return -1;
+
+ cpu_id = (mpidr >> MPIDR_AFF0_SHIFT) & MPIDR_AFFLVL_MASK;
+ if (cpu_id >= PLAT_MAX_CORES_PER_CLUSTER)
+ return -1;
+
+ return sq_calc_core_pos(mpidr);
+}
+
+const unsigned char *plat_get_power_domain_tree_desc(void)
+{
+ int i;
+
+ sq_pd_tree_desc[0] = PLAT_CLUSTER_COUNT;
+
+ for (i = 0; i < PLAT_CLUSTER_COUNT; i++)
+ sq_pd_tree_desc[i + 1] = PLAT_MAX_CORES_PER_CLUSTER;
+
+ return sq_pd_tree_desc;
+}