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(parent: 033d9b6) | patch
riscv64: add new port on 5.10 riscv-202103
authorZoltan HERPAI <wigyori@uid0.hu>
Sun, 16 Dec 2018 10:05:58 +0000 (11:05 +0100)
committerZoltan HERPAI <wigyori@uid0.hu>
Thu, 4 Mar 2021 00:04:45 +0000 (01:04 +0100)
commitb1d829a8f7ad375a3b9aeac30f277553154d6f8f
treec72cff10566f0d2496b40a2d40aca16e85c76460tree | snapshot
parent033d9b657d0d6c7b2f31dc809b09bea5b117c2f7commit | diff
riscv64: add new port on 5.10

RISC-V is a new CPU architecture aimed to be fully free and open. This
target will add support for it, based on 4.19.

Supports running on:
 - HiFive Unleashed (which is the most known devboard for this arch)
 - QEMU (support is available in mainline qemu)
Further devboards are expected given the interest in this new arch.

An SD-card image is generated, where the partitions are required to have
specific type codes. Compared to earlier branches for this target, BBL
support is removed, giving way for OpenSBI.

Signed-off-by: Zoltan HERPAI <wigyori@uid0.hu>
target/linux/riscv64/Makefile [new file with mode: 0644] blob
target/linux/riscv64/base-files/etc/board.d/02_network [new file with mode: 0644] blob
target/linux/riscv64/base-files/etc/inittab [new file with mode: 0644] blob
target/linux/riscv64/base-files/lib/preinit/80_debug [new file with mode: 0644] blob
target/linux/riscv64/config-5.10 [new file with mode: 0644] blob
target/linux/riscv64/image/Config.in [new file with mode: 0644] blob
target/linux/riscv64/image/Makefile [new file with mode: 0644] blob
target/linux/riscv64/image/gen_riscv64_sdcard_img.sh [new file with mode: 0755] blob
Staging tree of Zoltan Herpai