drm/amd/display: Embed DCN2 SOC bounding box
authorNicholas Kazlauskas <nicholas.kazlauskas@amd.com>
Tue, 30 Jul 2019 13:08:34 +0000 (09:08 -0400)
committerAlex Deucher <alexander.deucher@amd.com>
Wed, 31 Jul 2019 04:48:33 +0000 (23:48 -0500)
commitfb6959ae50176758a073687dbb081d26521f4576
tree1ce8faea569bfe186c0671a7d7041bdbf53d7686
parent1a2c29bce06083e0f53f3a328f0bb43a2856b622
drm/amd/display: Embed DCN2 SOC bounding box

[Why]
In order to support uclk switching on NV10 the SOC bounding box
needs to be updated.

[How]
We currently read the constants from the gpu info FW, but supporting
workarounds in DC for different versions of the FW adds additional
complexity to the codebase.

NV10 has been released so it's cleanest to keep the bounding box and
source code in sync by embedding the bounding box like we do for
other ASICs.

Fixes: 02316e963a5a ("drm/amd/display: Force uclk to max for every state")
Signed-off-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c