Use secure timer to generate S-EL1 interrupts
authorAchin Gupta <achin.gupta@arm.com>
Fri, 9 May 2014 11:00:17 +0000 (12:00 +0100)
committerAchin Gupta <achin.gupta@arm.com>
Thu, 22 May 2014 16:47:20 +0000 (17:47 +0100)
commitfa9c08b7d117cb736911288668f9fd987505b4e3
treec935c5a3ab474265b51c2b1c8c53ec798e9fee2c
parentdce74b891e0e6020d0a18384e32f280133631d9b
Use secure timer to generate S-EL1 interrupts

This patch adds support in the TSP to program the secure physical
generic timer to generate a EL-1 interrupt every half second. It also
adds support for maintaining the timer state across power management
operations. The TSPD ensures that S-EL1 can access the timer by
programming the SCR_EL3.ST bit.

This patch does not actually enable the timer. This will be done in a
subsequent patch once the complete framework for handling S-EL1
interrupts is in place.

Change-Id: I1b3985cfb50262f60824be3a51c6314ce90571bc
bl32/tsp/tsp.mk
bl32/tsp/tsp_timer.c [new file with mode: 0644]
include/bl32/payloads/tsp.h
include/lib/aarch64/arch.h
include/lib/aarch64/arch_helpers.h
lib/aarch64/sysreg_helpers.S
services/spd/tspd/tspd_common.c